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Journal articles on the topic 'Delay models for CMOS circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Dokic, Branko, Tatjana Pesic-Brdjanin, and Rados Dabic. "Analytic models of CMOS logic in various regimes." Serbian Journal of Electrical Engineering 11, no. 2 (2014): 269–90. http://dx.doi.org/10.2298/sjee140106022d.

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In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS) have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

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2

Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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3

Jang, Ikchan, Jintae Kim, and SoYoung Kim. "Accurate delay models of CMOS CML circuits for design optimization." Analog Integrated Circuits and Signal Processing 82, no. 1 (December 5, 2014): 297–307. http://dx.doi.org/10.1007/s10470-014-0460-4.

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4

Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies." Crystals 11, no. 9 (September 21, 2021): 1150. http://dx.doi.org/10.3390/cryst11091150.

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All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

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5

Esonu, M. O., D. Al-Khalili, and C. Rozon. "Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits." VLSI Design 1, no. 4 (January 1, 1994): 261–76. http://dx.doi.org/10.1155/1994/70696.

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The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise Margin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent ECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used.

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6

Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

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7

Sharroush, Sherif. "Optimizing the Performance of MOS Stacks." Iraqi Journal for Electrical and Electronic Engineering 16, no. 1 (June 7, 2020): 85–98. http://dx.doi.org/10.37917/ijeee.16.1.11.

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CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

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8

Embabi, S. H. K., and R. Damodaran. "Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 9 (1994): 1132–42. http://dx.doi.org/10.1109/43.310902.

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9

Długosz, Rafał, Andrzej Rydlewski, and Tomasz Talaśka. "Novel, low power, nonlinear dilatation and erosion filters realized in the CMOS technology." Facta universitatis - series: Electronics and Energetics 28, no. 2 (2015): 237–49. http://dx.doi.org/10.2298/fuee1502237d.

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In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18?m technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120?C, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively.

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10

Karthikeyan, A., and P. S. Mallick. "Buffer for High Performance in CNT Based VLSI Interconnects." Advanced Science Letters 24, no. 8 (August 1, 2018): 5975–81. http://dx.doi.org/10.1166/asl.2018.12230.

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Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

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11

Hoppe, B., G. Neuendorf, D. Schmitt-Landsiedel, and W. Specks. "Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 3 (March 1990): 236–47. http://dx.doi.org/10.1109/43.46799.

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12

VOYIATZIS, I., and D. KEHAGIAS. "A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT." Journal of Circuits, Systems and Computers 15, no. 05 (October 2006): 739–56. http://dx.doi.org/10.1142/s0218126606003350.

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Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

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13

Nikhil, R., G. V. S. Veerendra, J. Rahul M. S. Sri Harsha, and Dr V. S. V. Prabhakar. "Implementation of time efficient hybrid multiplier for FFT computation." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.7.10755.

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Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.

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14

Geißler, R., and H. J. Pfleiderer. "Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern." Advances in Radio Science 1 (May 5, 2003): 273–78. http://dx.doi.org/10.5194/ars-1-273-2003.

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Abstract. In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference values extracted from SPICE simulations, the model achieves a typical precision of 5%.

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15

Park, Chester Sungchung, Sunwoo Kim, Jooho Wang, and Sungkyung Park. "Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation." Electronics 10, no. 3 (January 20, 2021): 231. http://dx.doi.org/10.3390/electronics10030231.

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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Patel, Pramod Kumar, M. M. Malik, and Tarun Kumar Gutpa. "A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology." Circuit World 46, no. 3 (March 23, 2020): 203–14. http://dx.doi.org/10.1108/cw-06-2019-0054.

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Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells. Design/methodology/approach This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue. Findings The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart. Research limitations/implications Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit. Practical implications GNRFET devices are suitable for implementing low power and high density SRAM cell. Social implications The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices. Originality/value This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

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17

Ding, Ning, Yusong Mu, Yuping Guo, Teng Chen, and Yuchun Chang. "A 6.4-GS/s 10-b Time-Interleaved SAR ADC with Time-Skew Immune Sampling Network in 28-nm CMOS." Journal of Circuits, Systems and Computers 29, no. 16 (July 27, 2020): 2050264. http://dx.doi.org/10.1142/s0218126620502643.

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This paper presents a 6.4-GS/s 16-way 10-bit time-interleaved (TI) SAR ADC for wideband wireless applications. A two-stage master–slave hierarchical sampling network, which is immune to the time skew of multi-phase clocks, is introduced to avoid the time-skew calibration for design simplicity and hardware efficiency. To perform low distortion and fast sampling at acceptable power consumption, a linearity- and energy efficiency-improved track-and-hold (T&H) buffer with current-feedback compensation scheme is proposed. Accompanied by its low-output-impedance feature, the buffer obtains adequate bandwidth which can cover the entire ADC Nyquist sampling range. Moreover, the split capacitor DAC combined with a novel nonbinary algorithm is adopted in single-channel ADC, enabling a shorter DAC settling time as well as less switching energy. Capacitor mismatch effect with related design trade-off is discussed and behavior models are built to evaluate the effect of capacitor mismatch on ENOB. An asynchronous self-triggered SAR logic is designed and optimized to minimize the delay on logic paths to match up the acceleration on DAC and comparator. With these proposed techniques, the 10-b sub-ADC achieves a 400-MHz conversion rate with only 3.5-mW power consumption. The circuit is designed and simulated in TSMC 28 HPC process and the results show that the overall ADC achieves 54.6-dB SNDR and 58.1-dB SFDR at Nyquist input while consuming 127-mW power from 1-V/1.5-V supply and achieving a Walden FoM of 45[Formula: see text]fJ/conv-step.

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18

Milovanović, Dragiša P., and Vančo B. Litovski. "Fault models of CMOS circuits." Microelectronics Reliability 34, no. 5 (May 1994): 883–96. http://dx.doi.org/10.1016/0026-2714(94)90012-4.

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19

Samanta, Jagannath, and Bishnu Prasad De. "Delay analysis of UDSM CMOS VLSI circuits." Procedia Engineering 30 (2012): 135–43. http://dx.doi.org/10.1016/j.proeng.2012.01.844.

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20

Seckin, U., and Chih-Kong Ken Yang. "A Comprehensive Delay Model for CMOS CML Circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 9 (October 2008): 2608–18. http://dx.doi.org/10.1109/tcsi.2008.920069.

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21

Vemuru, Srinivasa. "Delay-Macromodelling Of Cmos Transmission-Gate-Based-Circuits." International Journal of Modelling and Simulation 15, no. 3 (January 1995): 90–97. http://dx.doi.org/10.1080/02286203.1995.11760258.

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22

N Md, Mohasinul Huq, Mohan Das S, and Bilal N Md. "Estimation of Leakage Power and Delay in CMOS Circuits." International Journal of Engineering Technology and Management Sciences 4, no. 7 (November 28, 2020): 14–19. http://dx.doi.org/10.46647/ijetms.2020.v04i07.003.

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This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

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23

Deng, A. C., and Y. C. Shiau. "Generic linear RC delay modeling for digital CMOS circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 4 (April 1990): 367–76. http://dx.doi.org/10.1109/43.45868.

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24

Deng, A. C. "Piecewise-linear timing delay modeling for digital CMOS circuits." IEEE Transactions on Circuits and Systems 35, no. 10 (1988): 1330–34. http://dx.doi.org/10.1109/31.7609.

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Kim, Dong-Wook, and Tae-Yong Choi. "Delay Time Estimation Model for Large Digital CMOS Circuits." VLSI Design 11, no. 2 (January 1, 2000): 161–73. http://dx.doi.org/10.1155/2000/18189.

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Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.

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Ejlali, Alireza, and Seyed Ghassem Miremadi. "Emulating switch-level models of CMOS circuits." Microelectronic Engineering 84, no. 2 (February 2007): 204–12. http://dx.doi.org/10.1016/j.mee.2006.02.005.

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Marranghello, Felipe S., André I. Reis, and Renato P. Ribas. "Improving Analytical Delay Modelingfor CMOS Inverters." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 123–34. http://dx.doi.org/10.29292/jics.v10i2.414.

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Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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Yelamarthi, Kumar, and Chien-In Henry Chen. "Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations." VLSI Design 2010 (March 7, 2010): 1–13. http://dx.doi.org/10.1155/2010/230783.

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The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

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Pomeranz, Irith, and Sudhakar M. Reddy. "Delay fault models for VLSI circuits." Integration 26, no. 1-2 (December 1998): 21–40. http://dx.doi.org/10.1016/s0167-9260(98)00019-4.

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Panwar, Shikha, Mayuresh Piske, and Aatreya Vivek Madgula. "Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits." VLSI Design 2014 (July 15, 2014): 1–5. http://dx.doi.org/10.1155/2014/380362.

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This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

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Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

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Tayal, Shubham, and Sunil Jadav. "Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control." Sensor Letters 18, no. 3 (March 1, 2020): 210–15. http://dx.doi.org/10.1166/sl.2020.4211.

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Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.

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Carlson, B. S., and Suh-Juch Lee. "Delay optimization of digital CMOS VLSI circuits by transistor reordering." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 10 (1995): 1183–92. http://dx.doi.org/10.1109/43.466335.

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Kumar, R., and V. Kursun. "Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 10 (October 2006): 1078–82. http://dx.doi.org/10.1109/tcsii.2006.882218.

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Aylapogu, Pramod Kumar, B. L. V. S. S. Aditya, G. Sony, Ch Prasanna, A. Satish, G. Sony, G. Sony, et al. "Estimation of power and delay in CMOS circuits using LCT." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 990. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp990-998.

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<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s</p>

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Kumar, Manoj, Sandeep K. Arya, and Sujata Pandey. "Low power CMOS full adder design with body biasing approach." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 75–80. http://dx.doi.org/10.29292/jics.v6i1.341.

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In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

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Al-Arian, S., and D. Agrawal. "Physical failures and fault models of CMOS circuits." IEEE Transactions on Circuits and Systems 34, no. 3 (March 1987): 269–79. http://dx.doi.org/10.1109/tcs.1987.1086138.

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (November 11, 2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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Jaikumar, R., and P. Poongodi. "Noise measurement in high-speed domino pseudo-CMOS keeper." Measurement and Control 52, no. 1-2 (November 28, 2018): 20–27. http://dx.doi.org/10.1177/0020294018813642.

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Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

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Sayed, Shimaa Ibrahim, Mostafa Mamdouh Abutaleb, and Zaki Bassuoni Nossair. "Optimization of CNFET Parameters for High Performance Digital Circuits." Advances in Materials Science and Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/6303725.

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The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

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Bundalo, Dusanka, Branimir Ðordjevic, and Zlatko Bundalo. "Quaternary regenerative CMOS logic circuits with high-impedance output state." Facta universitatis - series: Electronics and Energetics 18, no. 3 (2005): 505–14. http://dx.doi.org/10.2298/fuee0503505b.

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Principles and possibilities of synthesis and design of quaternary multiple valued regenerative CMOS logic circuits with high-impedance output state are de- scribed and proposed in the paper. Two principles of synthesis and implementation of CMOS regenerative quaternary multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. The schemes of such logic circuits are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.

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Gupta, Kirti, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, and Maneesha Gupta. "New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic." Journal of Electrical and Computer Engineering 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/670508.

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Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

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HAGIWARA, Shiho, Takashi SATO, and Kazuya MASU. "Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 4 (2009): 1031–38. http://dx.doi.org/10.1587/transfun.e92.a.1031.

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Subbian, Vignesh, and FatDuen Ho. "Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors." IETE Journal of Research 58, no. 1 (2012): 24. http://dx.doi.org/10.4103/0377-2063.94078.

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Zasio, John. "4587480 Delay testing method for CMOS LSI and VLSI integrated circuits." Microelectronics Reliability 27, no. 1 (January 1987): 197. http://dx.doi.org/10.1016/0026-2714(87)90752-9.

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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Djordjevic. "Multiple-valued cmos logic circuits with high-impedance output state." Facta universitatis - series: Electronics and Energetics 15, no. 3 (2002): 371–83. http://dx.doi.org/10.2298/fuee0203371b.

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Principles and possibilities of synthesis and design of bus interface circuits with high-impedance output state in multiple-valued logic systems are described and proposed in the paper. The general principles for implementation of such circuits are considered first. Then the methods for synthesis and design of logic circuits with high-impedance output state in multiple-valued CMOS logic systems with any logic basis are proposed and described. Two principles of synthesis and implementation of CMOS multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. As an example, the schemes of such CMOS multiple-valued logic circuits with the logic basis of 5 (quaternary multiple-valued logic circuits) are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.

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Prasad, Vikash, and Debaprasad Das. "A Review on MOSFET-Like CNTFETs." Science & Technology Journal 4, no. 2 (July 1, 2016): 124–29. http://dx.doi.org/10.22232/stj.2016.04.02.06.

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Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

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Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (January 1, 2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

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We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

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Lalgudi, K. N., and M. C. Papaefthymiou. "Retiming edge-triggered circuits under general delay models." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 12 (1997): 1393–408. http://dx.doi.org/10.1109/43.664222.

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Wróblewski, Artur, Christian V. Schimpfle, Otto Schumacher, and Josef A. Nossek. "Minimizing Spurious Switching Activities with Transistor Sizing." VLSI Design 15, no. 2 (January 1, 2002): 537–45. http://dx.doi.org/10.1080/1065514021000012156.

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In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows equalizing different path delays without influencing the total delay of the circuit. Unfortunately, not only the delay, but also power consumption circuits depend on the transistor sizes. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence.

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