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Relevant bibliographies by topics / Delta Sigma Analog to Digital Conversion

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Academic literature on the topic 'Delta Sigma Analog to Digital Conversion'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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Journal articles on the topic "Delta Sigma Analog to Digital Conversion"

1

Jantzi, S., R. Schreier, and M. Snelgrove. "Bandpass sigma-delta analog-to-digital conversion." IEEE Transactions on Circuits and Systems 38, no. 11 (1991): 1406–9. http://dx.doi.org/10.1109/31.99179.

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Kumar, R. S. Ashwin, Debasish Behera, and Nagendra Krishnapura. "Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 11 (November 2018): 3651–61. http://dx.doi.org/10.1109/tcsi.2018.2854707.

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Bryukhanov, Yu A., and Yu A. Lukashevich. "Nonlinear distortions caused by sigma‒delta analog-digital conversion of signals." Journal of Communications Technology and Electronics 62, no. 3 (March 2017): 219–28. http://dx.doi.org/10.1134/s1064226917030044.

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Siahmakoun, Azad, Pablo Constanzo-Caso, and Erin Reeves. "Photonic asynchronous delta-sigma modulator system for analog-to-digital conversion." Microwave and Optical Technology Letters 54, no. 5 (March 13, 2012): 1287–92. http://dx.doi.org/10.1002/mop.26760.

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WAN, KAREN, GIGI CHAN, WILLIAM WONG, KAM CHUEN WAN, BRYCE YAU, ANDY WU, DAVID KWONG, and ANDREA BASCHIROTTO. "A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340012. http://dx.doi.org/10.1142/s0218126613400124.

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A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

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Zhao, Ying Kai, Liang Yin, Zhao Tong Liu, Wei Ping Chen, and Xiao Wei Liu. "A 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope." Key Engineering Materials 645-646 (May 2015): 605–9. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.605.

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In this paper, a 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope is proposedin order to enhance the precision of the digital to analog converter level.The interpolation filterhas achieved 64 times interpolation function,using three cascaded manner, it employs three level cascaded of FIR filterstructure. It achieves a 64 times oversampling feature. The signalbandwidth of the designs interpolation filter is 100 kHz, SNR reach 106dB. Fifth-order single-loop structure CIFB achieve noise shaping modulator function to verify the stability of the system, after the completion of CSD coefficient coding, signal to noise ratio reached 119.7dB, effective bits reached 19.59. The switched capacitor technology actualize analog reconstruction filter module, and using a typically switched capacitor DAC achieved high jump "0, 1" digital signal is converted into an analog signal, the digital-analog conversion achieved.

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Lammers, Mark, Alexander M. Powell, and Özgür Yılmaz. "Alternative dual frames for digital-to-analog conversion in sigma–delta quantization." Advances in Computational Mathematics 32, no. 1 (July 19, 2008): 73–102. http://dx.doi.org/10.1007/s10444-008-9088-1.

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Kurikov, S. F., D. A. Prilutskij, and S. V. Selishchev. "Use of analog-to-digital sigma-delta conversion technology in digital multi-channel electrocardiographs." Computer Standards & Interfaces 21, no. 2 (June 1999): 99. http://dx.doi.org/10.1016/s0920-5489(99)91924-4.

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Yin, Y., H. Klar, and P. Wennekers. "A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator." Advances in Radio Science 3 (May 12, 2005): 277–80. http://dx.doi.org/10.5194/ars-3-277-2005.

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Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.

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DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

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Dissertations / Theses on the topic "Delta Sigma Analog to Digital Conversion"

1

Louis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.

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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.

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Kim, Daeik D. "Design of Robust and Flexible On-chip Analog-to-Digital Conversion Architecture." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4773.

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This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

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Itskovich, Mikhail. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34901.

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The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption. This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator.
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Abcarius, John 1972. "High-speed low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20898.

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As digital electronics becomes increasingly popular, the need for efficient data conversion to provide the link to our analog world grows all the more important. To sustain the current rate of technological advancement, the requirements on the data conversion systems are becoming more stringent. Wireless communication systems demand high speed, high performance analog-to-digital conversion front-ends. Furthermore, consumers demand quality electronics at low cost, which precludes the use of expensive analog processes.
This thesis investigates the potential of DeltaSigma modulation techniques in addressing both of these issues through the design, implementation and experimentation of several prototype integrated circuits. Delta-Sigma modulation has recently become widely recognized for its ability to perform high performance data conversion without the use of high precision components. To extend these benefits to wireless applications, a novel eighth-order bandpass DeltaSigma modulator for A/D conversion will be presented. The modulator design is developed beginning at the signal processing level and realized in a 0.8mu BiCMOS process using the switched-capacitor (SC) technique. To address the cost issue, the design of a data conversion system based on the DeltaSigma modulation technique using an economical purely digital CMOS implementation is investigated. The distortion performance of experimental prototypes implemented using switched-capacitor (with capacitors realized using MOSFETs) and switched-current techniques is assessed.
This work therefore contributes to the ongoing drive to improve the performance and applicability of the DeltaSigma modulation technique in meeting modern-day data conversion needs.

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Abcarius, John. "High-speed/low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0027/MQ50588.pdf.

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7

Davis, Janet M. (Janet Marie) Carleton University Dissertation Engineering Electrical. "Comparison of oversampled sigma delta modulators for analog to digital conversion in digital subscriber loops." Ottawa, 1987.

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8

Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.

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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs.

QC 20150422

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Cheng, Yongjie. "Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1561.pdf.

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Chopp, Philip. "Frequency-translating delta-sigma modulation for bandpass analog-to-digital conversion of high- frequency signals." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110454.

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A traditional heterodyne receiver downconverts its input signal to one or more intermediate frequencies (IFs) before digitizing it at baseband. In a digital-IF receiver, the input signal is digitized directly at an IF using a bandpass analog-to-digital converter (ADC). Accordingly, the digital-IF receiver replaces the image-reject mixers and baseband filters of a heterodyne receiver with accurate and effcient digital functions, and therefore provides greater potential for reconfigurability. In order to maximize the advantages of a digital-IF receiver, a common design objective is to position the bandpass ADC as close as possible to the antenna, and to operate on the input signal at a high IF.A bandpass ADC is effciently implemented using a delta-sigma modulator, which can provide high-resolution A/D (analog-to-digital) conversion over a relatively narrow band around an IF. In order to operate on high-IF signals, conventional bandpass delta-sigma modulators require high-frequency filters and high sampling rates, which can result in high sensitivity to circuit non-idealities and high power consumption. These disadvantages are addressed by the frequency-translating delta-sigma modulator, which uses downconversion mixing inside its delta-sigma loop to process high-IF signals using low sampling rates and primarily low-frequency filters.This thesis investigates frequency-translating delta-sigma modulators for direct A/D conversion of high-IF signals. It first analyses the system architecture and performance limitations of an existing type of frequency-translating delta-sigma modulator that is based on image-reject mixing. This analysis is supported by an initial study on the effect of timing errors in a conventional delta-sigma modulator. The thesis then introduces a novel frequency-translating delta-sigma modulator that is based on single-path mixing. The advantages of the presented single-path architecture are demonstrated using an experimental delta-sigma modulator.The experimental delta-sigma modulator is designed to digitize a 4 MHz input-signal band that is centred at an IF of 225 MHz. It uses a local oscillation signal with a frequency of 200 MHz to downconvert this input-signal band to an IF of 25 MHz inside its delta-sigma loop, and samples at 100 MHz. The experimental prototype was fabricated in a standard 65 nm CMOS process. It achieves a peak SNDR of 55 dB and a dynamic range of 57.5 dB, while consuming 13 mW from a 1-V power supply. It has a full-scale range of 700 mVp-p.
Un recepteur heterodyne traditionnel transpose un signal en entree vers une ou plusieurs frequences intermediaires (FI) avant de le numeriser a la bande de base. Dans un recepteur numerique FI, le signal en entree est numerise directement a la frequence FI a l'aide d'un convertisseur analogique-numerique passe-bande. Par consequent, le recepteur numerique FI remplace les melangeurs de rejection d'image et les filtres a bande de base d'un recepteur heterodyne traditionnel par des fonctions numeriques precises et efficaces. De ce fait, le recepteur numerique FI offre plus de possibilites de reconfiguration. Afin de maximiser les avantages d'un recepteur numerique FI, un objectif de conception frequent consiste a placer le convertisseur analogique-numerique passe-bande aussi pres que possible de l'antenne et de numeriser le signal en entree a une frequence FI elevee.Un convertisseur analogique-numerique passe-bande peut etre realise efficacement en utilisant un modulateur delta-sigma. En effet, ce dernier procure une conversion A/N (analogique-numerique) a haute resolution sur une bande relativement restreinte centree autour d'une frequence FI. Afin de fonctionner sur des signaux a frequences FI elevees, les modulateurs delta-sigma passe-bande classiques requierent des filtres hautes-frequences et des frequences d'echantillonnage elevees, ce qui peut les rendre tres sensibles aux non-idealites du circuit et mener a une consommation electrique importante. Il est possible de remedier a ces inconvenients en utilisant un modulateur delta-sigma a transposition de frequence. En effet, ce dernier utilise des melangeurs dans sa boucle delta-sigma pour traiter des signaux a frequence FI elevee a des frequences d'echantillonnage faibles avec principalement des filtres basses-frequences.Cette these etudie l'utilisation de modulateurs delta-sigma a transposition de frequence pour une conversion A/N directe de signaux a frequence FI elevee. Elle analyse d'abord l'architecture et les limitations de performance d'un modulateur delta-sigma a transposition de frequence base sur un melangeur de rejection d'image. Cette analyse est appuyee par une etude initiale effectuee sur l'effet d'erreurs d'horloge sur un modulateur delta-sigma classique. Cette these introduit ensuite un nouveau modulateur delta-sigma a transposition de frequence base sur un melangeur de mono-trajet. Les avantages de cette architecture sont demontres a l'aide d'un prototype de modulateur delta-sigma.Le prototype de modulateur delta-sigma est concu afin de numeriser une bande de signaux en entree de 4 MHz centree autour d'une FI de 225 MHz. Il utilise un signal a oscillation locale d'une frequence de 200 MHz pour transposer cette bande de signaux en entree vers 25 MHz a l'interieur de sa boucle delta-sigma et effectue l'echantillonnage a 100 MHz. Ce prototype a ete realise en utilisant un procede CMOS standard de 65 nm. Il a un SNDR de 55 dB et une gamme dynamique de 57.5 dB tout en consommant 13 mW pour une alimentation de 1-V. Sa plage d'amplitude maximale est de 700 mVp-p.

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Books on the topic "Delta Sigma Analog to Digital Conversion"

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Jantzi, Stephen A. Bandpass sigma-delta analog-to-digital conversion. Ottawa: National Library of Canada, 1992.

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Singor, Frank Wayne. High-frequency bandpass delta-sigma analog-to digital conversion. Ottawa: National Library of Canada, 1994.

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1938-, Huijsing Johan H., ed. Continuous-time Sigma-Delta modulation for A/D conversion in radio receivers. Boston: Kluwer Academic Publishers, 2001.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D conversion: Theory, practice and fundamental performance limits. New York: Kluwer Academic, 2002.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D/ conversion: Theory, practice, and fundamental performance limits. Boston: Kluwer Academic Pub., 2000.

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1929-, Temes Gabor C., ed. Understanding delta-sigma data converters. Piscataway, NJ: IEEE Press, 2005.

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Bajdechi, Ovidiu. Systematic design of Sigma-Delta analog-to-digital converters. Boston: Kluwer Academic Publishers, 2004.

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Bajdechi, Ovidiu. Systematic design of Sigma-Delta analog-to-digital converters. Boston: Kluwer Academic Publishers, 2004.

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Bajdechi, Ovidiu, and Johan H. Huijsing. Systematic Design of Sigma-Delta Analog-to-Digital Converters. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-7946-7.

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Farrell, Ronan John. Non-linear analysis of second-order sigma-delta modulators. Dublin: University College Dublin, 1998.

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Book chapters on the topic "Delta Sigma Analog to Digital Conversion"

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Pelgrom, Marcel J. M. "Sigma–Delta Modulation." In Analog-to-Digital Conversion, 419–68. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-1371-4_9.

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Pelgrom, Marcel. "Sigma-Delta Modulation." In Analog-to-Digital Conversion, 441–506. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-44971-5_10.

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Pelgrom, Marcel J. M. "Sigma-delta Modulation." In Analog-to-Digital Conversion, 321–58. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-8888-8_9.

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Plassche, Rudy. "Sigma-delta A/D conversion." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 417–76. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_9.

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Horn, Gert, and Johan L. Huijsing. "Calibration using Sigma-Delta Analog-to-Digital Conversion." In Integrated Smart Sensors, 127–72. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2890-3_5.

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Plassche, Rudy. "Sigma-delta converters." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 413–51. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_11.

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Thurston, A. M., T. H. Pearce, M. D. Higman, and M. J. Hawksford. "Bandpass Sigma Delta A-D Conversion." In Analog Circuit Design, 259–81. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2233-8_12.

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Ohnhäuser, Frank. "Basics on Delta-Sigma Converters." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters, 207–35. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_4.

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Ohnhäuser, Frank. "Continuous-Time Delta-Sigma ADCs." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters, 237–65. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_5.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Analog-to-Digital and Digital-to-Analog Converters." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 7–18. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_2.

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Conference papers on the topic "Delta Sigma Analog to Digital Conversion"

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Taillefer, Christopher S., and Gordon W. Roberts. "Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing." In 2007 IEEE International Symposium on Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/iscas.2007.378131.

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Mandl, William J., and Carl M. Rutschow. "All-digital monolithic scanning readout based on sigma-delta analog-to-digital conversion." In Aerospace Sensing, edited by Eric R. Fossum. SPIE, 1992. http://dx.doi.org/10.1117/12.60513.

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Saxena, Vishal, Kaijun Li, Geng Zheng, and R. Jacob Baker. "A K-Delta-1-Sigma modulator for wideband analog to digital conversion." In 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2009. http://dx.doi.org/10.1109/mwscas.2009.5236069.

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Keady, A. "A new architecture for bandpass sigma delta analogue to digital conversion." In IEE Colloquium on Oversampling and Sigma-Delta Strategies for DSP (Digital Signal Processing). IEE, 1995. http://dx.doi.org/10.1049/ic:19951378.

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Yang, Zhenglin, Jie Jin, and Mingyao Wang. "A signal processing method using pulse-based intermediate values for delta-sigma analog-to-digital conversion." In 2015 IEEE International Conference on Digital Signal Processing (DSP). IEEE, 2015. http://dx.doi.org/10.1109/icdsp.2015.7251853.

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Roy, Angsuman, and R. Jacob Baker. "A passive 2^nd-order sigma-delta modulator for low-power analog-to-digital conversion." In 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908485.

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Mendis, Sunetra K., Bedabrata Pain, Robert H. Nixon, and Eric R. Fossum. "Design of a low-light-level image sensor with on-chip sigma-delta analog-to-digital conversion." In IS&T/SPIE's Symposium on Electronic Imaging: Science and Technology, edited by Morley M. Blouke. SPIE, 1993. http://dx.doi.org/10.1117/12.148606.

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Zeng, Yu-Fan, Wing-Kuen Ling, Yuping Gui, Zhijing Yang, and Qingyun Dai. "Stabilization of single bit high order interpolative sigma delta modulators for analog-to-digital conversion in wireless mobile handset based electromyogram acquisition system." In 2016 IEEE 14th International Conference on Industrial Informatics (INDIN). IEEE, 2016. http://dx.doi.org/10.1109/indin.2016.7819334.

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Katara, Arun, Sandip D. Ramteke, Abhijit V. Bapat, and Swapnil S. Jain. "Improved Delta Sigma Analog to Digital Converter." In 2011 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2011. http://dx.doi.org/10.1109/cicn.2011.93.

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Ren, Saiyu, Ray Siferd, Robert Blumgold, Nima Emami, and Robert Gillen. "Pipelined Delta Sigma Modulator Analog to Digital Converter." In 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.382009.

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Reports on the topic "Delta Sigma Analog to Digital Conversion"

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Mahurin, Eric, and Ray Siford. GaAs Sigma-Delta Modulator Modeling for Analog to Digital Converters (ADCS). Fort Belvoir, VA: Defense Technical Information Center, December 1992. http://dx.doi.org/10.21236/ada263419.

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