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Louis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.
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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
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Kim, Daeik D. "Design of Robust and Flexible On-chip Analog-to-Digital Conversion Architecture." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4773.
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This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work.
While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors.
Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs.
The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem.
A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.
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Itskovich, Mikhail. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34901.
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The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption.
This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator.Master of Science
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Abcarius, John 1972. "High-speed low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20898.
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As digital electronics becomes increasingly popular, the need for efficient data conversion to provide the link to our analog world grows all the more important. To sustain the current rate of technological advancement, the requirements on the data conversion systems are becoming more stringent. Wireless communication systems demand high speed, high performance analog-to-digital conversion front-ends. Furthermore, consumers demand quality electronics at low cost, which precludes the use of expensive analog processes.This thesis investigates the potential of DeltaSigma modulation techniques in addressing both of these issues through the design, implementation and experimentation of several prototype integrated circuits. Delta-Sigma modulation has recently become widely recognized for its ability to perform high performance data conversion without the use of high precision components. To extend these benefits to wireless applications, a novel eighth-order bandpass DeltaSigma modulator for A/D conversion will be presented. The modulator design is developed beginning at the signal processing level and realized in a 0.8mu BiCMOS process using the switched-capacitor (SC) technique. To address the cost issue, the design of a data conversion system based on the DeltaSigma modulation technique using an economical purely digital CMOS implementation is investigated. The distortion performance of experimental prototypes implemented using switched-capacitor (with capacitors realized using MOSFETs) and switched-current techniques is assessed.
This work therefore contributes to the ongoing drive to improve the performance and applicability of the DeltaSigma modulation technique in meeting modern-day data conversion needs.
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Abcarius, John. "High-speed/low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0027/MQ50588.pdf.
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Davis, Janet M. (Janet Marie) Carleton University Dissertation Engineering Electrical. "Comparison of oversampled sigma delta modulators for analog to digital conversion in digital subscriber loops." Ottawa, 1987.
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Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.
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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs.QC 20150422
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Cheng, Yongjie. "Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1561.pdf.
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Chopp, Philip. "Frequency-translating delta-sigma modulation for bandpass analog-to-digital conversion of high- frequency signals." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110454.
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A traditional heterodyne receiver downconverts its input signal to one or more intermediate frequencies (IFs) before digitizing it at baseband. In a digital-IF receiver, the input signal is digitized directly at an IF using a bandpass analog-to-digital converter (ADC). Accordingly, the digital-IF receiver replaces the image-reject mixers and baseband filters of a heterodyne receiver with accurate and effcient digital functions, and therefore provides greater potential for reconfigurability. In order to maximize the advantages of a digital-IF receiver, a common design objective is to position the bandpass ADC as close as possible to the antenna, and to operate on the input signal at a high IF.A bandpass ADC is effciently implemented using a delta-sigma modulator, which can provide high-resolution A/D (analog-to-digital) conversion over a relatively narrow band around an IF. In order to operate on high-IF signals, conventional bandpass delta-sigma modulators require high-frequency filters and high sampling rates, which can result in high sensitivity to circuit non-idealities and high power consumption. These disadvantages are addressed by the frequency-translating delta-sigma modulator, which uses downconversion mixing inside its delta-sigma loop to process high-IF signals using low sampling rates and primarily low-frequency filters.This thesis investigates frequency-translating delta-sigma modulators for direct A/D conversion of high-IF signals. It first analyses the system architecture and performance limitations of an existing type of frequency-translating delta-sigma modulator that is based on image-reject mixing. This analysis is supported by an initial study on the effect of timing errors in a conventional delta-sigma modulator. The thesis then introduces a novel frequency-translating delta-sigma modulator that is based on single-path mixing. The advantages of the presented single-path architecture are demonstrated using an experimental delta-sigma modulator.The experimental delta-sigma modulator is designed to digitize a 4 MHz input-signal band that is centred at an IF of 225 MHz. It uses a local oscillation signal with a frequency of 200 MHz to downconvert this input-signal band to an IF of 25 MHz inside its delta-sigma loop, and samples at 100 MHz. The experimental prototype was fabricated in a standard 65 nm CMOS process. It achieves a peak SNDR of 55 dB and a dynamic range of 57.5 dB, while consuming 13 mW from a 1-V power supply. It has a full-scale range of 700 mVp-p.Un recepteur heterodyne traditionnel transpose un signal en entree vers une ou plusieurs frequences intermediaires (FI) avant de le numeriser a la bande de base. Dans un recepteur numerique FI, le signal en entree est numerise directement a la frequence FI a l'aide d'un convertisseur analogique-numerique passe-bande. Par consequent, le recepteur numerique FI remplace les melangeurs de rejection d'image et les filtres a bande de base d'un recepteur heterodyne traditionnel par des fonctions numeriques precises et efficaces. De ce fait, le recepteur numerique FI offre plus de possibilites de reconfiguration. Afin de maximiser les avantages d'un recepteur numerique FI, un objectif de conception frequent consiste a placer le convertisseur analogique-numerique passe-bande aussi pres que possible de l'antenne et de numeriser le signal en entree a une frequence FI elevee.Un convertisseur analogique-numerique passe-bande peut etre realise efficacement en utilisant un modulateur delta-sigma. En effet, ce dernier procure une conversion A/N (analogique-numerique) a haute resolution sur une bande relativement restreinte centree autour d'une frequence FI. Afin de fonctionner sur des signaux a frequences FI elevees, les modulateurs delta-sigma passe-bande classiques requierent des filtres hautes-frequences et des frequences d'echantillonnage elevees, ce qui peut les rendre tres sensibles aux non-idealites du circuit et mener a une consommation electrique importante. Il est possible de remedier a ces inconvenients en utilisant un modulateur delta-sigma a transposition de frequence. En effet, ce dernier utilise des melangeurs dans sa boucle delta-sigma pour traiter des signaux a frequence FI elevee a des frequences d'echantillonnage faibles avec principalement des filtres basses-frequences.Cette these etudie l'utilisation de modulateurs delta-sigma a transposition de frequence pour une conversion A/N directe de signaux a frequence FI elevee. Elle analyse d'abord l'architecture et les limitations de performance d'un modulateur delta-sigma a transposition de frequence base sur un melangeur de rejection d'image. Cette analyse est appuyee par une etude initiale effectuee sur l'effet d'erreurs d'horloge sur un modulateur delta-sigma classique. Cette these introduit ensuite un nouveau modulateur delta-sigma a transposition de frequence base sur un melangeur de mono-trajet. Les avantages de cette architecture sont demontres a l'aide d'un prototype de modulateur delta-sigma.Le prototype de modulateur delta-sigma est concu afin de numeriser une bande de signaux en entree de 4 MHz centree autour d'une FI de 225 MHz. Il utilise un signal a oscillation locale d'une frequence de 200 MHz pour transposer cette bande de signaux en entree vers 25 MHz a l'interieur de sa boucle delta-sigma et effectue l'echantillonnage a 100 MHz. Ce prototype a ete realise en utilisant un procede CMOS standard de 65 nm. Il a un SNDR de 55 dB et une gamme dynamique de 57.5 dB tout en consommant 13 mW pour une alimentation de 1-V. Sa plage d'amplitude maximale est de 700 mVp-p.
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Bulzacchelli, John F. (John Francis). "A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/16949.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 291-305).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Direct analog-to-digital conversion of multi-GHz radio frequency (RF) signals is the ultimate goal in software radio receiver design but remains a daunting challenge for any technology. This thesis examines the potential of superconducting technology for realizing RF analog-to-digital converters (ADCs) with improved performance. A bandpass delta-sigma (AE) modulator is an attractive architecture for digitizing narrowband signals with high linearity and a large signal-to-noise ratio (SNR). The design of a superconducting bandpass AE modulator presented here exploits several advantages of superconducting electronics: the high quality factor of resonators, the high sampling rates of comparators realized with Josephson junctions, natural quantization of voltage pulses, and high circuit sensitivity. Demonstration of a superconducting circuit operating at clock rates in the tens of GHz is often hindered by the difficulty of high speed interfacing with room-temperature test equipment. In this work, a test chip with integrated acquisition memory is used to simplify high speed testing in a cryogenic environment. The small size (256 bits) of the on-chip memory severely limits the frequency resolution of spectra based on standard fast Fourier transforms. Higher resolution spectra are obtained by "segmented correlation", a new method for testing ADCs. Two different techniques have been found for clocking the superconducting modulator at frequencies in the tens of GHz. In the first approach, an optical clocking technique was developed, in which picosecond laser pulses are delivered via optical fiber to an on-chip metal-semiconductor-metal (MSM) photodiode, whose output current pulses trigger the Josephson circuitry. In the second approach, the superconducting modulator is clocked by an on-chip Josephson oscillator.
(cont.) These testing methods have been applied in the successful demonstration of a super-conducting bandpass AE modulator fabricated in a niobium integrated circuit process with 1 kA/cm2 critical current density for the Josephson junctions. At a 42.6 GHz sampling rate, the center frequency of the experimental modulator is 2.23 GHz, the measured SNR is 49 dB over a 20.8 MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2 GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6 MHz bandwidth.
by John Francis Bulzacchelli.
Ph.D.
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Garcia, Julian. "Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447.
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The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative.QC 20120528
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Li, Xiangtao. "High-speed analog-to-digital conversion in SiGe HBT technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24652.
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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Cressler, John D.; Committee Member: Laskar, Joy; Committee Member: Lee, Chin-Hui; Committee Member: Morley, Thomas; Committee Member: Papapolymerou, John
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Agah, Ali. "Design of incremental sigma-delta modulators with extended range for high-resolution analog-go-digital conversion for bioluminescence detection arrays /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Aguirre, Paulo Cesar Comassetto de. "Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/105065.
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Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit.Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.
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Penrod, Logan B. "An Exploratory Study of Pulse Width and Delta Sigma Modulators." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2278.
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This paper explores the noise shaping and noise producing qualities of Delta-Sigma Modulators (DSM) and Pulse-Width Modulators (PWM). DSM has long been dominant in the Delta Sigma Analog-to-Digital Converter (DSADC) as a noise-shaped quantizer and time discretizer, while PWM, with a similar self oscillating structure, has seen use in Class D Power Amplifiers, performing a similar function. It has been shown that the PWM in Class D Amplifiers outperforms the DSM [1], but could this advantage be used in DSADC use-cases? LTSpice simulation and printed circuit board implementation and test are used to present data on four variations of these modulators: The DSM, PWM, the out-of-loop discretized PWM (OOLDP), and the cascaded modulator. A generic form of an Nth order loop filter is presented, where three orders of this generic topology are analyzed in simulation for each modulator, and two orders are used in physical testing.
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Khushk, Hasham Ahmed. "Modulateur ΣΔ passe-haut et application dans la réception multistandards." Phd thesis, Télécom ParisTech, 2009. http://pastel.archives-ouvertes.fr/pastel-00006055.
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Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.
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Spáčil, Tomáš. "Bicí automat pro hudebníky." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-220353.
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The aim of this work is to create a functional prototype of a drum machine with sound generating using a microcontroller. Introduction is devoted to general drum machine and an analysis of its parts, principle and basic modes of operation. The following chapter deals with the principle of digital signal processing and sound generation using a microcontroller. Part of this chapter is focused on mixing using compression methods. The core of this work is to design my own block structure and overall scheme of the drum machine with a description of the parts. Followed by analysis and implementation with theoretical and practical point of view. It is mainly about presentation and description of important parts of firmware codes, DPS design and another technical documentation useful for final prototype production. The conclusion contains a summary of the results with prezentation and discussion.
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Littlehales, Patrick Anthony. "Chaos in sigma delta modulators." Thesis, Coventry University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241306.
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Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
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Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.
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Longo, Lorenzo L. Carleton University Dissertation Engineering Electrical. "Multi-stage sigma delta modulators." Ottawa, 1988.
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Berndt, Holger. "Analyse und Anwendung stochastischer Quantisierungsprinzipien in Analog/Digital-Wandlern /." Dresden : TUDpress, Verl. der Wiss, 2008. http://deposit.d-nb.de/cgi-bin/dokserv?id=3082083&prov=M&dok_var=1&dok_ext=htm.
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Tang, Yi. "Digitally-assisted sigma-delta ADCs for scaled CMOS technology /." Thesis, Connect to this title online; UW restricted, 2007. http://hdl.handle.net/1773/5958.
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Kwan, Hing-kit. "Design algorithms for delta-sigma modulator loop filter topologies." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B4150883X.
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Wang, Peng Chong. "Design of wideband switched-capacitor delta-sigma analog-to-digital converters /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20WANG.
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Ng, Sheung Yan. "A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.
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Cannillo, Francesco. "Techniques for ultra low-power FM-to-digital delta-sigma conversion." Thesis, Imperial College London, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.498018.
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Zrilić, D., D. Skendzić, S. Pajavić, R. Ghorishi, F. Fu, and G. Kandus. "A Charge-Balancing Incremental Analog to Digital Converter for Instrumental Applications." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615013.
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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, NevadaA switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.
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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
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Botteron, Yvan. "Analysis and design of higher-order sigma-delta analog-to-digital converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/mq24715.pdf.
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Early, Adrian Bruce. "A high-accuracy, DC-calibrated, monolithic, delta-sigma analog-to-digital converter." Diss., The University of Arizona, 1990. http://hdl.handle.net/10150/185072.
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Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, Delta-Sigma Analog-to-Digital converter in monolithic form. Autocalibration gives endpoint correction, and chopper stabilization minimizes the effect of parameter shifts, drift, and flicker noise. A digital filter, needed for all Delta-Sigma converters, serves as a signal processor to reject out-of-band noise and resonant responses of the external system. A 3-micron, double-poly CMOS process is used. Power requirements are +/- 5 Volts. A six-pole Gaussian IIR digital filter is chosen for good transient response and no overshoot. The filter algorithm and hardware solve the difference equations of a low-pass switched-capacitor prototype filter in digital form. Due to the low bandwidth needed, an area-efficient shift-and-add architecture is used. The area is further reduced with a novel multiplication algorithm, and the logic is reused to perform the calculations required for calibration. The system level device performance is verified in FORTRAN. The analog subcircuits are simulated over process and temperature corners in HSPICE. Measurements show differential and integral linearlity, DC accuracy and noise near the 20-bit level. Power supply rejection, and out-of-band signal attenuation are good, and the step response is monotonic. The circuit is marketed as Crystal Semiconductor CSC5503 and CSC5501 (20 and 16-bit resolutions, respectively).
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Guyton, Matthew C. (Matthew Christopher). "A low-voltage zero-crossing-based delta-sigma analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/60147.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 179-183).
A zero-crossing-based (ZCB) switched-capacitor technique is presented for operation under low power supply voltages without gate boosting. Voltage ramp generators maintain common-mode level at each integrator output. Correlated level-shifting is used to increase the effective output impedance of gated current sources. The technique was used to design a single-bit 4th-order delta-sigma analog-to-digital converter for audio applications. The prototype ADC was implemented in 0.13 [mu]m CMOS and achieves 11.9 ENOB for 60 kHz input bandwidth while dissipating 1.2 mW power.
by Matthew C. Guyton.
Ph.D.
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Huang, Li. "Calibration of a two-step Incremental Sigma-Delta Analog-to-Digital Converter." Thesis, université Paris-Saclay, 2020. http://www.theses.fr/2020UPAST041.
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Dans le cadre des imageurs Haute Définition, une tendance est d’intégrer un banc de convertisseurs analogiques-numériques jouxtant la matrice de pixel. La contrepartie est une contrainte sur le facteur de forme du convertisseur. Un convertisseur de type Sigma-Delta incrémental à base d’inverseur a été conçu lors de travaux précédents en respectant ces contraintes. Mais le placement-routage du circuit a abouti à une dégradation des performances à savoir une résolution de 9 bits au lieu des 14 bits escomptés. Une méthode de calibration s’imposait donc. Cette thèse propose plusieurs méthodes de correction implémentées par des filtres numériques appliqués sur les bits de sortie et sur des combinaisons des bits de sorties pour tenir compte de phénomènes non-linéaires observés en simulation « post-placement-routage ». Les méthodes ont été validées à partir des résultats de simulation « post-placement-routage » et permettent d’atteindre 14 bits de résolution. Pour aller plus loin, la thèse propose également un modèle des défauts du circuit au niveau des intégrateurs qui sont la partie la plus critique du circuit. Ce modèle, qui met en oeuvre des capacités parasites, rejoint les résultats de simulation « post-placement-routage » avec une très bonne précision ce qui permet d’envisager des voies d’amélioration pour une prochaine conceptionIn the context of High Definition imagers, a trend is to integrate a bank of analogto-digital converters adjacent to the pixel matrix. The disadvantage is a constraint on the form factor of the converter. An incremental inverter-based Sigma-Delta converter was designed during previous work while respecting these constraints. But the post-layout of the circuit resulted in a performance degradation namely a resolution of 9 bits instead of the expected 14 bits. A calibration method was therefore necessary. This thesis proposes several correction methods implemented by digital filters applied on the output bits and on combinations of the output bits to take account of non-linear phenomena observed in post-layout simulation. The methods have been validated from the post-layout simulation results and achieve 14-bit resolution. To go further, the thesis also proposes a model of the circuit defects at the level of the integrators which are the most critical part of the circuit. This model, which implements parasitic capacitances, joins the post-layout simulation results with a very high precision, which makes it possible to consider ways of improvement for a future design
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Tam, Yiu-Ming. "A tri-mode sigma-delta modulator for wireless receivers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TAM.
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Berndt, Holger. "Analyse und Anwendung stochastischer Quantisierungsprinzipien in Analog-Digital-Wandlern." Dresden TUDpress, 2007. http://d-nb.info/987972022/04.
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Kwan, Hing-kit, and 關興杰. "Design algorithms for delta-sigma modulator loop filter topologies." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B4150883X.
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Pan, Yaobin, and Xizhuo Li. "Design and Implementation of Sigma-Delta Converter : in Oversampling frequency." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-53052.
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Nowadays, Sigma-Delta analog-to-digital converters have been widely used in the technology of analog-to-digital conversion. It depends on the merits that the approach of Sigma-Delta has. The signal converted by oversampling is precise and well-suited in signal processing systems.This thesis mainly focuses on the principles and simulations of fundamental first-order Sigma-Delta converter, and some brief introductions about other Sigma-Delta converters.The main researches of this thesis are as follows: (1)This thesis shows not only the path about development of technology of different ADCs, but also the features and principles of these ADCs and their structures. (2)The thesis discusses how the technologies of oversampling and noise shaping are used in Sigma-Delta analog-to-digital conversion. (3)Illustrate different orders Sigma-Delta converters in different bits and their advantages and disadvantages, respectively. (4)The simulation is given in Matlab(Simulink). Typical first-order SigmaDelta converter is simulated with additional noise which will impact the input signal when implement.Sigma-Delta Converter
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Saleem, Jawad, and Abdul Mateen Malik. "REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
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The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.
The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.
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Javidan, Mohammad. "Design of high-order sigma-delta modulators for parallel analog-to-digital converters." Paris 11, 2009. http://www.theses.fr/2009PA112303.
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Les travaux menés se situent dans le contexte de la radio logicielle ou l'élément bloquant est le CAN. Une voie pour la réalisation de ce bloc, à savoir une structure EFBD, est proposé. Les différentes spécifications auxquelles un modulateur sigma-delta doit satisfaire dans ce système sont énumérés. Après avoir dressé un état de l'art des différentes technologies d'implantation du résonanteur (l'élément clé du modulateur), l'utilisation d'un résonateur à onde de Lamb est proposé. Un circuit de commande permettant la compensation de l'antirésonance et la réduction des impédances de connexions est présenté. Une méthode pour optimiser les performances de chaque modulateur en fonction des imperfections de l'électronique utilisée pour l'implémentation et en fonction de la fréquence centrale de chacun d'entre eux est développé. Il s'agit ici d'un travail conséquent et surtout nécessaire avant d'envisager la réalisation des modulateurs. Finalement la réalisation d'un modulateur d'ordre 2 est faitThis work is about design of convenient high-order continuous-time sigma-delta modulators for EFBD systems. Of all studied sorts of the resonators, Lamb wave resonators are chosen to obtain the required Q-factor. Also, solutions are proposed to overcome the issues of piezo-electique resonators. A new structure of 6th-order modulators based on weighted feedforward techniques is proposed. This structure provides moreover a filtering STF without modifying the NTF. An optimization method on the modifiable parameters of the proposed topology is developed to recover the performance of the modulator accounting analog imperfections. Finally, a second-order modulator is implemented to benchmark the proposed solutions
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Cheshmehdoost, Reza. "An alternative approach to the performance enhancements of second order sigma-delta modulator A/D convertors." Thesis, University of the West of Scotland, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336901.
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Saleem, Jawad, and Abdul Mateen Malik. "Realization of Cascade of Resonators with Distributed Feed-Back Sigma-Delta." Thesis, Linköpings universitet, Institutionen för systemteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
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The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.
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Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.
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Software radio architecture can support multiple standards by performing analogto-
digital (A/D) conversion of the radio frequency (RF) signals and running
reconfigurable software programs on the backend digital signal processor (DSP). A
slight variation of this architecture is the software defined radio architecture in which the
A/D conversion is performed on intermediate frequency (IF) signals after a single down
conversion.
The first part of this research deals with the design and implementation of a
fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters
for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC
architecture is proposed which uses only non-return to zero feedback digital to analog
converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz
and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ±
1.25 V supply.
The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF
digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA
architecture combines both cross coupling and source degeneration in order to obtain
good IM3 performance. A system level digital tuning scheme is proposed to tune the
ADC performance over process, voltage and temperature variations. The output bit
stream of the ADC is captured using an external DSP, where a software tuning algorithm
tunes the ADC parameters for best SNR performance. The IF ADC was designed in
TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V
supply.
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Puidokas, Vytenis. "Design and Research on Sigma-Delta Digital-to-Analog Converters for Audio Power Amplifiers." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2011. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20111220_133108-90590.
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The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis.Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objektas – skaitmeninis Sigma-Delta garso galios SA keitiklis, jo sandaros tobulinamas bei eksperimentinis tyrimas. Disertacijos tikslas – pasiūlyti skaitmeninio Sigma-Delta garso galios SA keitiklio interpoliatoriaus struktūros tobulinimo bei keitiklio tyrimo metodus.
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Leong, Choon-Haw. "New architectures for high-order bandpass sigma-delta modulation in digital-to-analog converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0033/MQ50636.pdf.
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Tsang, Robin Matthew 1979. "High-performance [delta sigma] analog-to-digital conversion." 2008. http://hdl.handle.net/2152/17804.
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This dissertation is about a new [delta sigma] analog-to-digital converter that offers enhanced quantization noise suppression at low oversampling ratios. This feature makes the converter attractive in applications where speed and resolution are simultaneously demanded. The converter exploits double-sampling for speed, and takes advantage of a new loop-filter to pin down passband quantization noise. A proto-type is fabricated in 0.18-[mu]m CMOS and tested. Results show that at 200-MS/s, the converter achieves an effective number of bits (ENOB) of 12.2-b in a 12.5-MHz signal band while consuming 89-mW from a 1.8-V supply. Using a common performance metric that takes into account of ENOB and signal bandwidth, the prototype outperforms all previously-reported IEEE switched-capacitor [delta sigma] modulators.text
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Hamilton, Joseph Garrett. "VCO-based analog-to-digital conversion." 2012. http://hdl.handle.net/2152/22041.
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This dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented.text
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Ranjbar, Mohammad. "Power efficient continuous-time delta-sigma modulator architectures for wideband analog to digital conversion." 2012. https://scholarworks.umass.edu/dissertations/AAI3518412.
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This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.
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Nowacki, Błażej. "Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits." Doctoral thesis, 2016. http://hdl.handle.net/10362/18507.
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This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date.
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Ghosh, Anjana. "Decimation Filtering For Complex Sigma Delta Analog To Digital Conversion In A Low-IF Receiver." Thesis, 2005. http://etd.iisc.ernet.in/handle/2005/1399.
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