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Journal articles on the topic 'Delta Sigma Analog to Digital Conversion'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Jantzi, S., R. Schreier, and M. Snelgrove. "Bandpass sigma-delta analog-to-digital conversion." IEEE Transactions on Circuits and Systems 38, no. 11 (1991): 1406–9. http://dx.doi.org/10.1109/31.99179.

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2

Kumar, R. S. Ashwin, Debasish Behera, and Nagendra Krishnapura. "Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 11 (November 2018): 3651–61. http://dx.doi.org/10.1109/tcsi.2018.2854707.

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3

Bryukhanov, Yu A., and Yu A. Lukashevich. "Nonlinear distortions caused by sigma‒delta analog-digital conversion of signals." Journal of Communications Technology and Electronics 62, no. 3 (March 2017): 219–28. http://dx.doi.org/10.1134/s1064226917030044.

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4

Siahmakoun, Azad, Pablo Constanzo-Caso, and Erin Reeves. "Photonic asynchronous delta-sigma modulator system for analog-to-digital conversion." Microwave and Optical Technology Letters 54, no. 5 (March 13, 2012): 1287–92. http://dx.doi.org/10.1002/mop.26760.

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5

WAN, KAREN, GIGI CHAN, WILLIAM WONG, KAM CHUEN WAN, BRYCE YAU, ANDY WU, DAVID KWONG, and ANDREA BASCHIROTTO. "A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340012. http://dx.doi.org/10.1142/s0218126613400124.

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A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

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6

Zhao, Ying Kai, Liang Yin, Zhao Tong Liu, Wei Ping Chen, and Xiao Wei Liu. "A 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope." Key Engineering Materials 645-646 (May 2015): 605–9. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.605.

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In this paper, a 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope is proposedin order to enhance the precision of the digital to analog converter level.The interpolation filterhas achieved 64 times interpolation function,using three cascaded manner, it employs three level cascaded of FIR filterstructure. It achieves a 64 times oversampling feature. The signalbandwidth of the designs interpolation filter is 100 kHz, SNR reach 106dB. Fifth-order single-loop structure CIFB achieve noise shaping modulator function to verify the stability of the system, after the completion of CSD coefficient coding, signal to noise ratio reached 119.7dB, effective bits reached 19.59. The switched capacitor technology actualize analog reconstruction filter module, and using a typically switched capacitor DAC achieved high jump "0, 1" digital signal is converted into an analog signal, the digital-analog conversion achieved.

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7

Lammers, Mark, Alexander M. Powell, and Özgür Yılmaz. "Alternative dual frames for digital-to-analog conversion in sigma–delta quantization." Advances in Computational Mathematics 32, no. 1 (July 19, 2008): 73–102. http://dx.doi.org/10.1007/s10444-008-9088-1.

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8

Kurikov, S. F., D. A. Prilutskij, and S. V. Selishchev. "Use of analog-to-digital sigma-delta conversion technology in digital multi-channel electrocardiographs." Computer Standards & Interfaces 21, no. 2 (June 1999): 99. http://dx.doi.org/10.1016/s0920-5489(99)91924-4.

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9

Yin, Y., H. Klar, and P. Wennekers. "A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator." Advances in Radio Science 3 (May 12, 2005): 277–80. http://dx.doi.org/10.5194/ars-3-277-2005.

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Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.

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10

DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

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11

KiYoung Nam, Sang-Min Lee, D. K. Su, and B. A. Wooley. "A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion." IEEE Journal of Solid-State Circuits 40, no. 9 (September 2005): 1855–64. http://dx.doi.org/10.1109/jssc.2005.852161.

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12

Lv, Risheng, Weiping Chen, and Xiaowei Liu. "A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes." Micromachines 9, no. 8 (July 27, 2018): 372. http://dx.doi.org/10.3390/mi9080372.

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This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

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13

Li, Xiangyu, Jianping Hu, and Xiaowei Liu. "Harmonic Distortion Optimization for Sigma-Delta Modulators Interface Circuit of TMR Sensors." Sensors 20, no. 4 (February 14, 2020): 1041. http://dx.doi.org/10.3390/s20041041.

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The tunneling magnetoresistance micro-sensors (TMR) developed by magnetic multilayer material has many advantages, such as high sensitivity, high frequency response, and good reliability. It is widely used in military and civil fields. This work presents a high-performance interface circuit for TMR sensors. Because of the nonlinearity of signal conversion between sensitive structure and interface circuit in feedback loop and forward path, large harmonic distortion occurs in output signal spectrum, which greatly leads to the reduction of SNDR (signal noise distortion rate). In this paper, we analyzed the main source of harmonic distortion in closed-loop detection circuit and establish an accurate harmonic distortion model in TMR micro-sensors system. Some factors are considered, including non-linear gain of operational amplifier unit, effective gain bandwidth, conversion speed, nonlinearity of analog transmission gate, and nonlinearity of polycrystalline capacitance in high-order sigma-delta system. We optimized the CMOS switch and first-stage integrator in the switched-capacitor circuit. The harmonic distortion parameter is optimally designed in the TMR sensors system, aiming at the mismatch of misalignment of front-end system, non-linearity of quantizer, non-linearity of capacitor, and non-linearity of analog switch. The digital output is attained by the interface circuit based on a low-noise front-end interface circuit and a third-order sigma-delta modulator. The digital interface circuit is implemented by 0.35μm CMOS (complementary metal oxide semiconductor) technology. The high-performance digital TMR sensors system is implemented by double chip integration and the active interface circuit area is about 3.2 × 2 mm. The TMR sensors system consumes 20 mW at a single 5 V supply voltage. The TMR sensors system can achieve a linearity of 0.3% at full scale range (±105 nT) and a resolution of 0.25 nT/Hz1/2(@1Hz).

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14

Kumar, R. S. Ashwin, and Nagendra Krishnapura. "Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 11 (November 2020): 3693–703. http://dx.doi.org/10.1109/tcsi.2020.3013691.

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15

Ignjatovic, Zeljko, Danijel Maricic, and Mark F. Bocko. "Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling $\Sigma\Delta$ Analog-to-Digital Conversion." IEEE Sensors Journal 12, no. 4 (April 2012): 737–46. http://dx.doi.org/10.1109/jsen.2011.2158818.

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16

Gao, Zhenyi, Bin Zhou, Xiang Li, Lei Yang, Qi Wei, and Rong Zhang. "A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control." Sensors 21, no. 2 (January 9, 2021): 431. http://dx.doi.org/10.3390/s21020431.

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Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.

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17

Gao, Zhenyi, Bin Zhou, Xiang Li, Lei Yang, Qi Wei, and Rong Zhang. "A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control." Sensors 21, no. 2 (January 9, 2021): 431. http://dx.doi.org/10.3390/s21020431.

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Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.

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18

Wei, Rongshan, Weiwen Lin, Xiaoxia Xiao, Qunchao Chen, and Fanyang Li. "A Large Measurable Range Capacitance-to-Digital Converter for Smart Humidity Sensors." Micromachines 10, no. 9 (August 24, 2019): 561. http://dx.doi.org/10.3390/mi10090561.

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This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.

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19

Lv, Risheng, Weiping Chen, Qiang Fu, Liang Yin, Yufeng Zhang, and Xiaowei Liu. "A triple-channel incremental zoom-ADC for 3-DoF MEMS digital gyroscopes." Modern Physics Letters B 34, no. 13 (March 30, 2020): 2050136. http://dx.doi.org/10.1142/s0217984920501365.

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This paper presents a multiplexed analog-to-digital converter (ADC) consisting mainly of high-precision sampling holders (S/H) and an incremental zoom ADC. Flip-around design is employed in S/H modules for power economy and noise suppression. Based on efficient coordination between S/H and multiplexers, synchronous sampling is available in the whole triple-channel ADC to maintain phase accordance. The core converter employed a hybrid architecture of successive approximation register (SAR) and Sigma-Delta [Formula: see text], which constitutes an energy-efficient zoom ADC. Final conversion result is a combination of the two steps. Both the SAR and [Formula: see text] modulation share a third-order loop filter to compromise between systematic stability and input range. On-chip digital logic include capacitor array controlling and dynamic-element-matching (DEM) technique. Manufactured in a standard [Formula: see text]m CMOS technology, the whole chip occupies an area of 2.7 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB, with a power consumption of 2.1 mW from a 5 V supply.

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20

Chen, Hongmei, Li Wang, Ting Li, Lin He, and Fujiang Lin. "A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path." Journal of Circuits, Systems and Computers 26, no. 07 (March 17, 2017): 1750117. http://dx.doi.org/10.1142/s0218126617501171.

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This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

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21

Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (January 10, 2020): 137. http://dx.doi.org/10.3390/electronics9010137.

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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22

Fan, Suyan, Man-Kay Law, Mingzhong Li, Zhiyuan Chen, Chio-In Ieong, Pui-In Mak, and Rui P. Martins. "Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell." Journal of Circuits, Systems and Computers 25, no. 01 (November 15, 2015): 1640006. http://dx.doi.org/10.1142/s0218126616400065.

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In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

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23

Huang, Fu Xiang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope." Key Engineering Materials 645-646 (May 2015): 548–54. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.548.

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Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

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24

Miller, Donald L., John X. Przybysz, A. Hodge Worsham, and Andrew H. Miklich. "Superconducting sigma-delta analog-to-digital converters." Applied Superconductivity 6, no. 10-12 (October 1999): 657–61. http://dx.doi.org/10.1016/s0964-1807(99)00025-3.

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25

Diwakar, Krishna, Chinnaiyan Senthilpari, Ajay Singh, and Lim Soong. "Delta-Sigma Modulator Based Analog Multiplier with Digital Output." Recent Patents on Electrical Engineeringe 2, no. 2 (June 1, 2009): 161–64. http://dx.doi.org/10.2174/1874476110902020161.

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26

Jeong, Jinyoung, Danbi Choi, and Jeongjin Roh. "Incremental Delta-Sigma Analog to Digital Converter for Sensor." Journal of the Institute of Electronics Engineers of Korea 49, no. 10 (October 25, 2012): 148–58. http://dx.doi.org/10.5573/ieek.2012.49.10.148.

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27

Hummels, D. M., D. Gerow, and F. H. Irons. "Compensation technique for sigma-delta analog-to-digital converters." Computer Standards & Interfaces 21, no. 2 (June 1999): 101. http://dx.doi.org/10.1016/s0920-5489(99)91934-7.

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28

Kiss, P., J. Arias, D. Li, and V. Boccuzzi. "Stable High-Order Delta–Sigma Digital-to-Analog Converters." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 51, no. 1 (January 2004): 200–205. http://dx.doi.org/10.1109/tcsi.2003.821283.

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29

Bulzacchelli, John F., Hae-Seung Lee, James A. Misewich, and Mark B. Ketchen. "Development of superconducting bandpass delta-sigma analog-to-digital converter." Physica C: Superconductivity 412-414 (October 2004): 1539–45. http://dx.doi.org/10.1016/j.physc.2004.01.156.

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30

Boser, B. E., and B. A. Wooley. "The design of sigma-delta modulation analog-to-digital converters." IEEE Journal of Solid-State Circuits 23, no. 6 (1988): 1298–308. http://dx.doi.org/10.1109/4.90025.

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31

Arpaia, P., F. Cennamo, P. Daponte, and H. Schumny. "Modeling and characterization of sigma-delta analog-to-digital converters." IEEE Transactions on Instrumentation and Measurement 52, no. 3 (June 2003): 978–83. http://dx.doi.org/10.1109/tim.2003.809106.

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32

Wilson, Gerald, and Robert S. Green. "Multiplierless interpolator for a delta-sigma digital to analog converter." Journal of the Acoustical Society of America 112, no. 6 (2002): 2515. http://dx.doi.org/10.1121/1.1536480.

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33

Przybysz, J. X., D. L. Miller, and E. H. Naviasky. "Two-loop modulator for sigma-delta analog to digital converter." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2248–51. http://dx.doi.org/10.1109/77.403033.

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34

Miller, D. L., J. X. Przybysz, D. L. Meier, Joonhee Kang, and A. H. Worsham. "Characterization of a superconductive sigma-delta analog to digital converter." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2453–56. http://dx.doi.org/10.1109/77.403087.

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Xu, Chi, Yu Jin, and Duli Yu. "A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator." Mathematical Problems in Engineering 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/9861383.

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This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

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Puidokas, Vytenis, and Albinas J. Marcinkevičius. "High Resolution High Power Low Frequency Digital-to-Analog Converter." Solid State Phenomena 164 (June 2010): 133–38. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.133.

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The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.

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Skripnichenko, M. N., and I. A. Lipatov. "DESIGN AND VERIFICATION FLOW OF MULTI-STAGE SIGMA-DELTA ADC DIGITAL CORE." Issues of radio electronics, no. 8 (August 20, 2018): 56–63. http://dx.doi.org/10.21778/2218-5453-2018-8-56-63.

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There is a need for analog-to-digital converters with high signal-to-noise ratio and large signal bandwidth to solve a number of radiolocation problems. Developing such ADC is a challenge in the analog core, digital core and verification. The design flow of the digital core must take into account the possibility of changing the analog core specification at any design stage, provide the ability to quickly obtain the synthesizable RTL code of the device and conduct its functional verification. Automation tools were used to reduce the time spent on development and verification. This article describes the developed software package that generates the synthesizable RTL code and the verification environment configurations for each stage of development of the analog core of the multi-stage sigma-delta ADC.

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Tsai, Chia-Chi, Tzu-Ming Wang, and Ming-Dou Ker. "Implementation of delta—sigma analog-to-digital converter in LTPS process." Journal of the Society for Information Display 18, no. 11 (2010): 904. http://dx.doi.org/10.1889/jsid18.11.904.

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Becker, M., K. Heiber, M. Ortmanns, and Y. Manoli. "Eine verlustleistungsoptimierte Dezimator-Architektur für kaskadierte Sigma-Delta Analog-Digital Umsetzer." Advances in Radio Science 2 (May 27, 2005): 199–203. http://dx.doi.org/10.5194/ars-2-199-2004.

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Abstract. Dieser Beitrag stellt einen neuartigen Ansatz einer leistungsfähigen Dezimator-Architektur f¨ur kaskadierte Sigma-Delta Modulatoren vor. Die Besonderheit der dargestellten Struktur ist die Integration der Rekombinationslogik kaskadierter Modulatoren und der Korrektur des Verstärkungsfehlers zeitkontinuierlicher (continuous time, CT) Modulatoren in die erste Stufe des Dezimators. Der Entwurf einer passenden Filtertopologie wird abgeleitet, analysiert und durch Simulationen verifiziert. Die vorgeschlagene Struktur wird mit einer herk¨ommlichen Implementierung verglichen. Das Ergebnis dieses Vergleiches ist eine Verbesserung der Effizienz um Dekaden.

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Becker, M., N. Lotze, J. Becker, M. Ortmanns, and Y. Manoli. "Implementierung eines verlustleistungsoptimierten Dezimators für kaskadierte Sigma-Delta Analog-Digital Umsetzer." Advances in Radio Science 3 (May 13, 2005): 389–93. http://dx.doi.org/10.5194/ars-3-389-2005.

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Abstract. Dieser Beitrag stellt die Implementierung eines neuartigen Ansatzes einer effizienten Dezimator-Architektur für kaskadierte Sigma-Delta Modulatoren vor. Die Rekombinationslogik kaskadierter Modulatoren und die Korrektur des Verstärkungsfehlers zeitkontinuierlicher (CT) Modulatoren werden in die erste Stufe des Dezimators integriert. Eine entsprechende Filtertopologie wird hergeleitet und auf einem Hardware-Emulator der Firma Mentor Graphics implementiert. Der Vergleich der vorgeschlagenen Struktur mit einer herkömmlichen Implementierung zeigt eine nennenswerte Verbesserung der Effizienz.

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Xie, Y. P., S. R. Whiteley, and T. van Duzer. "High-speed decimation filter for delta-sigma analog-to-digital converter." IEEE Transactions on Appiled Superconductivity 9, no. 2 (June 1999): 3632–35. http://dx.doi.org/10.1109/77.783815.

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Miller, D. L., J. X. Przybysz, A. H. Worsham, and E. J. Dean. "Flux quantum sigma-delta analog-to-digital converters for rf signals." IEEE Transactions on Appiled Superconductivity 9, no. 2 (June 1999): 4026–29. http://dx.doi.org/10.1109/77.783911.

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43

Inerfield, M., W. Skones, S. Nelson, D. Ching, P. Cheng, and C. Wong. "High dynamic range InP HBT delta-sigma analog-to-digital converters." IEEE Journal of Solid-State Circuits 38, no. 9 (September 2003): 1524–32. http://dx.doi.org/10.1109/jssc.2003.815920.

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Gani, M. R. "Robust digital correction of analog errors in cascaded sigma delta converters." Measurement 37, no. 4 (June 2005): 310–19. http://dx.doi.org/10.1016/j.measurement.2005.03.003.

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Yokoyama, Yuji, Yutaka Ohno, Shigeru Kishimoto, Koichi Maezawa, and Takashi Mizutani. "A Delta-Sigma Analog-to-Digital Converter Using Resonant Tunneling Diodes." Japanese Journal of Applied Physics 40, Part 2, No. 10A (October 1, 2001): L1005—L1007. http://dx.doi.org/10.1143/jjap.40.l1005.

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Friedman, V., D. M. Brinthaupt, D. P. Chen, T. Deppa, J. P. Elward, E. M. Fields, and H. Meleis. "A bit-slice architecture for sigma-delta analog-to-digital converters." IEEE Journal on Selected Areas in Communications 6, no. 3 (April 1988): 520–26. http://dx.doi.org/10.1109/49.1920.

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Suszyński, Robert, and Krzysztof Wawryn. "Rapid Prototyping of Third-Order Sigma-Delta A/D Converters." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 99–104. http://dx.doi.org/10.2478/eletel-2013-0012.

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Abstract Prototyping of third-order sigma-delta analog to digital converters (ΣΔ ADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ΣΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured to satisfy input specifications.

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48

Prasad, Deepak, and Vijay Nath. "An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 12. http://dx.doi.org/10.11591/ijres.v7.i1.pp12-20.

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In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.

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Silva-Rivas, F., C. Y. Lu, P. Kode, B. K. Thandri, and J. Silva-Martinez. "Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters." Analog Integrated Circuits and Signal Processing 59, no. 1 (November 27, 2008): 91–95. http://dx.doi.org/10.1007/s10470-008-9240-3.

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Daniels, Jorg, Wim Dehaene, Michiel S. J. Steyaert, and Andreas Wiesbauer. "A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (September 2010): 2404–12. http://dx.doi.org/10.1109/tcsi.2010.2043169.

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