Academic literature on the topic 'Design av digitale systemer'

Denne oppgaven er stilt av Aptina Norway AS og tar for seg utviklingen av et FPGA-basert system for emulering av output fra en A/D-omformer i en CMOS-bildesensor.Dette systemet er ment a benyttes til verisering av RTL-design til CMOS-bildesensorprodukter. Emulatoren bruker en tilnrming til normalfordelingen for aemulere foton-, rad- og kolonnesty, og kan kjre pa frekvenser opp til 124:81 MHz.Dette gjr at emulatoren kan behandle 60 bilder i sekundet med full HD-opplsning. Systemet lar brukeren bestemme opplsning, stytyper og eventueltstandardavvikene til rad- og kolonnestyen ved oppstart. Hastigheten bestemmes avfrekvensen pa klokken som patrykkes. Simuleringene og testene som er utfrt viserat emulatoren gir et resultat som er visuelt likt reell foton-, rad- og kolonnesty,men styfordelingene er noe kunstige og kan forarsake uventede artifakter i bildene.

Digital circuits designed today are almost exclusively clocked. As designs grow in size it becomes harder to effectively distribute the various clock signals over the circuit. The clock is also a big contribution to the power consumption of a circuit. Some work is being done to provide alternatives to standard synchronous design. One of these alternatives is the Balsa system.Several versions of an asynchronous module for controlling the startup process of a microcontroller was made in Balsa and compared to a standard synchronous implementation. Area estimates for the best asynchronous implementation gives a number that is a factor of over four larger than for the synchronous implementation. The asynchronous implementation has other advantages though. It has no dynamic power consumption when it is in a stable state. Additionally it can operate closer to the sub-threshold area.The asynchronous implementations have been tested and found working in active HDL. Balsa generated verilog netlists in a 350 nm library from the balsa language description. Design Compiler from Synopsys was used to get the area estimates. The asynchronous implementations shows potential, especially with regards to reduced power consumption.

<p>Three algorithms for video scaling were developed and tested in software, for implementation on an FPGA. Two of the algorithms were implemented in a video scaler system. These two algorithms scale up with factors 1.25 and 1.875, which is used for scaling SD WIDE to HD resolution and SD WIDE to FullHD resolution, respectively. An algorithm with scaling factor 1.5, scaling HD to FullHD, was also discussed, but not implemented. The video scaler was tested with a verilog testbench provided by ARM. When passing the testbench, the video scaler system was loaded on an FPGA. Results from the FPGA were compared with the software algorithms and the simulation results from the testbench. The video scaler implemented on the FPGA produced predictable results. Even though a fully functional video scaler was made, there were not time left to create the necessary software drivers and application software that would be needed to run the video scaler in real time with live video output. So a comparison of the output from the implemented algorithms is performed with common scaling algorithms used in video scalers, such as bilinear interpolation and bicubic interpolation. This thesis also deal with graphics scaling. Some well-known algorithms for graphic scaling were written in software, including a self-made algorithm to suit hardware. These algorithms were not implemented in hardware, but comparison of the results are performed.</p>

With Moore&#146;s law exponentially increasing the number of transistors on inte-grated circuits, developers fail to keep up. This makes chip area an increasinglycheap resource. At the same time, researchers and developers are trying to findways to dynamically reconfigure FPGAs, preferably at run time, so as to in-crease the flexibility of hardware solutions, and close the gap between the speedof hardware and flexibility of software. A proposed way of solving both of theseissues at once is by using nondeterministic finite-state machines as a fundamen-tal unit of design. This could provide great flexibility and dynamic hardwaresolutions, but before this can be known for sure, a system like this would needto be simulated. This paper documents the planning and development of a Sys-temC library that creates nondeterministic finite-state machines from regularexpressions, and a special regular expression syntax designed for this specificapplication. The paper can also be used as a reference for the inner workingsof, and how to use, the library.

The NTNU Test Satellite (NUTS) project is aiming to launch a 10&#215;10&#215;20 cm nanosatellite by the year 2014. The goal is to design and develope a low cost satellite by exploring the use of commersially available components. This work will focus on the power system of the NUTS satellite, which consists of a power distribution system, the backplane, and a power condition system, the Electrical Power System (EPS).This thesis describes the design and evaluation of the EPS module, which is a critical part of the satellite, because without power the satellite will not be able to operate. The electrical power system of the satellite consists of the solar cells, batteries, and voltage converters. With limited power available, the main focus of the design has been to implement an efficient system with minimum losses in power conversions.The Electrical Power System (EPS) module has been designed with simplicity, reliability, and redundancy in mind. The designed is based on the requirements of a reliable power source, with the main goals of charging the batteries with power from the solar cells and regulate the battery voltage down to the requested voltages of the backplane. A charger is chosen for its abilities to provide efficient and safe charging by using proper strategies for efficient energy harvesting and charging. To accommodate the voltage request of the backplane, four fixed value regulators is chosen for the design. For power monitoring of the provided power from the solar cells and batteries, current monitor sensors are implemented after each charger circuit and the batteries. Based on the specification of the solar cells and the batteries a final design of the main functionalities has been provided and a prototype of the EPS module has been produced.The proposed solution offers a reliable and redundant system, where a loss of one charger or converter will not mean the end of the mission. The EPS module has been tested and evaluated, and displays good performance results in terms of charging the batteries and voltage regulation. The efficiency of the EPS chargers is found to be 95 %.

The Mandelbrot set, shown on the front page of this report, is perhaps themost well-known example of a fractal. Fractals is a certain familyof shapes with a very distinctive, interesting shape. The term was coined byBenoit B. Mandelbrot, for whom the Mandelbrot set is named after. The Mandelbrotset and other fractals are traditionally used for aesthetic purposes, such as inart, clothing, computer games, etc. However, there are also several practicalapplications for fractals, such as image compression.The Mandelbrot set is infinitely complex, making it desirable togenerate images of arbitrary sections of the set. Several software programs thatgenerate such images exists, but due to the computationally expensive nature ofthis task, these implementations are typically very slow, even on moderncomputers. However, the problem can be shown to be highly parallelizable,suggesting that a hardware implementation of such as generator should be able togenerate smooth real-time zoom animations, unlike existing softwareimplementations.A hardware fractal generator for the Mandelbrot set has been designed andimplemented in Verilog-2001. The design is very scalable, having a parameterspecifying the number of fractal point generators (cores) the synthesistool should implement. Furthermore, it is designed so that the floating pointunits in the cores are utilized nearly 100% of the time under normal operation.The design was tested on a Xilinx Virtex-6 FPGA with up to 16 cores, and it wasshown that the design was faster than a reference software solution running on adesktop computer when the number of cores was set to 2 or more.Additionally, a simplified Mandelbrot set algorithm is proposed and studiedexperimentally. In the simplified algorithm, the break condition in the algorithmloop is (|z_re| &gt; 2) || (|z_im| &gt; 2) as opposed to the standard |z| &gt; 2.The images produced using the simplified algorithm was judged to be nearlyindistinguishable from those produced with the standard algorithm, and thereforepreferred as it is easier to implement.Finally some future work is proposed. The integration of the fractal generatorwith the Mali-400 GPU originally planned as part of this thesis is left asfuture work. It is also suggested to consider designing a custom fixed-pointformat for use internally in the fractal generator, as the standardbinary32 floating-point format (FP32) is shown to be badly suited forthis application.

This report aims to provide a complete specification of an IEEE-754 1985 compliantdesign, as well as a working, synthesizable implementation in Verilog HDL. Thereport is based on a preliminary project, which analyzed the IEEE-754 standardand suggested a set of algorithms suitable for a compact realization.Through traditional methods of both algorithmic analysis and dataanalysis,requirements of functional units are derived, and operations are scheduled.A set of functional simulations assert the correctness of the design, while areaand performance analysis provides information on the speedup gained, versus thehardware cost.Finally, the results obtained are compared to existing implementations, bothhardware and software.

When using CMOS technology for image sensors, there is a possibility that any givenpixel is defective and will thus produce a value that does not correlate to the amount oflight it was subject to. As such, the processing unit will calculate a value that diersfrom the value produced if the transistor was working correctly. Having a pixel with adefective value can manifest itself as a light spot or a dark spot depending on whether thetransistor for that pixel is on or o. In some areas where the value of the defective pixeldoes not dier greatly from its neighbors, the image will not appear as degraded in theeyes of the viewer as if the defective value was in great contrast to its surroundings.Theability to compensate for the defective pixels with an algorithm will result in a morerobust device that is not required to function perfectly in order to produce an image. Italso translates into prot as a company can sell image sensors that would otherwise havebeen discarded by testing procedures.This report is organized with chapter 1 providing the introduction to the assignment interms of the nature of defective pixels and also creating a context with explanation asto why it is an important aspect of manufacturing image sensors .Chapter 2 describesthe development board that is utilized and how an embedded system can utilize a vhdlperipheral. It also shows what components will go into making an embedded system withthe required functionality. The theory behind components and techniques used in thisproject is in chapter 3. The vhdl les to be added to a peripheral so that they can beaccessed by the cpu, and the architectures of the vhdl les and microblaze are placedin chapter 4. Chapter 5 contains the simulations of the input images with dierentnoise levels and threshold levels in addition to tests designed to determine the embeddedsystems functional ability.The vhdl les and the microblaze systems are synthesized withthe resulting numbers revealed in chapter 6. The tools used in this project are listedin chapter 7 with their version number. Chapter 8 contains discussions regarding theresults and techniques in this project. The concluding remarks and the further work forthe project are in chapter 9 and 10, respectively. A list of terms will explain abbreviationsused in this report.i

Programvaredefinert radio (SDR) er ein ny m&#229;te &#229; implementere radiosystem p&#229;. Hovudtanken er at delar av radioen som tidlegare har vore implementert med l&#229;ste analoge og digitale l&#248;ysingar skal erstattast med programvare som k&#248;yrer p&#229; ein prosessor. Dette kan forbetre mellom anna fleksibilitet, tilpassingsdyktigheit og produksjonskostnadar.Denne oppg&#229;va tek for seg ein DSP-arkitektur spesielt tilpassa l&#229;geffekt modulasjon og demodulasjon av radiosignaler med lav kompleksitet. Bluetooth er vald som d&#248;me og demodulasjonsdelen av denne er analysert for &#229; belyse kva krav ein slik applikasjon vil stille til ein digital signalprosessor.Gjennom denne analyse kjem det fram at ein del av applikasjonen, estimasjon av arcus tangens, b&#248;r akselererast for &#229; oppn&#229; optimal yting og effektforbruk. Dette blir realisert gjennom &#229; introdusere ei CORDIC-eining i systemet. Denne er s&#229; satt i samanheng med resten av prosessorarkitekturen, og det er sett p&#229; korleis dette p&#229;verkar krava til arkitekturen.Det blir mellom anna konkludert med at DSP-en b&#248;r innehalde ein dedikert l&#248;kkehandterar samt ein cache for programminnet.