Relevant bibliographies by topics / Design en vue du test

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Design en vue du test'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Design en vue du test"

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Bayrakçeken, Hüseyin, Faruk Emre Aysal, and İbrahim Mutlu. "The Design and Manufacturing of Brake‐Suspension Test Device." Afyon Kocatepe University Journal of Sciences and Engineering 16, no. 2 (June 1, 2016): 454–60. http://dx.doi.org/10.5578/fmbd.27861.

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Alavi, Omid, Leander Van Cappellen, Ward De Ceuninck, and Michaël Daenen. "Practical Challenges of High-Power IGBT’s I-V Curve Measurement and Its Importance in Reliability Analysis." Electronics 10, no. 17 (August 29, 2021): 2095. http://dx.doi.org/10.3390/electronics10172095.

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This paper examines the practical challenges of simplified setups aimed at achieving high-power IGBTs’ IC–VCE curve. The slope of this I–V curve (which is defined as on-resistance RCE) and the point where the VCE–VGE curve visibly bends (threshold gate voltage) can be suitable failure precursor parameters to determine an IGBT’s health condition. A simplified/affordable design for these specific measurements can be used for in-situ condition monitoring or field testing of switching devices. First, the possible I–V curve measurement methods are discussed in detail in order to prevent self-heating. The selected design includes two IGBTs in which the high-side IGBT was the device under test (DUT) with a constant gate voltage (VGE) of 15 V. Then, the low-side IGBT was switched by a short pulse (50 μs) to impose a high-current pulse on the DUT. The VCE–VGE curve was also extracted as an important failure-precursor indicator. In the next stage, a power-cycling test was performed, and the impact of degradation on the IGBT was analyzed by these measurement methods. The results show that after 18,000 thermal cycles, a visible shift in I–V curve can be seen. The internal resistance increased by 13%, while the initial collector-emitter voltage and voltage at the knee point in the VCE–VGE curve slightly changed. It is likely that in our case, during the performed power-cycling test and aging process, the bond wires were most affected, but this hypothesis needs further investigation.
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Olson, John D., Mark T. Cunningham, Russell A. Higgins, Charles S. Eby, and John T. Brandt. "D-dimer: Simple Test, Tough Problems." Archives of Pathology & Laboratory Medicine 137, no. 8 (August 1, 2013): 1030–38. http://dx.doi.org/10.5858/arpa.2012-0296-cp.

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Context.—D-dimer is widely used for exclusion, or as an aid in diagnosis, of venous thromboembolism (VTE); however, the D-dimer assay methods available from manufacturers and the laboratory application of those methods vary widely. Objectives.—To describe the current laboratory practice regarding the assay and reporting of D-dimer. Design.—Laboratories' D-dimer proficiency testing data were analyzed and laboratory practices regarding the performance and reporting of D-dimer were surveyed. Results.—Initial grading of D-dimer proficiency testing demonstrated high variability within and among methods. This variability continued to be present for several years after attempts to intervene. The number of laboratories using D-dimer to exclude VTE grew from 1500 in 2004 to more than 3500 in 2012. Survey and proficiency testing data demonstrated that 33% of laboratories changed the type or magnitude of units from that recommended by the manufacturer, a practice associated with as much as a 20-fold increase in the failure of proficiency testing. Many laboratories used a threshold for the exclusion of VTE that is higher than that recommended by the manufacturer. Many laboratories continue to use qualitative assays with insufficient sensitivity for exclusion of VTE. Conclusions.—There is considerable variability both within and among quantitative methods used to assay D-dimer by laboratories. Laboratory practice continues to vary widely regarding the type and magnitude of units reported and the setting of the threshold for the exclusion of VTE. Although improved, the variability continues despite initial efforts to intervene.
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Li, Xu, Li Min Chang, Li Jing Zhang, and Yan Bin Shi. "Design of Integrated Control and Support Platform for Airborne Digital Image Transmission System." Applied Mechanics and Materials 380-384 (August 2013): 2845–49. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.2845.

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Aiming at the problems of guarantee equipment deficiency and poor versatility in airborne digital image transmission system, and adopting ATE design ideas, this paper presents a design scheme of integrated control and support platform based on VME bus architecture. With the technology of software radio and software function modules, the design realizes the universal support of multi-type digital image transmission system. Adopting the technology of virtual system, software designs which are hierarchical, modular and interface, it realizes the integrated control of test system. The practice has proved that this support platform has the advantage of stable operation, good versatility, strong practicality and broad application prospects.
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Almheiri, Zayed, Rawan Aleid, and Sharul Sham Dol. "Design of Fixed-Wing and Multi-Copter Hybrid Drone System for Human Body Temperature Measurement during COVID-19 Pandemic." WSEAS TRANSACTIONS ON SYSTEMS 20 (March 16, 2021): 31–39. http://dx.doi.org/10.37394/23202.2021.20.5.

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The purpose of this research is to conduct aerodynamics study and design a hybrid drone system of fixed-wing and multi-copter. The mission of this drone is to measure human body temperature during COVID19 pandemic. The specific aim of the drone is to fly and cover larger industrial areas roughly about 50 km2 with longer flying time than the conventional drone, of about 1.5 hours. The applications of the simulation software such as XFLR5 and ANSYS have a big impact in identifying areas that need to be improved for the drone system. XFLR5 software was used to compare the characteristics of different airfoils with highest lift over drag, L/D ratio. Based on the airfoil selection, it was found that NACA 4412 airfoil produces the highest L/D ratio. The detailed geometry of the drone system includes a fuselage length of 1.9 meters and wingspan of 2 meters. Moreover, 10 sheets of solar panels were placed along the wing for sustainable flight operation to cover wider areas of mission. The structural analysis was done on ANSYS to test the elastic stress, equivalent strain, deformation, factor of safety pressure as well as lift and drag forces under various operational conditions and payloads. The landing gear was analyzed for harsh landing. ANSYS Computational Fluid Dynamics (CFD) was utilized to study the aerodynamics of the drone at different parameters such as the velocities and angles of attack during the operation. This design ensures the stability of the drone during the temperature measurement phase. The best thermal-imaging camera for such purpose would be the Vue Pro R 336, 45° radiometric drone thermal camera with a resolution of 640 x 512 pixels. This camera has the advantage of a permanent continuous out focus that give the ability of taking measurements even if there was changing on the altitude or any kind of vibrations.
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Kim, Soobin, Jessie Klugman, Sarah Norell, Alexandra Kenefake, Laurel Komos, Divya Jain, Moire Corcoran, et al. "Improving VTE prophylaxis adherence among hospitalized adolescents using Human-Centered Design." Journal of Patient Safety and Risk Management 26, no. 4 (July 2021): 172–78. http://dx.doi.org/10.1177/25160435211036784.

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Background/problem statement Venous thromboembolism (VTE) is the leading cause of preventable hospital mortality in the United States; however, compliance with VTE prophylaxis is poor. Most materials for education about VTE prophylaxis are oriented toward adults rather than adolescents, for whom VTE risks are lower and prophylaxis indications differ. We hypothesized that educational materials for adolescents could improve compliance with VTE prophylaxis, reduce nurse burden for initiating and maintaining VTE prevention practices, and reduce practice variation by standardizing the conversation between clinicians and patients. Methods A multidisciplinary team including physicians, nurses, quality experts, communication designers, service designers, and medical students applied a human-centered design (HCD) process to define, iteratively prototype, and test education tools for nurses assigned to adolescents. We piloted a suite of six educational tools for adolescent VTE prophylaxis to fit into the existing hospital workflow. Results An in-room poster was selected after 85% of nurses responded favorably to this intervention. Adolescent adherence with Intermittent Pneumatic Compression Device increased from 69% to 79%, attaining the benchmark goal of 78%. Staff reported greater confidence in educating adolescent patients after the intervention: 62% of nurses and 72% of residents. Conclusion An HCD process helped nurses improve VTE prophylaxis for adolescents with an in-room poster and messaging strategy. Engaging staff in the design increased receptivity and adoption. The piloted materials also helped to create an environment of shared priority among the clinicians.
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Daniyanti, Selly Nur, Anna Fitri Hindriana, and Sri Redjeki. "Implementasi Praktikum Berbasis Diagram Vee Untuk Memunculkan Kemampuan Metakognitif Dan Penguasaan Konsep Siswa." Edubiologica Jurnal Penelitian Ilmu dan Pendidikan Biologi 6, no. 1 (December 28, 2019): 44. http://dx.doi.org/10.25134/edubiologica.v6i1.2362.

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The aim of the research is to determine the implementation of lab activities based Vee diagram to bring out students metacognitive skill and increasing students' learning achievement to the excretory system. Quasi-experimental research with nonequivalent control group design was conducted to the classes. Lab activities based Vee diagram was implemented to the experimental class and lab activities based guided inquiry was implemented to the control class. The sample was determined by purposive sampling technique. Data of the research was obtained from student� worksheet that applying metacognitive strategies and the result of� pre test and post test. Metacognitive skills of experimental class is higher than the control class. Based on analysis, metacognitive skills of experimental class was 75.0 and metacognitive skill of control class was 67.8. Learning achievement of experimental class is higher than control class. The results of the test showed an increasing (N gain) of learning achievement experimental class was 0.53 and control class was 0.41. T test showed t count > t table, which means that there are significant differences between pre-test and post test. Correlation test results showed the corellation between metacognitive skills and learning achievement is very high at 96.7%Keywords: Vee diagram; Guided inquiry; Metacognitive skill; Learning achievement
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Tin, Tan Geok, Noor Azean Atan, Mohd Nihra Haruzuan Mohamad Said, Mohd Fazli Ali, Sanitah Mohd, and Mohd Zolkifli Abd Hamid. "Integrating Animations in Chinese Character Writing Based on Cognitive Theory of Multimedia Learning to Promote Students’ Writing Skills." International Journal of Interactive Mobile Technologies (iJIM) 12, no. 7 (November 8, 2018): 97. http://dx.doi.org/10.3991/ijim.v12i7.9671.

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<p class="0abstract">The complexity of Chinese character caused students facing learning difficulty in mastering the Chinese character writing skills. This study aimed to investigate the effect and students' perception on the implementation of animation in teaching and learning of Chinese character writing based on Cognitive Theory of Multimedia Learning (AniCC Online Learning) via Frog VLE platform. Meanwhile, the relationship of implementation of AniCC Online Learning and pupil's writing performance was also studied to have further insights into the Chinese character teaching and learning situation. Pre-experimental one group pre-test and post-test design were adopted and thirty three Year 1 students were selected as the respondents in this research which involved four types of instruments. There was a significant different (p = 0.013) between the scores of pre-test and post-test for students' writing performance after performing paired samples t-test. The study also showed an increase in the means scores of students' writing skills and an increase in the percentage of students' writing skills ranking at rank 4 or above although no significant different (p = 0.180) was observed between the pre writing assessment and post writing assessment after Wilcoxon Test was performed. The students overall showed high acceptance towards integration of AniCC Online Learning with overall mean score 0.90 (maximum = 1). In sum, the design of AniCC Online Learning via Frog VLE platform is able to improve writing performance as well as to help students in their writing skills.</p>
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Suryani, Irma, and Riski Muliyani. "Penerapan Model Pembelajaran Heuristic Vee terhadap Peningkatan Pemahaman Konsep Siswa Pada Materi Fluida Statis." Journal of Natural Science and Integration 2, no. 2 (October 28, 2019): 52. http://dx.doi.org/10.24014/jnsi.v2i2.7885.

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Penelitian ini bertujuan untuk mendapatkan gambaran mengenai peningkatan aspek pemahaman konsep siswa setelah diterapkan model pembelajaran heuristic vee pada materi fluida statis. Penelitian yang digunakan adalah penelitian kuantitatif, dengan metode weak experiment design dengan desain one group pretest-posttest design. Teknik pengumpulan data yang digunakan adalah tes dan non tes. Instrumen tes berupa soal pre-test dan post-test pemahaman konsep. Sedangkan non tes berupa lembar observasi keterlaksanaan model dan lembar respon siswa. Sampel yang diambil dalam penelitian ini berupa Cluster sampling yang dipilih satu kelas dari seluruh siswa kelas VIII. Populasi dalam penelitian ini adalah kelas VIII SMP Negeri 8 Singkawang dengan jumlah 32 siswa. Hasil penelitian menunjukkan bahwa model pembelajaran heuristic vee dapat meningkatkan pemahaman konsep siswa pada aspek menafsirkan sebesar 0,7 dengan ketegori tinggi, aspek mengklasifikasikan sebesar 0,3 dengan ketegori sedang, aspek menyimpulkan sebesar 0,6 dengan ketegori sedang, ; aspek membandingkan dengan ketegori sedang dan aspek menjelaskan sebesar 0,2 dengan ketegori rendah.
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Robinson, Reagan N., and Anthony N. Taneh. "DIGITAL ILLITERACY: A CONSTRAINT TO TECHNOLOGY EDUCATION ADVANCEMENT IN SOUTH-SOUTH REGION OF NIGERIA." International Journal of Research -GRANTHAALAYAH 6, no. 11 (November 30, 2018): 307–14. http://dx.doi.org/10.29121/granthaalayah.v6.i11.2018.1132.

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Technology education is one the programmes designed to provide technical knowledge and skills necessary for economic development in Nigeria. But technology education programme has a constraint to its advancement which this study investigated. The study adopted the survey research method for the design. The population of the study was 453 persons comprised of 379 students and 74 technical teachers from one Technical College and a University with technology education department in each of the 6 states of the South-South geo-political zone. A simple random sampling technique was used to obtain a sample size of 188 which comprised of 33 technical teachers and 155 students. A 5-item questionnaire was used as the instrument for the study. The questionnaire item was followed by a single response category based on a 5-point rating scale format of Very High Extent (VHE), High Extent (HE), Moderate Extent (ME), Low Extent (LE) and Very Low Extent (VLE). A test re-test method was adapted to test the reliability of the instrument to obtain a coefficient of 0.73. The data gathered was analyzed using mean and z-test analysis to answer the research question and hypothesis respectively. The finding revealed that digital illiteracy is a constraint to technology education advancement in Nigeria. Based on the findings, it was recommended that in order to enhance digital proficiency in technology education, government should adequately provide digital facilities in all technology education institutions in Nigeria.
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Dissertations / Theses on the topic "Design en vue du test"

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Fkih, Yassine. "Conception en vue du Test des Circuits Intégrés 3D à base de TSVs." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20063/document.

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Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus récemment les circuits empilés en 3D : les 3D SIC (Stacked Integrated Circuits) à base de TSVs (Through Silicon Vias) interconnectant verticalement les tiers, ou puces, du système. Les 3D SIC présentent de nombreux avantages en termes de facteur de forme, de performance et de consommation mais demandent aussi de relever de nombreux défis en ce qui concerne leur test, étape nécessaire avant la mise en service de ces systèmes complexes. Dans cette thèse, nous nous attachons à définir les infrastructures de test qui permettront de détecter les éventuels défauts apparaissant lors de la fabrication des TSVs ou des différentes puces du système. Nous proposons une solution de BIST (Built In Self Test) pour le test avant empilement des TSVs. Cette solution est basée sur l'utilisation d'oscillateurs en anneaux dont la fréquence d'oscillation dépend des caractéristiques électriques des TSVs. La solution de test proposée permet non seulement la détection de TSVs fautifs mais aussi de renseigner sur le nombre d'éléments défectueux et leur identification. D'autre part, nous proposons une architecture de test 3D basée sur la nouvelle proposition de norme IEEE P1687. Cette infrastructure permet de donner accès aux composants du système 3D avant et après empilement. Elle permet d'autre part de profiter du recyclage des données de test développées et appliquées avant empilement pour chacun des tiers puis ré-appliqués durant ou après l'empilement. Ces travaux aboutissent finalement à l'ouverture d'une nouvelle problématique liée à l'ordonnancement des tests sous contraintes (puissance consommée, température).Mots-clés : test, circuits 3D, TSV, BIST, oscillateur en anneau, architecture de test 3D, IEEE P1687, test avant empilement, test après empilement
For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test
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Laraba, Asma. "Conception en vue de test de convertisseurs de signal analogique-numérique de type pipeline." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00947360.

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La Non-Linéarité-Différentielle (NLD) et la Non-Linéarité-Intégrale (NLI) sont les performances statiques les plus importantes des Convertisseurs Analogique-Numérique (CAN) qui sont mesurées lors d'un test de production. Ces deux performances indiquent la déviation de la fonction de transfert du CAN par rapport au cas idéal. Elles sont obtenues en appliquant une rampe ou une sinusoïde lente au CAN et en calculant le nombre d'occurrences de chacun des codes du CAN.Ceci permet la construction de l'histogramme qui permet l'extraction de la NLD et la NLI. Cette approche requiert lacollection d'une quantité importante de données puisque chacun des codes doit être traversé plusieurs fois afin de moyenner le bruit et la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. En effet,malgré que les circuits analogiques et mixtes occupent une surface qui n'excède pas généralement 5% de la surface globald'un System-on-Chip (SoC), leur temps de test représente souvent plus que 30% du temps de test global. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d'attention et qui est en train deprendre de l'ampleur. Les CAN de type pipeline offrent un bon compromis entre la vitesse, la résolution et la consommation.Ils sont convenables pour une variété d'applications et sont typiquement utilisés dans les SoCs destinés à des applicationsvidéo. En raison de leur façon particulière du traitement du signal d'entrée, les CAN de type pipeline ont des codes de sortiequi ont la même largeur. Par conséquent, au lieu de considérer tous les codes lors du test, il est possible de se limiter à un sous-ensemble, ce qui permet de réduire considérablement le temps de test. Dans ce travail, une technique pour l'applicationdu test à code réduit pour les CANs de type pipeline est proposée. Elle exploite principalement deux propriétés de ce type deCAN et permet d'obtenir une très bonne estimation des performances statiques. La technique est validée expérimentalementsur un CAN 11-bit, 55nm de STMicroelectronics, obtenant une estimation de la NLD et de la NLI pratiquement identiques àla NLD et la NLI obtenues par la méthode classique d'histogramme, en utilisant la mesure de seulement 6% des codes.
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Renaud, Guillaume. "Auto test de convertisseurs de signal de type pipeline." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT064/document.

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Cette thèse vise l’étude de nouvelles architectures d’auto test pour les convertisseurs de type pipeline. En production, les convertisseurs sont testés en fonctionnement statique et dynamique. Les techniques de test statique de linéarité sont les techniques les plus coûteuses durant la phase de production. La mesure des performances statiques utilise un stimulus à haute linéarité et très basse fréquence et la méthode de l’histogramme, nécessitant la collecte d’un grand nombre d’échantillons en sortie afin de moyenner le bruit. Ainsi, la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d’attention. Récemment, des nouvelles solutions ont été mises au point pour réduire de façon importante le temps de test, mais aucune solution d’auto test considérant un générateur de signal de haute résolution en combinaison avec une technique d'analyse intégrée, réduisant considérablement la quantité de données, n’a encore été développée. Dans le cadre de cette thèse, on envisage l’étude de techniques d’auto test statique pour ce type de convertisseurs. En particulier, cette thèse présente un générateur de stimulus de test intégré à haute linéarité et une technique modifiée de servo-loop qui, en combinaison avec un algorithme de test de linéarité avec réduction de codes, conduit à la définition d'une stratégie efficace et précise de test intégré pour les CANs de type pipeline. La thèse inclut la validation expérimentale des techniques proposées, en coopération avec ST Microelectronics, Grenoble
This PhD thesis is aimed at exploring new Built-In-Self-Test (BIST) techniques for static linearity characterization of pipeline ADCs. During the production phase, the static and dynamic performances of the ADCs are tested. Static linearity test techniques are one of the more expensive test procedures that are performed at production line. The measurement of the static linearity performance requires the application of a low frequency high linearity stimulus and the collection of a high volume of output samples for noise averaging, usually using a histogram-based test setup. Thus, as the resolution of state-of-the-art ADCs increases, test time for static linearity characterization increases exponentially. For this reason, the reduction of the ADC test time is a hot topic that has gained an increasing interest over the past years. New techniques have recently been proposed to effectively reduce test time, but no BIST technique has yet been developed that considers a high resolution signal generator in combination with an on-chip analysis technique that dramatically reduces the amount of data. In this thesis, static linearity BIST techniques will be investigated for pipeline ADCs. In particular, this thesis presents a novel high-linearity on-chip test stimulus generator and a modified servo-loop technique that, in combination with reduced-code linearity test algorithms, lead to the definition of an efficient and accurate BIST strategy for pipeline ADCs. The work includes the experimental validation of the proposed techniques in collaboration with STMicroelectronics, Grenoble
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Dimakos, Athanasios. "Test embarqué des circuits RF en utilisant des capteurs non-intrusifs." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT019/document.

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Cette thèse discute le problème de test de production en grand volume des circuits radio-fréquences (RF) et à ondes millimétriques (mm-wave). Le test des fonctionnalités RF et à ondes millimétriques est très onéreux. Le test intégré est une alternative prometteuse pour faciliter la procédure et réduire les couts, mais il est difficile à mettre en œuvre car il ne faut en aucun cas qu'il réduit la performance du circuit sous test (CUT). Dans cette thèse, nous étudions une technique du test intégré qui repose sur l'utilisation de capteurs non-intrusifs qui prend en compte la variabilité du procédé de fabrication. Cette technique est extrêmement intéressante pour les concepteurs des circuits RF et mm-wave car il leur permet de dissocier le test de la conception. Les capteurs non-intrusifs sont constitués d'étages analogiques triviaux et de composants simples qui sont copiés de la topologie du CUT et sont placés sur la puce à proximité du CUT. Ils offrent simplement une "image" des variations du procédé de fabrication, ce qui leur permet de suivre les variations de performance du CUT. En substance, cette technique tire parti des phénomènes non désirés de variabilité de procédé de fabrication. Le paradigme du test alternatif est utilisé pour estimer les performances du CUT à partir des mesures des capteurs non intrusifs, afin de remplacer les tests standards qui mesurent les performances directement. Ce principe de test est appliqué à deux différents CUTs, nommément un amplificateur à bas bruit à 2.4GHz réalisé en CMOS 65nm et un amplificateur à bas bruit large bande à 60GHz réalisé en CMOS 65nm. Nous démontrons qu'en ajoutant quelques capteurs non-intrusifs sur la puce, qui n'engendrent pratiquement pas de surcout de surface, et en obtenant de ces capteurs non-intrusifs certaines mesures dans le domaine continu et à basse fréquence, nous sommes capable de suivre les variations de toutes les performances du CUT avec une erreur de prédiction moyenne inférieure à l’écart-type de la performance, et une erreur de prédiction maximum qui est inférieure ou au moins comparable aux erreurs de mesure dans un équipement de test automatisé conventionnel
This thesis addresses the high-volume production test problem for RF and millimeter-wave (mm-wave) circuits. Testing the RF/mm-wave functions of systems-on-chip (SoCs) incurs a very high cost. Built-in test is a promising alternative to facilitate testing and reduce costs, but it is challenging since it should by no means degrade the performance of the Circuit Under Test (CUT). In this work, we study a built-in test technique which is based on non-intrusive variation-aware sensors. The non-intrusive property is very appealing for designers since the sensors are totally transparent to the design and, thereby, the test is completely dissociated from the design. The non-intrusive sensors are dummy analog stages and single layout components that are copied from the topology of the CUT and are placed on the die in close physical proximity to the CUT. They simply offer an “image” of process variations and by virtue of this they are capable of tracking variations in the performances of the CUT. In essence, the technique capitalizes on the undesired phenomenon of process variations. The alternate test paradigm is employed to map the outputs of the non-intrusive sensors to the performances of the CUT, in order to replace the standard tests for measuring the performances directly. The proposed test idea is applied to two different CUTs, namely a 2.4GHz CMOS 65nm inductive degenerated Low-Noise Amplifier (LNA) and a wide-band mm-wave 60GHz CMOS 65nm 3-stage LNA. We demonstrate that by adding on-chip a few non-intrusive sensors of practically zero area-overhead and by obtaining on these non-intrusive sensors DC or low-frequency measurements, we are able to track variations in all performances of the CUT with an average prediction error lower than one standard deviation of the performance and a maximum prediction error that is lower or at least comparable to the measurement and repeatability errors in a conventional Automatic Test Equipment (ATE) environment
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Dubois, Matthieu. "Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633056.

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L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
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Joaquim, da Rolt Jean. "Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.

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Dans cette thèse, nous analysons les vulnérabilités introduites par les infrastructures de test, comme les chaines de scan, utilisées dans les circuits intégrés digitaux dédiés à la cryptographie sur la sécurité d'un système. Nous développons de nouvelles attaques utilisant ces infrastructures et proposons des contre-mesures efficaces. L'insertion des chaînes de scan est la technique la plus utilisée pour assurer la testabilité des circuits numériques car elle permet d'obtenir d'excellents taux de couverture de fautes. Toutefois, pour les circuits intégrés à vocation cryptographique, les chaînes de scan peuvent être utilisées comme une porte dérobée pour accéder à des données secrètes, devenant ainsi une menace pour la sécurité de ces données. Nous commençons par décrire une série de nouvelles attaques qui exploitent les fuites d'informations sur des structures avancées de conception en vue du test telles que le compacteur de réponses, le masquage de valeur inconnues ou le scan partiel, par exemple. Au travers des attaques que nous proposons, nous montrons que ces structures ne protégent en rien les circuits à l'inverse de ce que certains travaux antérieurs ont prétendu. En ce qui concerne les contre-mesures, nous proposons trois nouvelles solutions. La première consiste à déplacer la comparaison entre réponses aux stimuli de test et réponses attenduesde l'équipement de test automatique vers le circuit lui-même. Cette solution entraine un surcoût de silicium négligeable, n'aucun impact sur la couverture de fautes. La deuxième contre-mesure viseà protéger le circuit contre tout accès non autorisé, par exemple au mode test du circuit, et d'assurer l'authentification du circuit. A cet effet, l'authentification mutuelle utilisant le protocole de Schnorr basé sur les courbes elliptiques est mis en oeuvre. Enfin, nous montronsque les contre-mesures algorithmiques agissant contre l'analyse différentielle peuvent être également utilisées pour se prémunir contre les attaques par chaine de scan. Parmi celles-ci on citera en particulier le masquage de point et le masquage de scalaire
In this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
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Hély, David. "Conception en vue du test de circuits sécurisés." Montpellier 2, 2005. http://www.theses.fr/2005MON20123.

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Eldh, Sigrid. "On Test Design." Doctoral thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13040.

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Testing is the dominating method for quality assurance of industrial software. Despite its importance and the vast amount of resources invested, there are surprisingly limited efforts spent on testing research, and the few industrially applicable results that emerge are rarely adopted by industry. At the same time, the software industry is in dire need of better support for testing its software within the limited time available. Our aim is to provide a better understanding of how test cases are created and applied, and what factors really impact the quality of the actual test. The plethora of test design techniques (TDTs) available makes decisions on how to test a difficult choice. Which techniques should be chosen and where in the software should they be applied? Are there any particular benefits of using a specific TDT? Which techniques are effective? Which can you automate? What is the most beneficial way to do a systematic test of a system? This thesis attempts to answer some of these questions by providing a set of guidelines for test design, including concrete suggestions for how to improve testing of industrial software systems, thereby contributing to an improved overall system quality. The guidelines are based on ten studies on the understanding and use of TDTs. The studies have been performed in a variety of system domains and consider several different aspects of software test. For example, we have investigated some of the common mistakes in creating test cases that can lead to poor and costly testing. We have also compared the effectiveness of different TDTs for different types of systems. One of the key factors for these comparisons is a profound understanding of faults and their propagation in different systems. Furthermore, we introduce a taxonomy for TDTs based on their effectiveness (fault finding ability), efficiency (fault finding rate), and applicability. Our goal is to provide an improved basis for making well-founded decisions regarding software testing, together with a better understanding of the complex process of test design and test case writing. Our guidelines are expected to lead to improvements in testing of complex industrial software, as well as to higher product quality and shorter time to market.
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Benabdenbi, Mounir. "Conception en vue du test de systèmes intégrés sur silicium (SoC)." Paris 6, 2002. http://www.theses.fr/2002PA066031.

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Eudeline, Laurence. "Modélisation structurelle et fonctionnelle des circuits logiques en vue du test." Montpellier 2, 1991. http://www.theses.fr/1991MON20057.

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Ce memoire propose une modelisatin hierarchisee, structurelle et fonctionnelle des circuits logiques, fondee sur une etude approfondie de leur comportement. Une synthese bibliographique, relative a l'etat de l'art en matiere de test logique, revele l'insuffisance du modele a portes pour propager les donnees de test, saines ou fautives, de maniere rapide et aisee. Pour ce defaire de ce type de deficience, d'autres travaux avaient deja cherche a considerer les systemes digitaux d'un plus haut point de vue. La partie description comportementale de la modelisation presentee, introduit en sus les concepts d'incompatibilites fonctionnelles, de transparence et de blocage pour reduire le nombre de retours arrieres, qui entravent toute tache de propagation, en se degageant de la plupart des incoherences d'affectations. Elle est supportee par une representation structurelle simple et homogene, qui decoupe le circuit en blocs fonctionnels, sans omettre les primitives topologiques. Aussi, elle permet de traverser tout module, y compris ceux de logiques aleatoires combinatoires et sequentielles synchrones, en une seule fois, et de facon bidirectionnelle. La modelisation exposee conduit naturellement a une methodologie de propagation entierement dirigee par la fonctionnalite realisee par les structures parcourues
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Books on the topic "Design en vue du test"

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Turino, Jon L. Design to Test. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-011-6044-5.

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Rajaram, S., N. B. Balamurugan, D. Gracia Nirmala Rani, and Virendra Singh, eds. VLSI Design and Test. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5950-7.

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Gaur, Manoj Singh, Mark Zwolinski, Vijay Laxmi, Dharmendra Boolchandani, Virendra Sing, and Adit D. Sing, eds. VLSI Design and Test. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5.

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Sengupta, Anirban, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, and Santosh Kumar Vishvakarma, eds. VLSI Design and Test. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8.

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Kaushik, Brajesh Kumar, Sudeb Dasgupta, and Virendra Singh, eds. VLSI Design and Test. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7.

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Acciardi, Raymond G. Pinhole test equipment design and test result evaluation. Denver, Colo: Geotechnical Branch, Division of Research and Laboratory Services, Engineering and Research Center, U.S. Dept. of the Interior, Bureau of Reclamation, 1985.

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7

Stewart, George. Well test design and analysis. Tulsa, Okla: PennWell, 2010.

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Well test design and analysis. Tulsa, Okla: PennWell, 2010.

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9

Reis, Ricardo, Marcelo Lubaszewski, and Jochen A. G. Jess, eds. Design of Systems on a Chip: Design and Test. Boston, MA: Springer US, 2006. http://dx.doi.org/10.1007/0-387-32500-x.

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1969-, Janssen Dennis, and Pinkster Iris 1972-, eds. Integrated test design and automation: Using the test frame method. Reading, Mass: Addison-Wesley, 2001.

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Book chapters on the topic "Design en vue du test"

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Marwedel, Peter. "Test." In Embedded System Design, 321–33. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0257-8_8.

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Wu, Margaret, Hak Ping Tam, and Tsung-Hau Jen. "Test Design." In Educational Measurement for Applied Researchers, 41–57. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3302-5_3.

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Lee, Weng Fook. "Design for Test." In Learning from VLSI Design Experience, 73–109. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-03238-8_5.

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Loo-Dinkins, J. "Field Test Design." In Handbook of Quantitative Forest Genetics, 96–139. Dordrecht: Springer Netherlands, 1992. http://dx.doi.org/10.1007/978-94-015-7987-2_4.

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Ruff, Ronald. "Design Fluency Test." In Encyclopedia of Clinical Neuropsychology, 1118–21. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-57111-9_1426.

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Green, Anthony, and Glenn Fulcher. "Test Design Cycle." In The Routledge Handbook of Second Language Acquisition and Language Testing, 69–77. New York: Routledge, 2020. | Series: The Routledge handbooks in second language acquisition: Routledge, 2020. http://dx.doi.org/10.4324/9781351034784-9.

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Ruff, Ronald. "Design Fluency Test." In Encyclopedia of Clinical Neuropsychology, 821–22. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-0-387-79948-3_1426.

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Bhathagar, Himanshu. "Design for Test." In Advanced ASIC Chip Synthesis, 147–58. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4419-8668-9_8.

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Ruff, Ronald. "Design Fluency Test." In Encyclopedia of Clinical Neuropsychology, 1–2. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-56782-2_1426-2.

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Hörbst, Egon, Christian Müller-Schloer, and Heinz Schwärtzel. "Test Concepts." In Design of VLSI Circuits, 136–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-95525-9_4.

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Conference papers on the topic "Design en vue du test"

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Stansbury, Richard S., Massood Towhidnejad, Darris White, and Jack McKisson. "EcoEagles Hybrid Vehicle Control Architecture." In ASME 2009 3rd International Conference on Energy Sustainability collocated with the Heat Transfer and InterPACK09 Conferences. ASMEDC, 2009. http://dx.doi.org/10.1115/es2009-90310.

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The EcoCar Challenge provides 17 universities the opportunity to compete in the design and development of a new hybrid-vehicle based off of the 2009 Saturn Vue. At Embry-Riddle Aeronautical University, the vehicle’s initial architecture has been designed that provides the opportunity for the vehicle to operate in up to four different modes: electric only, series, parallel thru the road, and gas only. The control architecture is comprised of the various embedded controllers throughout the vehicle plus the addition of two new computer systems. The first is a safety critical supervisory controller responsible for configuring the vehicle into one of the hybrid modes. The second is the Intelligent Drive Efficiency Assistant (I.D.E.A), which is responsible for suggesting the best hybrid mode possible given the anticipated state of the vehicle. This paper will present the control architecture and the hardware/software-in-the-loop test bed necessary to verify and evaluate the architecture as it is developed.
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Gantt, Lynn R., Patrick M. Walsh, and Douglas J. Nelson. "Design and Development Process for a Range Extended Split Parallel Hybrid Electric Vehicle." In ASME 2010 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2010. http://dx.doi.org/10.1115/detc2010-28576.

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The Hybrid Electric Vehicle Team of Virginia Tech (HEVT) is participating in the 2009–2011 EcoCAR: The NeXt Challenge Advanced Vehicle Technology Competition series organized by Argonne National Lab (ANL), and sponsored by General Motors Corporation (GM) and the U.S. Department of Energy (DOE). The goal of EcoCAR is for student engineers to take a GM-donated crossover SUV and re-engineer it to reduce greenhouse gas emissions and petroleum energy use, while maintaining performance, safety and consumer appeal. Following GM’s Vehicle Development Process (VDP), HEVT established team goals that meet or exceed the competition requirements for EcoCAR in the design of a plug-in range-extended hybrid electric vehicle. HEVT is split up into three subteams to complete the competition and meet the requirements of the vehicle development process. The Mechanical subteam is tasked with modifying and refining the Year 1 component specifications and designs for packaging in the vehicle. The Electrical subteam is tasked with implementing a safe high voltage system on the vehicle including the design and development of a Lithium Iron Phosphate (LiFePO4) energy storage subsystem (ESS) donated by A123 Systems. The Controls subteam is tasked with modeling the Vehicle Technical Specifications (VTS) so that the subteams can make intelligent design decisions. The Controls subteam also used a controller Hardware-In-the-Loop (HIL) simulation setup running a real-time vehicle model against the controller hardware to test the HEVT-designed Hybrid Vehicle Supervisory Controller (HVSC). The result of this design process is an Extended-Range Electric Vehicle (E-REV) that uses grid electric energy and E85 fuel for propulsion. The vehicle design is predicted to achieve an SAE J1711 utility factor-corrected fuel consumption of 2.9 l(ge)/100 km (82 mpgge) with an estimated all-electric range of 69 km (43 miles). Using corn-based E85 fuel in North America for the 2015 timeframe and an average North American electricity mix, the well-to-wheels petroleum energy use and greenhouse gas emissions are reduced by 90% and 30% respectively when compared to the stock vehicle: a 4-cylinder, gasoline-fueled Vue XE.
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Sun, Jianhong, and Martin Hardwick. "Building an Integrated Large Scale Step Database for Virtual Enterprises." In ASME 1999 Design Engineering Technical Conferences. American Society of Mechanical Engineers, 1999. http://dx.doi.org/10.1115/detc99/dfm-8965.

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Abstract The rapid expansion of high performance computer networks such as the Internet allows companies to come together electronically to exploit emerging market conditions and produce new products. Such a group of companies has been called a virtual enterprise (VE). One barrier to VE collaboration is the lack of interoperability among the application systems of different companies — product data produced by the systems at one company cannot be read by the systems at another. STEP is a state-of-the-art technology for product data exchange and provides a basis for VE data sharing. In this paper, some challenges and difficulties of building an integrated large-scale database of STEP data are discussed. A prototype database was designed and implemented to test our solutions. Preliminary results show that the database is scalable and able to integrate STEP data. We believe the solutions are a basis for building a practical STEP database that can be used to support VE collaboration.
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Peng, Gaoliang, Wenjian Liu, Xinhua Liu, and Xin Li. "A Petri Net Based Interactive Manager Model for Virtual Maintenance Environment Application." In ASME 2010 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2010. http://dx.doi.org/10.1115/detc2010-29140.

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Interaction is one of the most important characteristic of VR system. In this paper, a kind of Hierarchical Timed Color Petri Net (HTCPN) is defined and an Interactive Manager Model (IMM) of Virtual Maintenance Environment (VME) is established based on HTCPN. With the inputs including operation data from dataglove, collision information between objects and recognized assembly relationship, the IMM output concrete operation event to realize the interactive actions in VME such as navigation, dragging, assembling and disassembling. The practice test illustrate that IMM satisfied the requirements of VME such as real-time and incurrent, as well as realized the treatment of numerous discrete events and the capture of operation intend during virtual maintenance operation.
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Cecil, J., and S. Albuhamood. "An Internet-of-Things Based Cyber-Physical Test Bed for Collaborative Manufacturing." In ASME 2016 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/imece2016-65029.

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The emergence of cyber physical frameworks has been catalyzed by various smart technologies including Next Generation Networks and 3D based Virtual Prototyping. Such frameworks hold the potential to support complex distributed collaborative practices in various engineering fields especially advanced manufacturing. This paper discusses the design and implementation of such a cyber physical framework based on Internet-of-Things (IoT) technologies while addressing semantic interoperability issues. The components of this framework is outlined along with an overview of the role of the emerging GENI based Next Internet technologies. The semantic framework is designed based on a Virtual Enterprise (VE) context where multiple organizations with similar as well as different capabilities can form temporary partnerships.
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Ellman, A., J. Laitinen, and T. Tiainen. "Combination of Virtual and Physical Objects in User-Centered Design of a Mobile Work Machine Cabin." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-41778.

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User-centred design methods improve the understanding of user work practices and enable construction of customized and user-friendly products. Applying these methods is, however, challenging since the users must to be able to test prototypes which is too time consuming and expensive with real prototypes. This is particularly true in the case of a mobile work machine cabin because the cabin forms an integral part of the machine so that elements need to be prototyped. The main properties of the cabin are the drivers’ visibility, functionality, ergonomics and safety. Virtual environment (VE) offers an effective way to realize prototyping and provides a means to study the drivers’ visual field from the cabin. Today’s design work is already performed using 3D CAD software. Introducing such models in VE is, however, not without its obstacles, since no native CAD format is supported in VE. Employing a general-purpose 3D graphics format usually destroys the model structure and also visualization parameters such as textures and lighting. When the aim is to have users test the functionality of the cabin, the VE model is unsatisfactory because certain physical parts are also required. First the bench is needed to ensure natural posture of the test driver. Second, the steering wheel and pedals are the objects with which the driver most typically interacts. Third, a set of control panels, including gauges and switches, are also often interacted by the driver. This study presents a setup for virtual testing of a mobile work machine cabin as a resource for user-centred design. The study focuses on the importance of physical objects in making the test situation realistic for hands-on professionals. The prototypes are tested by cabin design professionals experienced the use of CAD tools and real prototypes. The aim is to obtain designers’ evaluations and interpretations of different combinations of virtual and physical objects in prototypes. To achieve this a procedure for user-centred design of mobile work machine cabins is presented. More generally, the study discusses the participation of users in the design process employing VE as a design tool.
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Yi, Yan, and Zichun Li. "Design and Implementation of Music Web Application based on Vue and Spring Boot." In EITCE 2020: 2020 4th International Conference on Electronic Information Technology and Computer Engineering. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3443467.3443875.

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De Souza, Matheus, and Eduardo Alves da Silva. "Estudo Comparativo de Tecnologias de Desenvolvimento front-end paraWeb." In Computer on the Beach. São José: Universidade do Vale do Itajaí, 2021. http://dx.doi.org/10.14210/cotb.v12.p201-208.

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There are several JavaScript technologies intended to assist in theconstruction of web systems user interfaces. Choose the most suitablefor a new project can be a difficult task. Three of these technologieshave gained prominence: Angular, Vue and React. All focusedon the front-end development of web applications. In order to facilitatethe process of decision making about which technology is themost suitable in a new project, this work establishes a comparativestudy of the three most used JavaScript technologies currently andto highlight the advantages and disadvantages of each one. Thiswork adopted performance, size and support for different browsersto carry out an experimental comparative study. An applicationwas developed as a use case and replicated in each of the technologies,in order to analyze the development process and the resultsunder the same set of tests. A software to perform the tests in anautomated way was implemented to collect the performance resultsusing the Google Chrome browser. It was possible to identify whichtechnology is most suitable in each test scenario. For example, theAngular framework performed better in 8 out of 10 scenarios evaluated,despite having a longer startup time and build size of theapplication compared to React and Vue. It is estimated that Angularloads more information in the initialization process to make thestate of the application “more prepared” for user interactions
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Leis, Brian N., Robert J. Eiber, L. Carlson, and A. Gilroy-Scott. "Relationship Between Apparent (Total) Charpy Vee-Notch Toughness and the Corresponding Dynamic Crack-Propagation Resistance." In 1998 2nd International Pipeline Conference. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/ipc1998-2084.

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The consequences of a dynamic fracture in a gas-transmission pipeline require that pipelines be designed to avoid such incidents at a high level of certainty. For this reason, the related phenomonology has been studied since the early 1970s when the possibility of a dynamic ductile fracture was recognized. Full-scale experiments were done to characterize the fracture and gas dynamics associated with this process and empirical models were developed as a means to represent these experiments in a design or analysis setting. Such experiments focused on pure methane gas, and in the early days used steels with toughnesses less than 100 J, consistent with the steel making capabilities of the 1970s. Subsequently, interest shifted to larger diameter, higher pressure, higher BTU “rich” gases requiring higher toughness steels. The full-scale tests conducted to validate the arrest toughness levels determined that these empirical models were non-conservative. This paper presents a relationship between the dynamic crack propagation resistance and the apparent crack propagation resistance as measured by Charpy vee-notch (CVN) test specimens. This relationship is used in conjunction with the existing Battelle empirical criterion for dynamic-fracture arrest to determine the apparent toughness required to arrest a propagating ductile fracture in gas-transmission pipelines. The validity of this relationship is illustrated by successful predictions of arrest toughness in pipelines under a range of conditions including rich gases and high-toughness steels, including those showing a rising upper-shelf behavior.
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Guan, Cindy, Brian Rothwell, Joe Kondo, Masahiko Murata, and Keith Armstrong. "Full Scale Burst Validation Tests for Crack Arrestor Designs for NPS 48 Grade 550 Rich Gas Pipeline." In 2016 11th International Pipeline Conference. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/ipc2016-64112.

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Two full scale burst tests for the assessment of different crack arrestor designs were carried out on the pipes that will be used in the Coastal GasLink (CGL) Pipeline project. The tests supported by LNG Canada and TransCanada Technology Management Program were conducted at the Spadeadam test site of DNV GL, United Kingdom (UK), on 1219 mm (48 inch) outside diameter CSA Z245.1 Category II Grade 550 pipe at a nominal pressure of 13.38 MPa (1,940 psig) with 80% SMYS and temperature of −5°C, and with a gas representative of the richest gas envisaged for transport in the CGL pipeline project. The reservoirs are spaced with a gap between the reservoir ends of approximately 130 m, where the test section, comprising eleven pipe lengths and a tie-in pup, was installed. The centre of the test section consisted of an 18.5 mm thick low toughness initiation pipe. The remaining pipes were referenced as 1E to 5E in the easterly direction and similarly 1W to 5W in the westerly direction. The propagation pipes (1E and 1W) with 18.5 mm wall thickness, used to establish steady-state propagation, were located immediately either side of the central initiation pipe. For the first test, two crack arrestor pipes with 29.6 mm wall thickness were installed adjacent to the propagation pipes in the west and east directions, with a lead-in transition of 18.5 mm wall thickness for a distance of 130 mm then a 4:1 taper running back to the full pipe wall thickness. To the east, the first crack arrestor pipe had an average Charpy Vee-notch (CVN) energy of 246 J and to the west it had an average CVN energy of 341 J at the inboard end. In both directions, the fracture propagated from the initiation pipe, through the propagation pipes (1E/1W) before arresting in the first 29.6 mm thick crack arrestor pipes (2E/2W). In both directions, the arrest resulted in the fracture turning at the toe of the tapered transition on the front end of crack arrestor pipes 2E and 2W. The pipe arrangement for the second test was similar to the first one. In the east direction, in order to optimize crack arrestor design, two 24.7 mm wall thickness pipes replaced the 29.6 mm pipes which were used in the first test. In the west direction, the test section contained four 18.5 mm wall thickness test pipes arranged with a progressively increasing Charpy energy, up to 452 J. A low toughness, 18.5 mm thick pipe (5W), with a 1.8 m long Clock Spring® crack arrestor completed the test section. To the east, the fracture propagated from the initiation pipe through pipe 1E before arresting near the inboard end of the crack arrestor pipe 2E. In the west direction, the fracture was observed to run through all four of the pipes arranged with increasing CVN energy, before being arrested by the Clock Spring® crack arrestor fitted to the fifth pipe.
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Reports on the topic "Design en vue du test"

1

Gerassimenko, M. Test Design Calculations II. Office of Scientific and Technical Information (OSTI), July 2000. http://dx.doi.org/10.2172/793924.

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2

Stepanek, G. Uranium Plate Test Stack: Test of CC Design. Office of Scientific and Technical Information (OSTI), December 1985. http://dx.doi.org/10.2172/1030019.

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3

Kelley, Christopher Lee, and Brian Thomas Naughton. NRT Design Verification Test Plan. Office of Scientific and Technical Information (OSTI), December 2018. http://dx.doi.org/10.2172/1489535.

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4

Snead, Mary A., Yong Yan, Michael Howell, James R. Keiser, and Kurt A. Terrani. Severe Accident Test Station Design Document. Office of Scientific and Technical Information (OSTI), September 2015. http://dx.doi.org/10.2172/1252142.

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5

Grandy, C., H. Belch, A. J. Brunett, F. Heidet, R. Hill, E. Hoffman, E. Jin, et al. FASTER Test Reactor Preconceptual Design Report. Office of Scientific and Technical Information (OSTI), March 2016. http://dx.doi.org/10.2172/1345032.

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6

Hassan Ranganath, Nagarjun. Training Set Design for Test Removal Classication in IC Test. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.2028.

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7

Grandy, C., H. Belch, A. Brunett, F. Heidet, R. Hill, E. Hoffman, E. Jin, et al. FASTER test reactor preconceptual design report summary. Office of Scientific and Technical Information (OSTI), February 2016. http://dx.doi.org/10.2172/1246340.

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8

Lisowski, Darius D., Craig D. Gerardi, Rui Hu, Dennis J. Kilsdonk, Nathan C. Bremer, Stephen W. Lomperski, Adam R. Kraus, Matthew D. Bucknor, and Mitchell T. Farmer. Water NSTF Design, Instrumentation, and Test Planning. Office of Scientific and Technical Information (OSTI), August 2017. http://dx.doi.org/10.2172/1375452.

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9

Woloshun, Keith Albert, Gregory E. Dale, Eric Richard Olivas, Angela Carol Naranjo, and Frank Patrick Romero. 29 mm Diameter Test Target Design Report. Office of Scientific and Technical Information (OSTI), August 2016. http://dx.doi.org/10.2172/1325690.

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10

Hardin, Ernest. Deep Borehole Field Test Conceptual Design Report. Office of Scientific and Technical Information (OSTI), October 2016. http://dx.doi.org/10.2172/1431188.

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