Relevant bibliographies by topics / Design for testability

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Design for testability'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Design for testability"

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Ting-Hua Chen and M. A. Breuer. "Automatic Design for Testability Via Testability Measures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4, no. 1 (January 1985): 3–11. http://dx.doi.org/10.1109/tcad.1985.1270093.

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Roberts, D. H., J. A. Elmore, R. Balcombe, R. B. Bennett, and J. M. Hodge. "Design for testability." IEE Proceedings A Physical Science, Measurement and Instrumentation, Management and Education, Reviews 132, no. 4 (1985): 241. http://dx.doi.org/10.1049/ip-a-1.1985.0054.

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Bennetts, R. G., and M. A. Jack. "Design for testability." IEE Proceedings G (Electronic Circuits and Systems) 132, no. 3 (1985): 73. http://dx.doi.org/10.1049/ip-g-1.1985.0017.

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McGrew, Lydia. "Testability, Likelihoods, and Design." Philo 7, no. 1 (2004): 5–21. http://dx.doi.org/10.5840/philo2004711.

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Ungar, Louis Y. "Testability design prevents harm." IEEE Aerospace and Electronic Systems Magazine 25, no. 3 (March 2010): 35–43. http://dx.doi.org/10.1109/maes.2010.5463955.

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Zhou, Ping, and Dong Feng Liu. "Research on Design for Testability of Marine Diesel Engine." Applied Mechanics and Materials 110-116 (October 2011): 4234–39. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.4234.

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The rapid development of manufacturing industry making the pursuit of equipment performance increasingly demanding. Proceeded from design, considering testing and diagnosis problems from whole system and life cycle is an effective way to avoid major accidents and reduce the cost of maintenance, therefore, testability is widespread concerned. In this paper, taken marine diesel engine as research object, analyzed its necessity and feasibility of design for testability (DFT), through fully study of marine diesel engine’s testability characteristics, introduced multi-signal model to analysis marine diesel engine’s lubrication system testability, then advanced improvements for its testability, it can detect and isolate all faults of lubrication system, which provided a reference guide to marine diesel engine’s manufacturing.
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Liu, Ye, and Yi Chen Wang. "The Study of the Requirement of Software Testability Based on Causal Analysis." Applied Mechanics and Materials 513-517 (February 2014): 1944–50. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.1944.

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Requirements for software testability is an important basis of design for software design of testability. During the software-testability-design work, a series of software design for testability measures must be taken to make software testing stage less detours, and formulation and implementation of requirements for software testing is an important element. This paper introduces a kind of develop-method of requirements for software testability. According as causal analysis, basing on manifestations of software testability, the method develops appropriate requirements for software testability for software system. Preface The software testability is referred to as a kind of attribute that aims to facilitate the application test and improve the location and correction of software error [. To a certain extent, the software testability can solve some problems facing the software test, such as helping the designer to develop the software that is easier to test, so as to reduce the test difficulty, save more test time and optimize the resource allocation. Therefore, the software testability has stood out as quite an important factor that has a great effect on the cost, time and labor allocation of software test, which are also closely related to the quality of software engineering [. Since the 1990s, the software testability has been widely concerned by the scholars both at home and abroad. According to the relevant literatures collected, the general research direction has been toward the measurement and analysis of the software testability [. It should be noted that a well developed scheme of the requirement of software testability can not only enhance the testability of the target software, but also serve as the evaluation criterion of the testability, which means that it will have special reference to the improvement on the software test [. Based on the casual analysis, this paper has sought to provide a whole set of the requirement of software testability and come up with a real case so as to approach the design issues of the software testability [. 1 The requirement of software testability
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Zhao, Jing, Wen Jun Zhao, and Qiang Zhang. "Design and Realization of an Avionics Equipment Testability Model Based on TADS." Applied Mechanics and Materials 644-650 (September 2014): 964–67. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.964.

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The testability design becomes one of important works to do during a design process of a system and en equipment. Whereas, the testability labor of current avionics equipments are performed after design and most of its testability results are acquired by manual statistic. In this article, taking an aviation radio’s power supply model for example, a testability model is designed based on TADS and the scientificity and practicability of this model is testified by realizing fault separation by GPTS.
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Dssouli, R., K. Karoui, K. Saleh, and O. Cherkaoui. "Communications software design for testability: specification transformations and testability measures." Information and Software Technology 41, no. 11-12 (September 1999): 729–43. http://dx.doi.org/10.1016/s0950-5849(99)00033-6.

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Ooi, Chia Yee, and Hideo Fujiwara. "A New Design-for-Testability Method Based on Thru-Testability." Journal of Electronic Testing 27, no. 5 (September 1, 2011): 583–98. http://dx.doi.org/10.1007/s10836-011-5241-8.

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Dissertations / Theses on the topic "Design for testability"

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Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.

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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.
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Shi, Cheng. "High-level design for testability." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336135.

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Almajdoub, Salahuddin A. "A Design Methodology for Physical Design for Testability." Diss., Virginia Tech, 1996. http://hdl.handle.net/10919/30574.

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Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare faults, the design process utilizes a new parameter called the fault index. The fault index for a particular fault is the probability of occurrence of the fault divided by the testability of the fault. Faults with the highest fault indices are considered the worst faults and are targeted by the PDFT design process to eliminate them or reduce their probability of occurrence. An implementation of the PDFT design process is constructed using several new tools in addition to other "off-the-shelf" tools. The first tool developed in this work is a testability measure tool for bridging faults. Two other tools are developed to eliminate or reduce the probability of occurrence of bridging faults with high fault indices. The row enhancer targets faults inside the logic elements of the circuit, while the channel enhancer targets faults inside the routing part of the circuit. To demonstrate the capabilities and test the eff ectiveness of the PDFT design process, this work conducts an experiment which includes designing three CMOS circuits from the ISCAS 1985 benchmark circuits. Several layouts are generated for every circuit. Every layout, except the rst one, utilizes information from the previous layout to minimize the probability of occurrence for faults with high fault indices. Experimental results show that the PDFT design process successfully achieves two goals of PDFT, providing layouts with fewer faults and minimizing the probability of occurrence of hard-to-test faults. Improvement in the total fault index was about 40 percent in some cases, while improvement in total critical area was about 30 percent in some cases. However, virtually all the improvements came from using the row enhancer; the channel enhancer provided only marginal improvements.
Ph. D.
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Li, Lin. "RF transceiver front-end design for testability." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2256.

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In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.

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Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.

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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.
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Das, Debaleena. "Design-for-testability techniques for deep submicron technology /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.

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In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.
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Donglikar, Swapneel B. "Design for Testability Techniques to Optimize VLSI Test Cost." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/43712.

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High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test application time. The degree of test data volume reduction depends on the fault coverage achievable in the broadcast mode. However, the fault coverage achieved in the broadcast mode of ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern information from an a-priori automatic test pattern generation (ATPG) run. In this thesis, we present novel low cost techniques to construct ILS scan configuration for a given design. These techniques efficiently utilize the circuit topology information and try to optimize the flip-flop assignment to a scan chain location without much compromise in the fault coverage in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any test set information. In addition, we also propose a new scan architecture which combines the broadcast mode of ILS and Random Access Scan architecture to enable further test volume reduction on and above effectively configured conventional ILS architecture using the aforementioned heuristics with reasonable area overhead. Experimental results on the ISCASâ 89 benchmark circuits show that the proposed ILS configuration methods can achieve on an average 5% more fault coverage in the broadcast mode and on average 15% more test data volume and test application time reduction than existing methods. The proposed new architecture achieves, on an average, 9% and 33% additional test data volume and test application time reduction respectively on top of our proposed ILS configuration heuristics.
Master of Science
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Taylor, David. "Design of certain silicon semi-customised structures incorporating self-test." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329218.

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Vermaak, Hermanus Jacobus. "Design-for-delay-testability techniques for high-speed digital circuits." Enschede : University of Twente [Host], 2005. http://doc.utwente.nl/57440.

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Books on the topic "Design for testability"

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Tsui, Frank F. LSI/VLSI testability design. New York: McGraw-Hill, 1987.

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Engineering design: Reliability, maintainability, and testability. Blue Ridge Summit, PA: TAB Professional and Reference Books, 1988.

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Jones, James V. Engineering design: Reliability, maintainability, and testability. Blue Ridge Summit, PA: Tab Books, 1988.

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Logic testing and design for testability. Cambridge, Mass: MIT Press, 1985.

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Huhn, Sebastian, and Rolf Drechsler. Design for Testability, Debug and Reliability. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69209-4.

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Weyerer, Manfred. Testability of electronic circuits. Munich: C. Hanser, 1991.

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Weyerer, Manfred. Testability of electronic circuits. Munich: Carl Hanser Verlag, 1992.

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Petlin, Oleg Alexandrovich. Design for testability of asynchronous VLSI circuits. Manchester: University of Manchester, 1996.

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Larsson, Erik. An integrated system-level design for testability methodology. Linköping: Department of Computer and Information Science, Linköping University, 2000.

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Gebotys, Catherine H. Optimal VLSI Architectural Synthesis: Area, Performance and Testability. Boston, MA: Springer US, 1992.

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Book chapters on the topic "Design for testability"

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Sayil, Selahattin. "Testability Design." In Contactless VLSI Measurement and Testing Techniques, 9–15. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69673-7_2.

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Chen, Tinghuai. "Testability Design via Testability Measures." In Fault Diagnosis and Fault Tolerance, 95–118. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/978-3-642-77179-8_3.

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Turino, Jon L. "Testability Busses." In Design to Test, 225–49. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-011-6044-5_10.

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Turino, Jon L. "Testability Documentation." In Design to Test, 283–90. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-011-6044-5_14.

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Kurup, Pran, and Taher Abbasi. "Design for Testability." In Logic Synthesis Using Synopsys®, 197–241. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2370-0_6.

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Rülling, Wolfgang. "Design for Testability." In The Electronic Design Automation Handbook, 339–81. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_15.

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Bhattacharya, Debashis, and John P. Hayes. "Design for Testability." In The Kluwer International Series in Engineering and Computer Science, 97–127. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1527-8_4.

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Kurup, Pran, and Taher Abbasi. "Design for Testability." In Logic Synthesis Using Synopsys®, 209–43. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4613-1455-4_8.

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Taraate, Vaibbhav. "Design for Testability." In ASIC Design and Synthesis, 217–27. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4642-0_14.

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Williams, T. "Design for Testability." In Handbook of Advanced Semiconductor Technology and Computer Systems, 425–62. Dordrecht: Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-011-7056-7_14.

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Conference papers on the topic "Design for testability"

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Flynn, D. W. "Modular bus design supports on-chip testability." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950548.

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THOMPSON, KEVIN. "Three phases of testability." In Aircraft Design, Systems and Operations Conference. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1988. http://dx.doi.org/10.2514/6.1988-4454.

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Maunder, C. "Design for test standards - where are they taking us?" In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950547.

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Grist, D. A. "The cost of C-testability in terms of silicon area and design complexity." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950549.

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Russell, G. "Teaching of testing techniques: the why, what and how?" In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950550.

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Wilkins, B. R. "Stretching the boundary: mixed-signals and P1149.4." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950551.

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Robson, M. "Digital techniques for testing analogue functions." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950552.

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Moorehead, J. D. "Testability aspects of a DSP based image processing system." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950553.

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Cooper, R. "The development and application of intelligent self test concepts in reconfigurable modular avionic systems." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950554.

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O'Dare, M. J. "System design for test using a genetically based hierarchical ATPG system." In IEE Colloquium on `Systems Design for Testability'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950555.

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Reports on the topic "Design for testability"

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Zhou, Lixin. Testability Design and Testability Analysis of a Cube Calculus Machine. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6787.

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Press, Ronald E., Michael E. Keller, and Gregory J. Maguire. Testability Design Rating System: Analytical Procedure. Volume 2. Fort Belvoir, VA: Defense Technical Information Center, February 1992. http://dx.doi.org/10.21236/ada254334.

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