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Books on the topic 'Design for testability'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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1

Tsui, Frank F. LSI/VLSI testability design. New York: McGraw-Hill, 1987.

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2

Engineering design: Reliability, maintainability, and testability. Blue Ridge Summit, PA: TAB Professional and Reference Books, 1988.

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3

Jones, James V. Engineering design: Reliability, maintainability, and testability. Blue Ridge Summit, PA: Tab Books, 1988.

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4

Logic testing and design for testability. Cambridge, Mass: MIT Press, 1985.

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5

Huhn, Sebastian, and Rolf Drechsler. Design for Testability, Debug and Reliability. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69209-4.

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6

Weyerer, Manfred. Testability of electronic circuits. Munich: C. Hanser, 1991.

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7

Weyerer, Manfred. Testability of electronic circuits. Munich: Carl Hanser Verlag, 1992.

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8

Petlin, Oleg Alexandrovich. Design for testability of asynchronous VLSI circuits. Manchester: University of Manchester, 1996.

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9

Larsson, Erik. An integrated system-level design for testability methodology. Linköping: Department of Computer and Information Science, Linköping University, 2000.

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10

Gebotys, Catherine H. Optimal VLSI Architectural Synthesis: Area, Performance and Testability. Boston, MA: Springer US, 1992.

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11

Huertas, José L. Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Boston, MA: Springer US, 2004.

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12

Huertas, José L. Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Boston, MA: Springer US, 2004.

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13

Huertas, José L., ed. Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9.

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14

Davidson, John Carl. Implementation of a Design for Testability strategy using the Genesil silicon compiler. Monterey, California: Naval Postgraduate School, 1989.

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15

Loureiro, G. V. Digital systems design for testability based on a reed-muller tree-circuit approach: Design and application of a CAD system for the minimization design and fault simulation of reed-muller tree-circuits. Manchester: UMIST, 1993.

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16

Vlsi Design for (Self- Testability). CRC, 1996.

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17

Tripathi, Suman Lata, Sobhit Saxena, and Sushanta Kumar Mohapatra. Advanced VLSI Design and Testability Issues. Taylor & Francis Group, 2020.

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18

Dick, John Henry, C. Dislis, I. D. Dear, and A. P. Ambler. Test Economics and Design for Testability. Prentice Hall, 1995.

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19

Advanced VLSI Design and Testability Issues. Taylor & Francis Group, 2020.

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20

Fujiwara, Hideo. Logic Testing and Design for Testability. MIT Press, 1985.

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21

Dick, John Henry, C. Dislis, I. D. Dear, and A. P. Ambler. Test Economics and Design for Testability. Prentice Hall, 1995.

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22

Tripathi, Suman Lata, Sobhit Saxena, and Sushanta Kumar Mohapatra. Advanced VLSI Design and Testability Issues. Taylor & Francis Group, 2020.

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23

Tripathi, Suman Lata, Sobhit Saxena, and Sushanta Kumar Mohapatra. Advanced VLSI Design and Testability Issues. Taylor & Francis Group, 2020.

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24

Fujiwara, Hideo. Logic Testing and Design for Testability. The MIT Press, 1985. http://dx.doi.org/10.7551/mitpress/4317.001.0001.

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25

Lubaszewski, Marcelo, Jose Huertas, Adoracion Rueda, and Andrew Richardson. Analog and Mixed Signal Design for Testability. John Wiley & Sons, 2004.

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26

Margala, Martin, and Sule Ozev. Design for Testability for RF Circuits and Systems. Springer, 2017.

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27

Laung-Terng, Wang, Wu, Cheng-Wen, EE Ph. D, and Wen Xiaoqing, eds. VLSI test principles and architectures: Design for testability. Amsterdam: Elsevier Morgan Kaufmann Publishers, 2006.

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28

Ozev, S. Testing and Design-for-Testability for RF Wireless Transceivers. 2nd ed. Springer, 2008.

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29

System-on-chip test architectures: Nanometer design for testability. Amsterdam: Morgan Kaufmann Publishers, 2008.

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30

Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer, 2004.

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31

C, Dislis, ed. Test economics and design for testability for electronic circuits and systems. New York: Ellis Horwood, 1995.

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32

Wang, Laung-Terng, Cheng-Wen Wu, and Xiaoqing Wen. VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon). Morgan Kaufmann, 2006.

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33

Wang, Laung-Terng, Cheng-Wen Wu, and Xiaoqing Wen. VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon). Morgan Kaufmann, 2006.

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34

Chakrabarty, Krishnendu, Tsung-Yi Ho, and Kai Hu. Computer-Aided Design of Microfluidic Very Large Scale Integration Biochips: Design Automation, Testing, and Design-for-Testability. Springer, 2017.

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35

Chakrabarty, Krishnendu, Tsung-Yi Ho, and Kai Hu. Computer-Aided Design of Microfluidic Very Large Scale Integration Biochips: Design Automation, Testing, and Design-for-Testability. Springer, 2018.

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36

Developing Electronic Systems for Testability Using Electronic Design Automation (EDA) and Standards. ERA Technology Ltd, 1993.

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37

Leenstra, J. Hierarchical test development and design-for-testability for (A)synchronous semi-custom ASICs. 1993.

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38

The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500 (Frontiers in Electronic Testing). Springer, 2006.

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