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1
Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.
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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.
2
Shi, Cheng. "High-level design for testability." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336135.
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Almajdoub, Salahuddin A. "A Design Methodology for Physical Design for Testability." Diss., Virginia Tech, 1996. http://hdl.handle.net/10919/30574.
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Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare faults, the design process utilizes a new parameter called the fault index. The fault index for a particular fault is the probability of occurrence of the fault divided by the testability of the fault. Faults with the highest fault indices are considered the worst faults and are targeted by the PDFT design process to eliminate them or reduce their probability of occurrence.
An implementation of the PDFT design process is constructed using several new tools in addition to other "off-the-shelf" tools. The first tool developed in this work is a testability measure tool for bridging faults. Two other tools are developed to eliminate or reduce the probability of occurrence of bridging faults with high fault indices. The row enhancer targets faults inside the logic elements of the circuit, while the channel enhancer targets faults inside the routing part of the circuit.
To demonstrate the capabilities and test the eff ectiveness of the PDFT design process, this work conducts an experiment which includes designing three CMOS circuits from the ISCAS 1985 benchmark circuits. Several layouts are generated for every circuit. Every layout, except the rst one, utilizes information from the previous layout to minimize the probability of occurrence for faults with high fault indices. Experimental results show that the PDFT design process successfully achieves two goals of PDFT, providing layouts with fewer faults and minimizing the probability of occurrence of hard-to-test faults. Improvement in the total fault index was about 40 percent in some cases, while improvement in total critical area was about 30 percent in some cases. However, virtually all the improvements came from using the row enhancer; the channel enhancer provided only marginal improvements.Ph. D.
4
Li, Lin. "RF transceiver front-end design for testability." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2256.
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In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.
5
Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.
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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.
6
Das, Debaleena. "Design-for-testability techniques for deep submicron technology /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.
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In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.
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Donglikar, Swapneel B. "Design for Testability Techniques to Optimize VLSI Test Cost." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/43712.
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High test data volume and long test application time are two major concerns for testing
scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective
in addressing both these issues. The ILS achieves a high degree of test data compression
thereby reducing both the test data volume and test application time. The degree of test
data volume reduction depends on the fault coverage achievable in the broadcast mode.
However, the fault coverage achieved in the broadcast mode of ILS architecture depends
on the actual configuration of individual scan chains, i.e., the number of chains and the
mapping of the individual flip-flops of the circuit to the respective scan chain positions.
Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern
information from an a-priori automatic test pattern generation (ATPG) run. In this thesis,
we present novel low cost techniques to construct ILS scan configuration for a given design.
These techniques efficiently utilize the circuit topology information and try to optimize the
flip-flop assignment to a scan chain location without much compromise in the fault coverage
in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any
test set information. In addition, we also propose a new scan architecture which combines
the broadcast mode of ILS and Random Access Scan architecture to enable further test
volume reduction on and above effectively configured conventional ILS architecture using
the aforementioned heuristics with reasonable area overhead. Experimental results on the
ISCASâ 89 benchmark circuits show that the proposed ILS configuration methods can achieve
on an average 5% more fault coverage in the broadcast mode and on average 15% more test
data volume and test application time reduction than existing methods. The proposed new
architecture achieves, on an average, 9% and 33% additional test data volume and test
application time reduction respectively on top of our proposed ILS configuration heuristics.Master of Science
9
Taylor, David. "Design of certain silicon semi-customised structures incorporating self-test." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329218.
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Vermaak, Hermanus Jacobus. "Design-for-delay-testability techniques for high-speed digital circuits." Enschede : University of Twente [Host], 2005. http://doc.utwente.nl/57440.
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Rahagude, Nikhil Prakash. "Integrated Enhancement of Testability and Diagnosability for Digital Circuits." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/35609.
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While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metric to identify such TD points. Further, we propose a new DFT + DFD architecture, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. Our experiments indicate that the proposed architecture can distinguish 4x more previously indistinguishable fault-pairs than existing DFT architectures while maintaining similar fault coverages. Further, the experiments illustrate that quality results can be achieved with an area overhead of around 5%. Additional experiments conducted on hard-to-test circuits show an increase in fault coverage by 48% while maintaining similar diagnostic resolution.
Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment (ATE). At the end of a test session, BIST generates a signature which is a compaction of the obtained output responses of the circuit for that session. Comparison of this signature with the reference signature categorizes the circuit as error free or buggy. While BIST provides a quick and low cost alternative to check circuit's correctness, diagnosis in BIST environment remains poor because of the limited information present in the lossily compacted final signature. The signature does not give any information about the possible defect location in the circuit. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories,response memory to store reference responses and fail memory to store failing responses. We propose a novel architecture in which only one additional memory is required. Experimental results conducted on benchmark circuits substantiate that the same fault coverage can be maintained using just 5% of the available test vectors. This reduces the size of memory required to store responses which in turn reduces area overhead. Further, by adding test points to the circuit using our proposed architecture, we can improve the diagnostic resolution by 60% with respect to external testing.Master of Science
12
Ramzan, Rashad. "Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18208.
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In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio. Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction. In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test. Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose. Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line. In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.
13
Ramzan, Rashad M. "Flexible wireless receivers : on-chip testing techniques and design for testability /." Linköping : Department of of Electrical Engineering, Linköping University, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18208.
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Ho, Chung Kin. "Fault diagnosis and design for testability applied to analogue integrated circuits." Thesis, University of Bath, 1998. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242531.
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Chiang, Kang-Chung. "Scan path design of PLA to improve its testability in VLSI realization." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183128113.
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Davidson, John Carl. "Implementation of a Design for Testability strategy using the Genesil silicon compiler." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/27087.
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Design for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurations
17
Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.
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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.
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Sayers, I. L. "An investigation of 'design for testability' techniques in very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.370643.
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Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.
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Lawson, John Ernest. "Implementation of residue code as a design for testability strategy using GENESIL Silicon Compiler." Thesis, Monterey, California: Naval Postgraduate School, 1990. http://hdl.handle.net/10945/27620.
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Approved for public release; distribution unlimited.This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon compiler. Two structured techniques of design for testability, Scan Design and Built-in Self Test, are discussed. Also, the methodology used to implement the residue code with GENESIL for testing the multiply-add module of a second-order Infinite Impulse Response notch filter is presented. The cost, in terms of increased hardware and decreased performance, associated with implementing the residue code is examined by comparing modulo-3 and modulo-15 checking algorithms.
21
Suparjo, Bambang Sunaryo. "Testing analogue circuits : design for testability structures and an investigation into supply current modelling." Thesis, University of Southampton, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239871.
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Pooler, Brian Lee. "A methodology for producing and testing a Genesil Silicon Compiler designed VLSI chip which incorporates Design for Testability." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA239465.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.Thesis Advisor(s): Loomis, Herschel H. Second Reader: Yang, Chyan. "September 1990." Description based on title screen as viewed on December 17, 2009. DTIC Descriptor(s): Scanning, Conversion, Files(Records), Simulation, Methodology, Models, Paths, Very Large Scale Integration, Time, Engineering, Silicon, Vector Analysis, Compilers, Automatic, Faults, Test And Evaluation. DTIC Identifier(s): Computer Aided Design, Circuit Testers, Theses. Author(s) subject terms: Design for testability, VLSI, Genesil Silicon Compiler, Automatic Test Generation, DAS 9100, DV550. Includes bibliographical references (p. 161-162). Also available in print.
23
Pendurkar, Rajesh. "Design for testability techniques and optimization algorithms for performance and functional testing of mult-chip module interconnections." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16635.
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Nguyen, Huy Tam. "Numerical transformations for area, power, and testability optimization in the synthesis of digtal signal processing ASICs." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13548.
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Jett, David B. "Selection of flip-flops for partial scan paths by use of a statistical testability measure." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-12302008-063234/.
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Rodrigues, Raphael de Oliveira. "Aplicação de design for testability na elaboração de requisitos de testes de produção no desenvolvimento de sistemas aeronáuticos." Instituto Tecnológico de Aeronáutica, 2011. http://www.bd.bibl.ita.br/tde_busca/arquivo.php?codArquivo=2797.
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Esta dissertação tem como objetivo estruturar a aplicação do Design for Testability (DFT) - procedimento que durante a fase de desenvolvimento de um novo produto incorpora regras e técnicas para tornar a execução de testes mais eficiente - no processo de elaboração de requisitos de testes de produção durante o desenvolvimento de sistemas aeronáuticos. A partir dessa aplicação, pretende-se obter a redução do ciclo de testes de produção em série de uma aeronave e a redução dos custos relativos a estes testes, além de realizar uma análise e otimização do processo atual. Para isso, foi necessária a análise do estado atual do processo e proposta de uma nova metodologia a fim de prover, além dos conceitos de DFT, robustez e padronização ao processo, garantindo assim o melhor aproveitamento dos recursos, a eliminação de desperdícios e a diminuição dos custos no processo produtivo. A aplicação do processo proposto foi simulada em parte do desenvolvimento de sistemas aeronáuticos em uma situação real, sendo evidenciados os ganhos obtidos a partir de sua aplicação, contribuindo com a redução de aproximadamente 33% do ciclo total de testes de produção durante a etapa de Montagem Final da aeronave.
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Munugala, Anvesh. "An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology." Youngstown State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399.
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ITO, Hideo, and Gang ZENG. "Low-Cost IP Core Test Using Tri-Template-Based Codes." Institute of Electronics, Information and Communication Engineers, 2007. http://hdl.handle.net/2237/15029.
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Banga, Mainak. "Testing and Verification Strategies for Enhancing Trust in Third Party IPs." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/30085.
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Globalization in semiconductor industry has surged up the trend of outsourcing component design and manufacturing process across geographical boundaries. While cost reduction and short time to market are the driving factors behind this trend, the authenticity of the final product remains a major question. Third party deliverables are solely based on mutual trust and any manufacturer with a malicious intent can fiddle with the original design to make it work otherwise than expected in certain specific situations. In case such a backfire happens, the consequences can be disastrous especially for mission critical systems such as space-explorations, defense equipments such as missiles, life saving equipments such as medical gadgets where a single failure can translate to a loss of lives or millions of dollars. Thus accompanied with outsourcing, comes the question of trustworthy design - "how to ensure that integrity of the product manufactured by a third party has not been compromised".
This dissertation aims towards developing verification methodologies and implementing non-destructive testing strategies to ensure the authenticity of a third party IP. This can be accomplished at various levels in the IC product life cycle. At the design stage, special testability features can be incorporated in the circuit to enhance its overall testability thereby making the otherwise hard to test portions of the design testable at the post silicon stage. We propose two different approaches to enhance the testability of the overall circuit. The first allows improved at-speed testing for the design while the second aims to exaggerate the effect of unwanted tampering (if present) on the IC. At the verification level, techniques like sequential equivalence checking can be employed to compare the third-party IP against a genuine specification and filter out components showing any deviation from the intended behavior. At the post silicon stage power discrepancies beyond a certain threshold between two otherwise identical ICs can indicate the presence of a malicious insertion in one of them. We have addressed all of them in this dissertation and suggested techniques that can be employed at each stage. Our experiments show promising results for detecting such alterations/insertions in the original design.Ph. D.
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Juracy, Leonardo Rezende. "Testing the blade resilient asynchronous template : a structural approach." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2018. http://tede2.pucrs.br/tede2/handle/tede/8167.
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Atualmente, a abordagem s?ncrona ? a mais utilizada em projeto de circuitos integrados por ser altamente automatizado pelas ferramentas comerciais e por incorporar margens de tempo para garantir o funcionamento correto nos piores cen?rios de varia??es de processo e ambiente, limitando otimiza??es no per?odo do rel?gio e aumentando o consumo de pot?ncia. Por um lado, circuitos ass?ncronos apresentam algumas vantagens em potencial quando comparados com os circuitos s?ncronos, como menor consumo de pot?ncia e maior vaz?o de dados, mas tamb?m podem sofrer com varia??es de processo e ambiente. Por outro lado, circuitos resilientes s?o uma alternativa para manter o circuito funcionando na presen?a de efeitos de varia??o. Sendo assim, foi proposto o circuito Blade que combina as vantagens de circuitos ass?ncronos com circuitos resilientes. Blade utiliza latches em sua implementa??o e mant?m seu desempenho em cen?rios de caso m?dio. Independentemente do estilo de projeto (s?ncrono ou ass?ncrono), durante o processo de fabrica??o de circuitos integrados, algumas imperfei??es podem acontecer, causando defeitos que reduzem o rendimento de fabrica??o. Circuitos defeituosos podem apresentar um comportamento falho, gerando uma sa?da diferente da esperada, devendo ser identificados antes de sua comercializa??o. Metodologias de teste podem ajudar na identifica??o e diagn?stico desse comportamento falho. Projeto visando testabilidade (do ingl?s, Design for Testability - DfT) aumenta a testabilidade do circuito adicionando um grau de controlabilidade e observabilidade atrav?s de diferentes t?cnicas. Scan ? uma t?cnica de DfT que fornece para um equipamento de teste externo acesso aos elementos de mem?ria internos do circuito, permitindo inser??o de padr?es de teste e compara??o da resposta. O objetivo deste trabalho ? propor uma abordagem de DfT estrutural, completamente autom?tica e integrada com as ferramentas comerciais de projeto de circuitos, incluindo uma s?rie de m?todos para lidar com os desafios relacionados ao teste de circuitos ass?ncronos e resilientes, com foco no Blade. O fluxo de DfT proposto ? avaliado usando um m?dulo criptogr?fico e um microprocessador. Os resultados obtidos para o m?dulo criptogr?fico mostram uma cobertura de falha de 98,17% para falhas do tipo stuck-at e 89,37% para falhas do tipo path-delay, com um acr?scimo de ?rea de 112,16%. Os resultados obtidos para o microprocessador mostram uma cobertura de 96,04% para falhas do tipo stuck-at e 99,00% para falhas do tipo path-delay, com um acr?scimo de ?rea de 50,57%.
Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worstcase scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.
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Hays, Mark A. "A Fault-Based Model of Fault Localization Techniques." UKnowledge, 2014. http://uknowledge.uky.edu/cs_etds/21.
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Every day, ordinary people depend on software working properly. We take it for granted; from banking software, to railroad switching software, to flight control software, to software that controls medical devices such as pacemakers or even gas pumps, our lives are touched by software that we expect to work. It is well known that the main technique/activity used to ensure the quality of software is testing. Often it is the only quality assurance activity undertaken, making it that much more important.
In a typical experiment studying these techniques, a researcher will intentionally seed a fault (intentionally breaking the functionality of some source code) with the hopes that the automated techniques under study will be able to identify the fault's location in the source code. These faults are picked arbitrarily; there is potential for bias in the selection of the faults. Previous researchers have established an ontology for understanding or expressing this bias called fault size. This research captures the fault size ontology in the form of a probabilistic model. The results of applying this model to measure fault size suggest that many faults generated through program mutation (the systematic replacement of source code operators to create faults) are very large and easily found. Secondary measures generated in the assessment of the model suggest a new static analysis method, called testability, for predicting the likelihood that code will contain a fault in the future.
While software testing researchers are not statisticians, they nonetheless make extensive use of statistics in their experiments to assess fault localization techniques. Researchers often select their statistical techniques without justification. This is a very worrisome situation because it can lead to incorrect conclusions about the significance of research. This research introduces an algorithm, MeansTest, which helps automate some aspects of the selection of appropriate statistical techniques. The results of an evaluation of MeansTest suggest that MeansTest performs well relative to its peers. This research then surveys recent work in software testing using MeansTest to evaluate the significance of researchers' work. The results of the survey indicate that software testing researchers are underreporting the significance of their work.
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Joaquim, da Rolt Jean. "Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.
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Dans cette thèse, nous analysons les vulnérabilités introduites par les infrastructures de test, comme les chaines de scan, utilisées dans les circuits intégrés digitaux dédiés à la cryptographie sur la sécurité d'un système. Nous développons de nouvelles attaques utilisant ces infrastructures et proposons des contre-mesures efficaces. L'insertion des chaînes de scan est la technique la plus utilisée pour assurer la testabilité des circuits numériques car elle permet d'obtenir d'excellents taux de couverture de fautes. Toutefois, pour les circuits intégrés à vocation cryptographique, les chaînes de scan peuvent être utilisées comme une porte dérobée pour accéder à des données secrètes, devenant ainsi une menace pour la sécurité de ces données. Nous commençons par décrire une série de nouvelles attaques qui exploitent les fuites d'informations sur des structures avancées de conception en vue du test telles que le compacteur de réponses, le masquage de valeur inconnues ou le scan partiel, par exemple. Au travers des attaques que nous proposons, nous montrons que ces structures ne protégent en rien les circuits à l'inverse de ce que certains travaux antérieurs ont prétendu. En ce qui concerne les contre-mesures, nous proposons trois nouvelles solutions. La première consiste à déplacer la comparaison entre réponses aux stimuli de test et réponses attenduesde l'équipement de test automatique vers le circuit lui-même. Cette solution entraine un surcoût de silicium négligeable, n'aucun impact sur la couverture de fautes. La deuxième contre-mesure viseà protéger le circuit contre tout accès non autorisé, par exemple au mode test du circuit, et d'assurer l'authentification du circuit. A cet effet, l'authentification mutuelle utilisant le protocole de Schnorr basé sur les courbes elliptiques est mis en oeuvre. Enfin, nous montronsque les contre-mesures algorithmiques agissant contre l'analyse différentielle peuvent être également utilisées pour se prémunir contre les attaques par chaine de scan. Parmi celles-ci on citera en particulier le masquage de point et le masquage de scalaireIn this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
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Lautner, Erik, and Daniel Körner. "An integrated System Development Approach for Mobile Machinery in consistence with Functional Safety Requirements." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-200666.
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The article identifies the challenges during the system and specifically the software development process for safety critical electro-hydraulic control systems by using the example of the hydrostatic driveline with a four speed transmission of a feeder mixer. An optimized development approach for mobile machinery has to fulfill all the requirements according to the Machinery Directive 2006/42/EC, considering functional safety, documentation and testing requirements from the beginning and throughout the entire machine life cycle. The functionality of the drive line control could be verified in advance of the availability of a prototype by using a “software-in-the-loop” development approach, based on a MATLAB/SIMULINK model of the drive line in connection with the embedded software.
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Ng, Chi Long. "Non-scan Design For Testability of digital circuits based on Genetic Algorithm = 基於基因算法的數字電路非掃描可測性設計." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1445654.
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Bonet, Zordan Leonardo Henrique. "Test de mémoires SRAM à faible consommation." Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20080.
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De nos jours, les mémoires embarquées sont les composants les plus denses dans les "System-On-Chips" (SOCs), représentant actuellement plus que 90% de leur superficie totale. Parmi les différents types de mémoires, les SRAMs sont très largement utilisées dans la conception des SOCs, particulièrement en raison de leur haute performance et haute densité d'intégration. En revanche, les SRAMs conçues en utilisant des technologies submicroniques sont devenus les principaux contributeurs de la consommation d'énergie globale des SOCs. Par conséquent, un effort élevé est actuellement consacré à la conception des SRAMs à faible consommation. En plus, en raison de leur structure dense, les SRAMs sont devenus de plus en plus susceptibles aux défauts physiques comparativement aux autres blocs du circuit, notamment dans les technologies les plus récentes. Par conséquent, les SRAMs se posent actuellement comme le principal détracteur du rendement des SOCs, ce qui cause la nécessité de développer des solutions de test efficaces ciblant ces dispositifs.Dans cette thèse, des simulations électriques ont été réalisées pour prédire les comportements fautifs causés par des défauts réalistes affectant les blocs de circuits spécifiques aux technologies SRAM faible consommation. Selon les comportements fautifs identifiés, différents tests fonctionnels, ainsi que des solutions de tests matériels, ont été proposés pour détecter les défauts étudiés. Par ailleurs, ce travail démontre que les circuits d'écriture et lecture, couramment incorporés dans les SRAMs faible consommation, peuvent être réutilisés pour augmenter le stress dans les SRAMs lors du test, ce qui permet d'améliorer la détection des défauts affectant la mémoireNowadays, embedded memories are the densest components within System-On-Chips (SOCs), accounting for more than 90% of the overall SOC area. Among different types of memories, SRAMs are still widely used for realizing complex SOCs, especially because they allow high access performance, high density and fast integration in CMOS designs. On the other hand, high density SRAMs designed with deep-submicrometer technologies have become the main contributor to the overall SOC power consumption. Hence, there is an increasing need to design low-power SRAMs, which embed mechanisms to reduce their power consumption. Moreover, due to their dense structure, SRAMs are more are more prone to defects compared to other circuit blocks, especially in recent technologies. Hence, SRAMs are arising as the main SOC yield detractor, which raises the need to develop efficient test solutions targeting such devices.In this thesis, failure analysis based on electrical simulations has been exploited to predict faulty behaviors caused by realistic defects affecting circuit blocks that are specific to low-power SRAMs, such as power gating mechanisms and voltage regulation systems. Based on identified faulty behaviors, efficient March tests and low area overhead design for testability schemes have been proposed to detect studied defects. Moreover, the reuse of read and write assist circuits, which are commonly embedded in low-power SRAMs, has been evaluated as an alternative to increase stress in the SRAM during test phase and then improve the defect coverage
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Aquino, guazzelli Ricardo. "test and side-channel analysis of asynchronous circuits." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT070.
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Les circuits asynchrones ont été explorés au cours des dernières décennies comme une alternative pour surmonter les problèmes et les limites apportés par la conception synchrone, en particulier lorsque les nœuds technologiques récents atteignent des limites physiques et que les variations de processus, de tension et de température (PVT) ont un impact significatif sur le comportement des circuits.Cela fait progresser l'utilisation de circuits asynchrones dans différentes applications nécessitant une grande vitesse, une faible consommation d'énergie, de la robustesse ou de la sécurité.En raison de leur style de conception non conventionnel, il n'est pas si banal de les concevoir.En effet, la conception asynchrone est peu enseignée dans les écoles d'ingénieurs et son flux de conception n'est pas entièrement compatible avec les outils commerciaux, qui ont été développés à l'origine pour des mises en place synchrones.Par conséquent, plusieurs méthodologies et techniques ont été introduites pour faciliter son adoption par l'industrie.Cependant, le flux de conception synchrone bien établi entrave les paradigmes de conception alternatifs et crée même une résistance à la poursuite du développement d'un flux de conception entièrement automatisé et optimisé pour les circuits asynchrones.Cela a également pour effet secondaire d'entraver les efforts visant à développer des techniques de test et de diagnostic pour ce type de circuits.Dans ce contexte, cette thèse porte sur les techniques dédiées au test et à l'analyse des circuits asynchrones.Une première partie présente une architecture de conception pour la testabilité (DFT) permettant des tests à la vitesse sur des circuits asynchrones bundled-data (BD), tout en maintenant un faible encombrement et une compatibilité avec les outils de DFT et de génération automatique de séquences de test (ATPG).L'architecture proposée a été mise en œuvre avec succès dans deux circuits de cas d'étude afin de montrer les détails techniques par des étapes de synthèse et d'ATPG, ainsi que de donner un aperçu des résultats tels que la couverture des défauts et l'utilisation de surface.La deuxième partie explore l'analyse des canaux caché sur les circuits asynchrones, en tirant parti de leur signature actuelle et de leur comportement intrinsèque.Cela a été appliqué à la détection des chevaux de Troie matériels (HT).Grâce à des expériences de simulation, il est démontré la capacité des circuits asynchrones à fournir des signatures de courant locales pour identifier la présence de minuscules HT.Les résultats montrent qu'une douzaine de transistors HT est détectable dans la conception de 13 000 transistors. De plus, une telle analyse ne nécessite pas de circuits ou de ports d'alimentation supplémentairesAsynchronous circuits have been explored in the last decades as an alternative to overcome the issues and limitations brought by synchronous design, especially as recent technology nodes reach physical limits and process, voltage and temperature (PVT) variations significantly impact circuit behavior.This pushes forward the use of asynchronous circuits on different applications requiring high-speed, low-power consumption, robustness or security.Due to their non-conventional design style, it is not so trivial to design them.Indeed, asynchronous design is marginally taught in engineering schools and its design flow is not fully compatible with commercial tools, which were originally developed for synchronous implementations.Therefore, several methodologies and techniques have been introduced to help its adoption by industry.However, the well-established synchronous design flow impedes alternative design paradigms and even creates resistance to further develop a fully automated and optimized design flow for asynchronous circuits.As a side effect, this also impacts the effort to develop testing and diagnosis techniques for this kind of circuits.In this context, this thesis targets dedicated techniques for testing and analyzing asynchronous circuits.A first part presents a Design-for-Testability (DFT) architecture enabling at-speed testing on asynchronous Bundled-data (BD) circuits, while maintaining low area overhead and compatibility with DfT and Automatic Test Pattern Generation (ATPG) tools.The proposed architecture has been successfully implemented in two study-case circuits in order to show the technical details through synthesis and ATPG steps, as well as overview the results such as fault coverage and area overhead.The second part explores side-channel analysis on asynchronous circuits, taking advantage of their current signature and intrinsic behavior.This has been applied to Hardware Trojan (HT) detection.Through simulation experiments, it is shown the ability of asynchronous circuits in providing local current signatures for identifying the presence of tiny HTs.The results demonstrate that a dozen-transistor HT is detectable in 13.000-transistor design. Moreover, such analysis does not require extra circuitry or extra power ports
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Forslund, Emil. "Code Generation in Java : A modular approach for better cohesion." Thesis, Högskolan i Skövde, Institutionen för informationsteknologi, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-11003.
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This project examines how the quality of a code generator used in an Object-Relational Mapping (ORM) framework can be improved in terms of maintainability, testability and reusability by changing the design from a top-down perspective to a bottom up. The resulting generator is tested in a case study to verify that the new design is more cohesive and less coupled than an existing code generator.
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Afonin, Andrej. "Abstrakčių automatų stebimumo nustatymo bei padidinimo tyrimas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050527_151100-63803.
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A circuit testing nowadays is expensive and complex process. That’s why circuits testing, errors finding and fixing require more and more investments. One of possible ways of reducing cost and speed up testing process is increasing controllability and observability of circuits. It takes a lot of time to find out circuit’s controllability and observability that’s why that process have to be computerized.
For that purpose was decided to create software which will be helpful for circuit designers in that process. As a result it will help designers in making design for testability schemes.
Research and training action for system on chip using internet software is dedicated for users that have C/C++ system on chip code from every place in the world, using only web browser, would be able put that code in to the server, test it and retrieve it‘s observability results in text and visual modes and also increase system’s on chip observability level. And as well review and get acquainted with systems on chip that are already on the server and are stored on it.
Software architecture uses client-server mode. All computations are performed on a server side. System is realized on Apache server with Linux OS. System modules are realized using HTML, JAVA, PHP, JavaScript, C++ and CGI programming languages.
Web page is working independent from users OS, user needs only web browser (Internet Explorer not older than 3.0 ver., Opera not older than 6.0 ver., Netscape Navigator not older... [to full text]
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Kuentzer, Felipe Augusto. "More than a timing resilient template : a case study on reliability-oriented improvements on blade." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2018. http://tede2.pucrs.br/tede2/handle/tede/8093.
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? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia natural de um circuito implementado com Blade, onde o monitoramento cont?nuo para detec??o de viola??es de atraso fornece a informa??o necess?ria para a detec??o concorrente de viola??es que extrapolam a capacidade de recupera??o do circuito resiliente. A integra??o de todas as contribui??es fornece uma cobertura de falha satisfat?ria para um custo de ?rea que, para os circuitos avaliados nesta Tese, pode variar de 4,24% a 6,87%, enquanto que a abordagem Scan para os mesmos circuitos apresenta custo que varia de 50,19% a 112,70% em ?rea, respectivamente. As contribui??es desta Tese demonstraram que, com algumas melhorias na arquitetura do Blade, ? poss?vel expandir sua confiabilidade para al?m de um sistema de toler?ncia a viola??es de atraso no caminho de dados, e tamb?m um avan?o para teste de falhas (inclusive falhas online) de todo o circuito, bem como melhorar seu rendimento, e lidar com quest?es de envelhecimento.
As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade?s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.
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Kincl, Zdeněk. "Metody pro testování analogových obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-233583.
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Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.
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Makris, Georgios. "Transparency-based hierarchical testability analysis and test generation for register transfer level designs /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2001. http://wwwlib.umi.com/cr/ucsd/fullcit?p9997571.
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Soomro, Rahman Abdul. "Testability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach." Case Western Reserve University School of Graduate Studies / OhioLINK, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=case1057589169.
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Shaheen, Muhammad Rabee. "Validation de métriques de testabilité logicielle pour les programmes objets." Phd thesis, Université Joseph Fourier (Grenoble), 2009. http://tel.archives-ouvertes.fr/tel-00978771.
Full textAbstract:
Pour les systèmes logiciels, la méthode de validation la plus utilisée est le test. Tester consiste en l'exécution du logiciel en sélectionnant des données et en observant/jugeant les sorties. C'est un processus souvent coûteux. Il dépend de la complexité du logiciel, des objectifs en termes de validation, des outils et du processus de développement. La testabilité logicielle s'intéresse à caractériser et prédire l'effort de test. Cela est nécessaire pour estimer le travail de test, prévoir les coûts, planifier et organiser le travail. De nombreuses mesures ont été proposées dans la littérature comme indicateurs du coût du test. Ces mesures sont focalisées sur l'évaluation de certains attributs qui peuvent rendre le test difficile. D'autres approches proposent de repérer des constructions difficiles à tester à l'aide de patrons (testability antipatterns) par exemple. D'une façon générale, peu d'études ont été réalisées pour valider ces métriques ou patrons. Certaines de ces études donnent des résultats contradictoires. Or il est essentiel de fournir des informations non biaisées. Notre travail de thèse porte en premier lieu sur la validation de certaines métriques de testabilité proposées pour la prédiction du coût du test de programmes objet. Notre approche s'appuie sur une mise en relation des métriques et des stratégies de test et vise à l'établissement de corrélation entre coût prédictive et coût effective. Ceci nous a conduit à raffiner certaines métriques étudiées. Dans un second temps, nous nous sommes intéressés à des patrons (testability antipatterns) visant à détecter des faiblesses dans le code vis à vis du test. Le but de cette étude est de comprendre à quels moments ces constructions sont introduites dans le code, afin de les repérer le plus efficacement possible.
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Tománek, Jakub. "Testovací rozhraní integrovaných obvodů s malým počtem vývodů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-320175.
Full textAbstract:
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
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CHEN, JIN-ZHUO, and 陳勁卓. "Testability design rule checker." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/14271064470504656602.
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Wu, Peng. "Test Generation Guided Design for Testability." 1988. http://hdl.handle.net/1721.1/6837.
Full textAbstract:
This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.
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Loureiro, Antonio Alfredo Ferreira. "Design for testability of communication protocols." Thesis, 1995. http://hdl.handle.net/2429/4776.
Full textAbstract:
There is growing consensus that some design principles are needed to overcome the ever increasing
complexity in verifying and testing software in order to build more reliable systems.
Design for testability (DFT) is the process of applying techniques and methods during the
design phase in order to reduce the effort and cost in testing its implementations. In this
thesis, the problem of design for testability of communication protocols is studied.
A framework that provides a general treatment to the problem of designing communication
protocols with testability in mind and some basic design principles are presented.
Following the protocol engineering life cycle we have identified and discussed in detail issues
related to design for testability in the analysis, design, implementation, and testing phases.
We discuss two important aspects that affect the testing of communication protocols:
testing taking the environment into consideration and distributed testing. We present a
novel algorithm and the corresponding design principles for tackling an important class
of faults caused by an unreliable environment, namely coordination loss, that are very
difficult to catch in the testing process. These design principles can be applied systematically
in the design of self-stabilizing protocols. We show that conformance relations that are
environment independent are not adequate to deal with errors caused by the environment
such as coordination loss. A more realistic conformance relation based on external behavior
as well as a "more testable" relation for environments which exhibit coordination loss are
introduced.
We also present a novel algorithm and the corresponding design principles for checking
dynamic unstable properties during the testing process. The method proposed can be used
in distributed testing of communication protocols and distributed programs in general. This
technique can also be used in normal execution of the protocol implementation to tackle the problems of state build-up and exception handling when a fault is detected. A specific
type of communication protocol, namely 3-way handshake protocols, is used to show it is
possible to check general properties using this algorithm.
A comprehensive survey of testability and design for testability in the software domain
is also included in the thesis.
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施振宇. "Application and Studying for Design-for-Testability." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/37286845135242630317.
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碩士中華大學
電機工程研究所
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In this thesis, it is to construct the flow of Design-for-Testability (DFT) based on full-scan and to help oneself to understand the DFT by learning this flow. Mary of design experiences are given to explain the effectiveness and efficiency of a design with full-scan to reach the high fault coverage.
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Zhao, Zhi De, and 趙智德. "GEMCAB：A Benchmark Circuit for Design for Testability." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/78486425361238058252.
Full textAbstract:
碩士中華大學
電機工程學系碩士班
87
The original intent of DFT(Design For Test) is to solve the problem in IC development. But it may produce another problem after we solve one. The problems of clock skew and bus contention always suffered from the design after DFT are proceeded. In this thesis we propound a GEMCAB benchmark circuit to behave the problems of a design before and after DFT and then give a possible way to solve them. Embedded memories are also augmented into the circuit. It is tried to discuss what to do with them in the DFT viewpoint.
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Chen, Bi Cheng, and 陳碧成. "Design-for-testability technology for multichip modules." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/79761734632044060448.
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