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Dissertations / Theses on the topic 'Design of analog electronic circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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1

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

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2

Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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3

Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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4

Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

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5

Cheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.

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6

Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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7

張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.

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8

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

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The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.
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9

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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10

Son, Kyung-Im. "A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son." Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5919.

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11

Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.

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The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.
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12

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.
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13

Ericson, Matthias, and Johan Silverudd. "Design of measurement circuits for SiC experiment : KTH student satellite MIST." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-191137.

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SiC in Space is one of the experiments on KTH’s miniature satellite, MIST. The experiment carries out tests on bipolar junction transistors of silicon and silicon carbide. This thesis describes how the characteristics of a transistor can be measured using analog circuits. The presented circuit design will work as a prototype for the SiC in Space experiment. The prototype measures the base current, the collector current, the base-emitter voltage as well as the temperature of the transistor. This thesis describes how a test circuit may be designed. The selected design has been constructed in incremental steps, with each design choice explained. Different designs have been developed. The designs have been verified with simulations. We have also constructed and tested three different prototypes on breadboards and printed circuit boards.
SiC in Space är ett av experimenten på KTHs miniatyrsatellit, MIST. Experimentet utför test på bipolära transistorer av kisel och kiselkarbid. Detta examensarbete förklarar hur transistorns karakteristik kan mätas med analoga kretsar. Den framtagna kretsdesignen kommer att fungera som en prototyp till SiC in Space-experimentet. Prototypen mäter basströmmen, kollektorströmmen, bas-emitter-spänningen samt temperaturen för transistorn. Detta examensarbete förklarar hur en testkrets kan designas. Den valda designen byggs i inkrementella steg, där varje designval förklaras. Olika designer har utvecklats. Designerna har verifierats genom simuleringar. Vi har också konstruerat och testat tre olika prototyper på kopplingsdäck och kretskort.
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14

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
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15

Michal, Vratislav. "Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.

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Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (Iq = 2mA) et une haute impédance d'entrée. Afin de fixer le gain avec précision dans la structure CMOS, deux méthodes différentes sont présentées et vérifiées sur un circuit intégré. Par la suite, le comportement des filtres dans la bande d'atténuation est étudié afin d'augmenter la fréquence de coupure maximale. Deux structures avec une faible influence des éléments actifs « réels » sont conçues: le filtre Sallen-Key amélioré et la structure basée sur un convoyeur du courant CCII-. Enfin, nous présentons un CCII- intégré en CMOS ayant une très faible impédance de sortie.
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16

Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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17

Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.

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18

Yengui, Firas. "Contribution aux méthodologies et outils d’aide à la conception de circuits analogiques." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0098/document.

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A la différence de la conception numérique, la conception analogique souffre d’un réel retard au niveau de la solution logicielle qui permet une conception à la fois rapide et fiable. Le dimensionnement de circuits analogiques exige en effet un nombre assez élevé de simulations et de vérifications et dépend beaucoup de l’expertise du concepteur. Pour pallier à ce retard, des outils de conception automatique basés sur des algorithmes d’optimisation locale et globale sont développés. Ces outils restent encore immatures car ils n’offrent que des réponses partielles aux questions du dimensionnement, alors que l’obtention d’un dimensionnement optimal d’un circuit analogique en un temps raisonnable reste toujours un enjeu majeur. La réduction du temps de conception de circuits analogiques intégrés nécessite la mise en place de méthodologies permettant une conception systématique et automatisable sur certaines étapes. Dans le cadre de cette thèse, nous avons travaillé suivant trois approches. Il s’agit d’abord de l’approche méthodologique. A ce niveau nous préconisons une approche hiérarchique descendante « top-down ». Cette dernière consiste à partitionner le système à dimensionner en sous blocs de fonctions élémentaires dont les spécifications sont directement héritées des spécifications du niveau système. Ensuite, nous avons cherché à réduire le temps de conception à travers l’exploration de solutions optimales à l’aide des algorithmes hybrides. Nous avons cherché à profiter de la rapidité de la recherche globale et de la précision de la recherche locale. L’intérêt des algorithmes de recherche hybride réside dans le fait qu’ils permettent d’effectuer une exploration efficace de l’espace de conception du circuit sans avoir besoin d’une connaissance préalable d’un dimensionnement initial. Ce qui peut être très intéressant pour un concepteur débutant. Enfin, nous avons travaillé sur l’accélération du temps des simulations en proposant l’utilisation des méta-modèles. Ceux-ci présentent un temps de simulation beaucoup plus réduit que celui des simulations des modèles électriques. Les méta-modèles sont obtenus automatiquement depuis une extraction des résultats des simulations électriques
Contrary to digital design, analog design suffers from a real delay in the software solution that enables fast and reliable design. In this PhD, three approaches are proposed. The first is the methodological approach. At this level we recommend a "top-down" hierarchical approach. It consists of partitioning the system to size into sub-blocks of elementary functions whose specifications are directly inherited from the system level specification. Next, we aimed to reduce design time through the exploration of optimal solutions using hybrid algorithms. We attempted to take advantage of the rapid global search and local search accuracy. The interest of hybrid search algorithms is that they allow to conduct effective exploration of the design space of the circuit without the need for prior knowledge of an initial design. This can be very useful for a beginner designer. Finally, we worked on the acceleration of time simulations proposing the use of meta-models which present a more reduced time than electrical simulation models. Meta-models are obtained automatically from extracting results of electrical simulations
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19

Remund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.

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20

Slezák, Josef. "Evoluční syntéza analogových elektronických obvodů s využitím algoritmů EDA." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-233666.

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Disertační práce je zaměřena na návrh analogových elektronických obvodů pomocí algoritmů s pravěpodobnostními modely (algoritmy EDA). Prezentované metody jsou na základě požadovaných charakteristik cílových obvodů schopny navrhnout jak parametry použitých komponent tak také jejich topologii zapojení. Tři různé metody využití EDA algoritmů jsou navrženy a otestovány na příkladech skutečných problémů z oblasti analogových elektronických obvodů. První metoda je určena pro návrh pasivních analogových obvodů a využívá algoritmus UMDA pro návrh jak topologie zapojení tak také hodnot parametrů použitých komponent. Metoda je použita pro návrh admitanční sítě s požadovanou vstupní impedancí pro účely chaotického oscilátoru. Druhá metoda je také určena pro návrh pasivních analogových obvodů a využívá hybridní přístup - UMDA pro návrh topologie a metodu lokální optimalizace pro návrh parametrů komponent. Třetí metoda umožňuje návrh analogových obvodů obsahujících také tranzistory. Metoda využívá hybridní přístup - EDA algoritmus pro syntézu topologie a metoda lokální optimalizace pro určení parametrů použitých komponent. Informace o topologii je v jednotlivých jedincích populace vyjádřena pomocí grafů a hypergrafů.
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21

Purohit, Siddharth. "Compact modeling of silicon carbide (SiC) vertical junction field effect transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SiC VJFET model." Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.

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22

Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.

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23

Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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24

Hu, Zongqi. "Analog integrated circuit design of hypertrellis decoders /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HU.

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25

Sapargaliyev, Yerbol. "Automatic design of analogue circuits." Thesis, Brunel University, 2011. http://bura.brunel.ac.uk/handle/2438/6323.

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Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits.
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26

Thomas, tomasevic Marc veljko. "Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles." Thesis, Toulouse, INSA, 2017. http://www.theses.fr/2017ISAT0002/document.

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Les circuits Smart Power, utilisés dans l’industrie automobile, se caractérisent par l’intégration sur une puce des parties de puissance avec des parties analogiques&numériques basse tension. Leur principal point faible vient de la commutation des structures de puissance sur des charges inductives. Celles-ci injectent des courants parasites dans le substrat, pouvant activer des structures bipolaires parasites inhérentes au layout du circuit, menant à une défaillance ou la destruction du circuit intégré.Ces structures parasites ne sont pas actuellement modélisées dans les outils CAO ni simulées par les simulateurs de type SPICE. L'extraction de ces structures à partir du layout et leur intégration dans les outils CAO est l’objectif du projet européen AUTOMICS, dans le cadre duquel cette thèse a été réalisée.La caractérisation du couplage substrat sur deux cas d’études a permis de valider les modèles théoriques et de les comparer aux simulations utilisant le nouveau modèle de couplage substrat
Smart Power circuits, used in the automotive industry, are characterized by the integration on one chip of the power parts with low voltage analog and digital parts. Their main weak point comes from the switching of power structures on inductive loads. These inject parasitic currents in the substrate, capable of activating the bipolar parasitic structures inherent in the layout of the circuit, leading to failure or destruction of the integrated circuit.These parasitic structures are not currently integrated into CAD tools nor simulated by SPICE simulators. The extraction of these structures from the layout and their integration into the CAD tools is the objective of the European AUTOMICS project, in which this thesis is carried out.The characterization of the substrate coupling of 2 case study was used to validate theoretical models and compare them to simulations using the new substrate coupling model
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Sabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.

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Knight, Clinton D. "WWW-based testing of analog circuits." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14863.

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Huang, Shu-Chuan. "Systematic design solutions for analog VLSI circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487850665560538.

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Najafizadeh, Laleh. "Design of analog circuits for extreme environment applications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31796.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Shen, Shyh-Chiang; Committee Member: Steffes, Paul; Committee Member: Zhou, Hao Min. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Mason, J. S. B. "Analog Design within High Speed Serial Interface Circuits." Thesis, Oxford Brookes University, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.493433.

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The serial interface is a pervasive component within many electronic products and will be familiar to users of personal computers and modern electronic devices. Over the last twenty years, the serial interface or link has developed from a specialist electronic subsystem for computer and telecommunication systems to an essential building block for modern electronic products ranging from disk storage devices to home entertainment consoles. The high speed serial interface (HSS!) offers fast data transfer at relatively low cost and is now an semiconductor vendors supplying chips to original equipment manufacturers.
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Das, Angan. "Algorithms for Topology Synthesis of Analog Circuits." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1227204301.

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Yoon, Heebyung. "Fault detection and identification techniques for embedded analog circuits." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13041.

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34

El-Gamal, Mohamed A. "Fault location and parameter identification in analog circuits." Ohio : Ohio University, 1990. http://www.ohiolink.edu/etd/view.cgi?ohiou1172776742.

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35

Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.

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Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC.
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Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).
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Yoo, Seoung Jae. "Design of analog baseband circuits for wireless communication receivers." The Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=osu1073617255.

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Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.

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To, Hing-yan. "Statistical Analysis and Design Techniques for Analog VLSI Circuits /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487928649989917.

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40

Dai, Hong. "Development of a decomposition approach for testing large analog circuits." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1172006982.

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41

Hu, Yichuan. "Analog non-linear coding for improved performance in compressed sensing." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 76 p, 2009. http://proquest.umi.com/pqdweb?did=1885755731&sid=5&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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42

Nalbantis, Dimitris. "World Wide Web based layout synthesis for analogue modules." Thesis, University of Kent, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365218.

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43

Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Hägglund, Robert. "An optimization-based approach to efficient design of analog circuits /." Linköping : Department of Electrical Engineering, Linköping University, 2006. http://www.bibl.liu.se/liupubl/disp/disp2006/tek1026s.pdf.

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Hjalmarson, Emil. "A computer-aided approach to design of robust analog circuits /." Linköping : Department of Electrical Engineering, Linköping University, 2006. http://www.bibl.liu.se/liupubl/disp/disp2006/tek1025s.pdf.

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46

Tang, Hongxia. "Study of Design for Reliability of RF and Analog Circuits." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5525.

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Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 μm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.
ID: 031001466; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Jiann S. Yuan.; Title from PDF title page (viewed July 10, 2013).; Thesis (Ph.D.)--University of Central Florida, 2012.; Includes bibliographical references (p. 101-111).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Peng, Sheng-Yu. "Charge-based analog circuits for reconfigurable smart sensory systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29655.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Gordon, Christal. "Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37222.

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This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons. An intracellular signal from a living neuron was amplified, an integrate-and-fire neuron was used as a simple processing element to detect the spikes, and an artificial synapse was used to send outputs to another living neuron. The key structure is an electronic synapse which is based around a floating-gate pFET. The charge on the floating-gate is analogous to the synaptic weight and can be modified. This modification can be viewed as similar to long-term potentiation and long-term depression. The modification can either be programmed (supervised learning) or can adapt to the inputs (unsupervised learning). Since the technology to change the floating-gate weight has greatly improved, these weights can be set quickly and accurately. Intrinsic floating-gate learning rules were explored and the ability to change the synaptic weight was shown.
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Hou, Junwei. "Concurrent fault simulation for mixed-signal circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15735.

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Rudolf, Robert. "Design methods to mitigate the effects of variation in analogue and mixed-signal circuits." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/374300/.

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The continued scaling of CMOS process features enables ever-faster and denser circuits, which comes at the cost of increased device parameter variation. The performance of analogue and mixed-signal circuits in particular degrades in such a high variation environment, which poses an extraordinary challenge in the design and fabrication of such circuits. This thesis develops a set of tools and methodologies for a post-fabrication calibration system called the Configurable Analogue Transistor (CAT). The principle of the CAT technique is to replace certain transistors in a circuit with calibration devices, which allow adjustment of circuit performance after fabrication to compensate the effects of device parameter variation. Building on initial research on the CAT, this thesis develops a methodology to identify the most suitable calibration devices in their circuit and determine their optimal sizes. Furthermore, the applicability of CAT is extended beyond parameter variation to also include direct compensation of temperature. A complementary technique to post-fabrication calibration is robust design, where a circuit is designed to be inherently robust against variation in device parameters. In this thesis, a novel closed-loop pick-off circuit for force-balanced MEMS accelerometers is presented. It is comparable in performance to other state-of-the-art techniques, but provides vastly improved robustness against parameter variation and a more intuitive design process.
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