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Journal articles on the topic 'Design of analog electronic circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 February 2022

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1

WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

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2

Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.

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3

Dieste-Velasco, M. Isabel. "Application of a Fuzzy Inference System for Optimization of an Amplifier Design." Mathematics 9, no. 17 (September 5, 2021): 2168. http://dx.doi.org/10.3390/math9172168.

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Simulation programs are widely used in the design of analog electronic circuits to analyze their behavior and to predict the response of a circuit to variations in the circuit components. A fuzzy inference system (FIS) in combination with these simulation tools can be applied to identify both the main and interaction effects of circuit parameters on the response variables, which can help to optimize them. This paper describes an application of fuzzy inference systems to modeling the behavior of analog electronic circuits for further optimization. First, a Monte Carlo analysis, generated from the tolerances of the circuit components, is performed. Once the Monte Carlo results are obtained for each of the response variables, the fuzzy inference systems are generated and then optimized using a particle swarm optimization (PSO) algorithm. These fuzzy inference systems are used to determine the influence of the circuit components on the response variables and to select them to optimize the amplifier design. The methodology proposed in this study can be used as the basis for optimizing the design of similar analog electronic circuits.

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4

WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (June 1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal analog circuit description language. The language syntax and semantics provide precise symbolic description of analog circuits functionality at different levels of hierarchy and connectivities together with transistor sizes of CMOS circuits at the transistor level. Different levels of hierarchy with circuit structures and performance parameters are presented in detail. It is shown how sentence conversion rules of language grammar can be used to derive transistor level circuits from input performance specifications through all intermediate levels of hierarchy. The implementation of the methodology and associated experimental results for CMOS operational amplifier designs are presented.

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Lima, Evelyn Cristina de Oliveira, André Borges Cavalcante, and João Viana Da Fonseca Neto. "Optimization of amplifier circuits by using gradient boosted trees and probability annealing policy." Journal of Integrated Circuits and Systems 15, no. 3 (December 3, 2020): 1–5. http://dx.doi.org/10.29292/jics.v15i3.184.

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One important step of the optimization of analog circuits is to properly size circuit components. Since the quantities that define specification may compete for different circuit parameter values, the optimization of analog circuits befits a hard and costly optimization problem. In this work, we propose two contributions to design automation methodologies based on machine learning. Firstly, we propose a probability annealing policy to boost early data collection and restrict electronic simulations later on in the optimization. Secondly, we employ multiple gradient boosted trees to predict design superiority, which reduces overfitting to learned designs. When compared to the state-of-the art, our approach reduces the number of electronic simulations, the number of queries made to the machine learning module required to finish the optimization.

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6

Jenn-Chyou Bor and Chung-Yu Wu. "Analog electronic cochlea design using multiplexing switched-capacitor circuits." IEEE Transactions on Neural Networks 7, no. 1 (1996): 155–66. http://dx.doi.org/10.1109/72.478400.

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7

Castejón, Federico, and Enrique J. Carmona. "Automatic design of analog electronic circuits using grammatical evolution." Applied Soft Computing 62 (January 2018): 1003–18. http://dx.doi.org/10.1016/j.asoc.2017.09.036.

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8

Felgueiras, Manuel Carlos, Jose Macedo, Andre Fidalgo, C. Petry, and Gustavo Alves. "How to Use Remote Labs for Enhancing E-Learning on PSoCs." International Journal of Online Engineering (iJOE) 12, no. 04 (April 28, 2016): 61. http://dx.doi.org/10.3991/ijoe.v12i04.5232.

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Electronic teaching is a task that intents to also prepare the student to understand and design analog and digital circuits. However the design flow in those two arenas are quite opposite as result of very different development state and also are the design methodologies, being challenging for both teachers and students. In fact, the electronic design in the digital field is centered in the use of components based in two kind of circuits (microprocessor and FPGA) using a relatively high level programing/configuring languages. In an opposite way, the analog design is traditionally founded in the use of elementary components (e.g. resistors and capacitors) associated with macroblocks (e.g. operational amplifiers) in order to built-up the wanted mission circuit. However they have just a few analog programmable components, as the PSoC that is analogically configurable in a similar manner that the one already used in the digital domain. The use of this kind of components, however, is not straightforward being necessary to get some concepts traditionally not taught in the analog electronic classes. The training using PSoC are then indispensable to verify if the programed analog circuit corresponds to the intended one. The current work present an innovative remote lab to support teaching of the PSoC.

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9

FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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10

Mhiri, Nesrine, Abdulrahman Alahdal, Hamza Ghulman, and Anis Ammous. "A Novel Analog Circuit Design for Maximum Power Point Tracking of Photovoltaic Panels." Advances in Power Electronics 2017 (September 25, 2017): 1–9. http://dx.doi.org/10.1155/2017/9409801.

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A new analog technique is proposed in order to track the maximum power point (MPP) of PV panels. The proposed technique uses the well-known simple functions of electronic circuits. The proposed technique is validated by applying it to boost based off grid PV system. The simulation of the PV system was done on the circuit oriented simulator Proteus-ISIS. A good efficiency of the analog technique (more than 98%) was registered. The variation of irradiation was introduced in order to study the robustness of the proposed analog MPPT technique.

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ISLAM, SYED S., and A. F. M. ANWAR. "SPICE MODEL OF AlGaN/GaN HEMTs AND SIMULATION OF VCO AND POWER AMPLIFIER." International Journal of High Speed Electronics and Systems 14, no. 03 (September 2004): 853–59. http://dx.doi.org/10.1142/s0129156404002946.

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SPICE model parameters are extracted from reported experimental data. The model is implemented in the Cadence Affirma Analog Circuit Design Environment and Spectre simulator is used to simulate class-E power amplifier and ring voltage controlled oscillator (VCO) circuits. The availability of the SPICE model for GaN HEMTs ensures optimization of analog/RF circuits before an expensive cut-and-try method is employed.

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12

Fujii, Nobuo. "Problems in computer-aided simulation and design of analog integrated circuits–stability of analog integrated circuits." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 74, no. 4 (1991): 22–30. http://dx.doi.org/10.1002/ecjc.4430740403.

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13

Schmidt, Alexander, Holger Kappert, and Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 171–82. http://dx.doi.org/10.4071/imaps.389.

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Analog circuits realized in a PD-SOI (partially-depleted silicon-on-insulator) CMOS technology for a wide temperature range up to 400°C are significantly affected by the transistor characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, for example, intrinsic gain and bandwidth, tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that RBB (reverse body biasing) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300°C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS technology by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400°C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, current mirrors, a two-stage operational amplifier, and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby, the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. As the method has also been applied to essential analog circuits, it has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400°C.

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14

Li, Bo, and Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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15

Skattebol, L. "Book Review: Analog Electronic Circuit Design." International Journal of Electrical Engineering & Education 30, no. 3 (July 1993): 275–76. http://dx.doi.org/10.1177/002072099303000312.

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16

Strangio, S., F. Settino, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni, and L. Selmi. "Digital and analog TFET circuits: Design and benchmark." Solid-State Electronics 146 (August 2018): 50–65. http://dx.doi.org/10.1016/j.sse.2018.05.003.

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17

Felgueiras, Manuel Carlos, Dinis Areias, Andre Fidalgo, Clovis Petry, and Gustavo Alves. "Using Remote Lab for Enhancing E-Learning on FPAAs." International Journal of Online Engineering (iJOE) 12, no. 04 (April 28, 2016): 58. http://dx.doi.org/10.3991/ijoe.v12i04.5230.

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Analog and digital electronic subjects are part of the electronic engineer degree but its taught is not easy because they are founded in opposite methodologies. The electronic design in the digital field is centered in the use of microprocessor and FPGA based circuits using high level programing/configuring languages. The counterpart analog design is traditionally based in the use of elementary components associated with macroblocks such operational amplifiers in order to built-up the wanted mission circuit. Some few components, as the FPAA, are analogically configurable in a similar manner already used with the FPGA. However the use of this kind of components is not straightforward once is necessary acquire some concepts not taught in the traditionally analog electronic classes. The current work present an innovative remote lab to support teaching of the FPAAs.

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18

Slezak, J., and T. Gotthans. "Design of Passive Analog Electronic Circuits Using Hybrid Modified UMDA algorithm." Radioengineering 24, no. 1 (April 15, 2015): 161–70. http://dx.doi.org/10.13164/re.2015.0161.

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19

Huang, Tsung-Ching, Ting Lei, Leilai Shao, Sridhar Sivapurapu, Madhavan Swaminathan, Zhenan Bao, Kwang-Ting Cheng, and Raymond Beausoleil. "Process Design Kit and Design Automation for Flexible Hybrid Electronics." Journal of Microelectronics and Electronic Packaging 16, no. 3 (July 1, 2019): 117–23. http://dx.doi.org/10.4071/imaps.925849.

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Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (<50 μm) silicon chips on soft, thin, and flexible substrates for a wide range of applications, from flexible displays to wearable medical devices. Here, we report (1) a process design kit (PDK) to enable FHE design automation for large-scale FHE circuits and (2) solution process-proven intellectual property blocks for TFT circuits design, including Pseudo-Complementary Metal-Oxide-Semiconductor (Pseudo-CMOS) flexible digital logic and analog amplifiers. The FHE-PDK is fully compatible with popular silicon design tools for design and simulation of hybrid-integrated flexible circuits.

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20

FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, MICHAEL J. DEGERSTROM, MICHAEL J. LORSUNG, JASON F. PRAIRIE, ERIC L. H. AMUNDSEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

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21

ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (September 1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

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Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

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22

RAZAVI, BEHZAD. "LOW-POWER, LOW-VOLTAGE DESIGN—AN OVERVIEW." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 145–57. http://dx.doi.org/10.1142/s0129156494000085.

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This paper gives an overview of design issues in low-power, low-voltage circuits. First, device and supply scaling is studied and its impact on both digital and analog circuits is described. Next, general low-power and low-voltage design strategies are presented. Finally, two examples of high-speed, low-power circuits are discussed.

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23

Gülden, Mehmet Ali, Ertan Zencir, and Enver Çavuş. "A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture." Journal of Circuits, Systems and Computers 29, no. 10 (January 6, 2020): 2050169. http://dx.doi.org/10.1142/s0218126620501698.

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In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

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24

Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.

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25

Brander, Chris. "Book Review: Design and Applications of Analog Integrated Circuits." International Journal of Electrical Engineering & Education 29, no. 3 (July 1992): 277–78. http://dx.doi.org/10.1177/002072099202900317.

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26

Mattiussi, Claudio, Daniel Marbach, Peter Dürr, and Dario Floreano. "The Age of Analog Networks." AI Magazine 29, no. 3 (September 6, 2008): 63. http://dx.doi.org/10.1609/aimag.v29i3.2156.

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A large class of systems of biological and technological relevance can be described as analog networks, that is, collections of dynamical devices interconnected by links of varying strength. Some examples of analog networks are genetic regulatory networks, metabolic networks, neural networks, analog electronic circuits, and control systems. Analog networks are typically complex systems which include nonlinear feedback loops and possess temporal dynamics at different time scales. Both the synthesis and reverse engineering of analog networks are recognized as knowledge-intensive activities, for which few systematic techniques exist. In this paper we will discuss the general relevance of the analog network concept and describe an evolutionary approach to the automatic synthesis and the reverse engineering of analog networks. The proposed approach is called analog genetic encoding (AGE) and realizes an implicit genetic encoding of analog networks. AGE permits the evolution of human-competitive solutions to real-world analog network design and identification problems. This is illustrated by some examples of application to the design of electronic circuits, control systems, learning neural architectures, and the reverse engineering of biological networks.

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27

Sarpeshkar, R. "Analog synthetic biology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130110. http://dx.doi.org/10.1098/rsta.2013.0110.

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We analyse the pros and cons of analog versus digital computation in living cells. Our analysis is based on fundamental laws of noise in gene and protein expression, which set limits on the energy, time, space, molecular count and part-count resources needed to compute at a given level of precision. We conclude that analog computation is significantly more efficient in its use of resources than deterministic digital computation even at relatively high levels of precision in the cell. Based on this analysis, we conclude that synthetic biology must use analog, collective analog, probabilistic and hybrid analog–digital computational approaches; otherwise, even relatively simple synthetic computations in cells such as addition will exceed energy and molecular-count budgets. We present schematics for efficiently representing analog DNA–protein computation in cells. Analog electronic flow in subthreshold transistors and analog molecular flux in chemical reactions obey Boltzmann exponential laws of thermodynamics and are described by astoundingly similar logarithmic electrochemical potentials. Therefore, cytomorphic circuits can help to map circuit designs between electronic and biochemical domains. We review recent work that uses positive-feedback linearization circuits to architect wide-dynamic-range logarithmic analog computation in Escherichia coli using three transcription factors, nearly two orders of magnitude more efficient in parts than prior digital implementations.

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Balabanov, A. A., A. L. Pereverzev, and D. V. Strekopytov. "Systematization of Approaches to the Analysis and Design of Analog Electronic Circuits." Proceedings of Universities. Electronics 23, no. 4 (August 2018): 410–19. http://dx.doi.org/10.24151/1561-5405-2018-23-4-410-419.

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Chattopadhyay, Saranyu, Pranesh Santikellur, Rajat Subhra Chakraborty, Jimson Mathew, and Marco Ottavi. "A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (November 30, 2021): 1–24. http://dx.doi.org/10.1145/3460004.

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Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

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HOLMAN, W. T. "RADIATION-TOLERANT DESIGN FOR HIGH PERFORMANCE MIXED-SIGNAL CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 353–66. http://dx.doi.org/10.1142/s0129156404002405.

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Modern semiconductor processes can provide significant intrinsic hardness against radiation effects in digital and analog circuits. Current design techniques using commercial processes for radiation-tolerant integrated circuits are summarized, with an emphasis on their application in high performance mixed-signal circuits and systems. Examples of "radiation hardened by design" (RHBD) methodologies are illustrated for reducing the vulnerability of circuits and components to total dose, single-event, and dose-rate effects.

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31

Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

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Et al., Andy Wahyu H. "Developing Learning Media Based Project Board in Electronic Materials to Improve the Analysis Capability and Skills for the Cadets of PIP Semarang." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 6 (April 5, 2021): 2686–94. http://dx.doi.org/10.17762/turcomat.v12i6.5769.

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Electronics is one of the most widely used materials on board, but in reality, the cadets still have difficulty in understanding the concepts, solving problems and making electronic circuits. The media used today have a significant risk, such as a short circuit or electric shock. There are several problems that the authors get in this study, they are; how is the learning media for electronic practice used today, how to design an appropriate media for learning electronics practice with project board. In this study, the method used Research and Development (R&D). It is a research method used to produce certain products, and test the effectiveness of these products. In producing certain products, the researchers used needs analysis. The final results of this study will produce the electronic learning media. From the results of the learning model design and testing of the Analog Experimenter ASH tool, there are a number of things that can be concluded: The electronic learning media used today is still not effective and efficient because the cadets have to buy the practical materials, while in terms of safety, it is very lacking. The design of instructional media made is more effective, efficient and safer than the methods currently used. This is proven by testing the ASH Analog Experimenter with a multimeter and Oscilloscope.

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33

Lopez-Martin, Antonio J., and Alfonso Carlosena. "Design of MOS-translinear Multiplier/Dividers in Analog VLSI." VLSI Design 11, no. 4 (January 1, 2000): 321–29. http://dx.doi.org/10.1155/2000/21852.

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A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS process, are provided in order to verify the correctness of the proposed approach.

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34

Kinget, P. R. "Device mismatch and tradeoffs in the design of analog circuits." IEEE Journal of Solid-State Circuits 40, no. 6 (June 2005): 1212–24. http://dx.doi.org/10.1109/jssc.2005.848021.

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Razavi, Behzad. "The Design Of Broadband I/O Circuits [The Analog Mind]." IEEE Solid-State Circuits Magazine 13, no. 2 (2021): 6–15. http://dx.doi.org/10.1109/mssc.2021.3072299.

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BŰRMEN, ÁRPÁD, TADEJ TUMA, and IZTOK FAJFAR. "A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION." Journal of Circuits, Systems and Computers 17, no. 01 (February 2008): 123–40. http://dx.doi.org/10.1142/s0218126608004125.

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The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed.

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Gelao, G., R. Marani, and A. G. Perri. "Effects of Temperature in CNTFET-Based Design of Analog Circuits." ECS Journal of Solid State Science and Technology 7, no. 2 (2018): M16—M21. http://dx.doi.org/10.1149/2.0031803jss.

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38

Wei, Zhaopeng, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, and Benjamin Blampey. "Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits." Active and Passive Electronic Components 2019 (July 4, 2019): 1–9. http://dx.doi.org/10.1155/2019/4578501.

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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Yilmaz, Ender, and GÜnhan Dundar. "Analog Layout Generator for CMOS Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 1 (January 2009): 32–45. http://dx.doi.org/10.1109/tcad.2008.2009137.

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Hashemian, Reza. "Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs." VLSI Design 2010 (March 9, 2010): 1–12. http://dx.doi.org/10.1155/2010/297083.

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A new technique is presented for biasing of analog circuits. The biasing design begins with local biasing of the nonlinear components (transistors), done according to the pre-specified operating points (OPs) and for the best performance of the circuit. Next, the transistors are replaced with their linear models to perform the AC design. Upon finishing with the AC design we need to move from the local biasing to global (normal) biasing while the OPs are kept unchanged. Here fixators—nullators plus sources—are shown to be very instrumental and with norators—as the place holders for the DC supplies in the circuit—they make pairs. The solution of the circuit so prepared provides the DC supplies at the designated locations in the circuit. The rules to engage in circuit analysis with fixator-norator pairs are discussed, and numerous pitfalls in this line are specified. Finally, two design examples are worked out that clearly demonstrate the capability and power of the proposed technique for biasing any analog circuit.

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Grasso, Francesco, Stefano Manetti, and Maria Cristina Piccirilli. "A symbolic approach to design centering of analog circuits." Microelectronics Reliability 47, no. 8 (August 2007): 1288–95. http://dx.doi.org/10.1016/j.microrel.2006.09.022.

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Temich, Sebastian, Tomasz Golonek, and Damian Grzechca. "Design an Identification Function to Reduce the Computational Resources on the Testing Process of an Analog Electronic Circuit." Elektronika ir Elektrotechnika 25, no. 3 (June 25, 2019): 25–33. http://dx.doi.org/10.5755/j01.eie.25.3.23672.

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In modern electronic circuits, imperfectness in the technological process can cause errors in reaching the correct values of the functional parameters. In order to solve this problem, a novel approach of analog and mixed-signal circuit testing methodology is used. The presented approach allows the testing complexity to be reduced and the testing time to be decreased. For this paper, selected signal features were designated from the transient output signal response. Using regression models with the extracted signal features, the functional parameters of a circuit were determined. An evolutionary determination of the regression models enabled the efficiency of the identification process to be maximized. The proposed methodology is presented for an exemplary CMOS Dickson charge pump circuit.

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UNNO, N., and N. FUJII. "Automated Design of Analog Circuits Starting with Idealized Elements." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 11 (November 1, 2006): 3313–19. http://dx.doi.org/10.1093/ietfec/e89-a.11.3313.

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Wang, Jing Li. "Optimal Design of Electronic Circuit." Applied Mechanics and Materials 58-60 (June 2011): 2581–84. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.2581.

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Circuit optimization method should include the topology of automatic design circuit and automatically determine components parameters of the circuit. At present, CAD or EDA optimization tools is produced by combined optimization algorithm and the basic analysis above together with the tolerance analysis. In this paper, optimization design which can modular basic analog circuit by using Optimizer, which makes the circuit topology structure and component parameters tend to be more reasonable, provides the basis for teaching practice and scientific research. It has practical significance.

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Zemliak, Alexander, Fernando Reyes, and Olga Felix. "On a Quasi Optimal Algorithm for Analog Circuits Optimization." WSEAS TRANSACTIONS ON ELECTRONICS 12 (August 2, 2021): 61–72. http://dx.doi.org/10.37394/232017.2021.12.9.

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An analog circuit design methodology based on applications of control theory is the basis for constructing an optimal or quasi-optimal design algorithm. The main criterion for identifying the required structure of the algorithm is the behavior of the Lyapunov function, which was decisive for the circuit optimization process. The characteristics of the Lyapunov function and its derivative are the basis for finding the optimal structure of the control vector that determines the structure of the algorithm. A block diagram of a quasi-optimal algorithm that implements the main ideas of the methodology is constructed, and the main characteristics of this algorithm are presented in comparison with the traditional approach

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46

Manganaro, G. "Analog circuit design [Book Review]." IEEE Circuits and Devices Magazine 17, no. 4 (July 2001): 34. http://dx.doi.org/10.1109/mcd.2001.950058.

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Dam, Samiran, and Pradip Mandal. "Modeling and design of CMOS analog circuits through hierarchical abstraction." Integration 46, no. 4 (September 2013): 449–62. http://dx.doi.org/10.1016/j.vlsi.2013.02.001.

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Seo, Dongwon, Hayg Dabag, Yuhua Guo, Manu Mishra, and Gene H. McAllister. "High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 10 (October 2007): 2159–66. http://dx.doi.org/10.1109/tcsi.2007.904600.

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Vittoz, E. A. "The Design of High-Performance Analog Circuits on Digital CMOS Chips." IEEE Journal of Solid-State Circuits 20, no. 3 (June 1985): 657–65. http://dx.doi.org/10.1109/jssc.1985.1052365.

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HAIDER, MOHAMMAD RAFIQUL, JEREMY HOLLEMAN, SALWA MOSTAFA, and SYED KAMRUL ISLAM. "LOW-POWER BIOMEDICAL SIGNAL MONITORING SYSTEM FOR IMPLANTABLE SENSOR APPLICATIONS." International Journal of High Speed Electronics and Systems 20, no. 01 (March 2011): 115–28. http://dx.doi.org/10.1142/s0129156411006453.

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Implantable biomedical sensors and continuous real time in vivo monitoring of various physiological parameters requires low-power sensor electronics and wireless telemetry for transmission of sensor data. In this article, generic blocks required for such systems have been demonstrated with design examples. Ideally neural or electro-chemical sensor signal monitoring units comprise of low noise amplifiers, current or voltage mode analog to digital domain data conversion circuits and wireless telemetry circuits. The low-noise amplifier described here has a novel open loop amplifier scheme used for neural signal recording systems. The design has been implemented using 0.5-μm SOI-BiCMOS process. The fabricated chip can work with 1 V supply and consumes 805 nA. The current mode analog to digital conversion signal processing circuitry takes the current signal as an input and generates a pulse-width modulated data signal. The data signal is then modulated with a high frequency carrier signal to generate FSK data for wireless transmission. The design is fabricated in 0.5-μm standard CMOS process and consumes 1.1 mW of power with 3.5 V supply.

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