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Dissertations / Theses on the topic 'Design of CMOS integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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1

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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2

Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.

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Thesis (Ph. D.)--Ohio State University, 2004.<br>Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).

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3

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

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4

Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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5

Larson, Bruce C. (Bruce Carl). "Design considerations for minimizing noise in micropower CMOS integrated circuits." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/40228.

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6

Massingham, John William. "A design technique for mixed ECL and CMOS circuitry." Thesis, University of Aberdeen, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241357.

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In this thesis, the principles of mixing ECL and CMOS technologies have been investigated with the intention of increasing the operating speed of synchronous systems. To achieve this, the design will be primarily CMOS based with the critical path implemented in ECL to reduce the delay and hence improve the execution time. Logic conversion circuitry between the two technologies has been designed, with the CMOS-ECL conversion circuit being a simple enhancement of the basic ECL current switch and ECL-CMOS translation being achieved with 0.5ns using a "double inverter circuit". To reduce the power

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7

Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

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8

Zhu, Yongdong. "Parasitic-aware design and layout for RF CMOS analogue integrated circuits." Thesis, University of Essex, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442535.

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9

Leite, Bernardo. "Design and modeling of mm-wave integrated transformers in CMOS and BiCMOS technologies." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2011. http://tel.archives-ouvertes.fr/tel-00667744.

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Les systèmes de communication sans fil en fréquences millimétriques ont gagné considérablement en importance au cours des dernières années. Des applications comme les réseaux WLAN et WPAN à 60 GHz, le radar automobile autour de 80 GHz ou l'imagerie à 94 GHz sont apparues, demandant un effort conséquent pour la conception des circuits intégrés émetteurs et récepteurs sur silicium. Dans ce contexte, les transformateurs intégrés sont particulièrement intéressants. Ils peuvent réaliser des fonctions comme l'adaptation d'impédance, la conversion du mode asymétrique au différentiel et la combinaison

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10

Ross, Kyle Gene. "Distributed amplifier circuit design using a commercial CMOS process technology." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/ross/RossK0806.pdf.

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11

Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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12

Sayles, Andre Harding. "Design of integrated CMOS circuits for parallel detection and storage of optical data." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/13740.

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13

Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.

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14

Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuito

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15

Biswas, Shampa. "Integrated CMOS Doppler Radar : System Specification & Oscillator Design." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129222.

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This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. With this selected CMOS process, the frequency band at 2.45 GHz or 5 GHz, with a maximum output power level of 25 mW (e.i.r.p), is found to be appropriate for the whole system to obtain a good performance. In this thesis work, a Ring VCO with pseudo-differential architecture has been designed and o

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16

Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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17

Murty, Anjali. "Highly linear, rail-to-rail ICMR, low voltage CMOS operational amplifer." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/14884.

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18

Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.

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19

Jin, Yalin. "Radio-frequency integrated-circuit design for CMOS single-chip UWB systems." Thesis, [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2724.

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20

Gallo, John T. "Design of a holographic read-only-memory for parallel data transfer to integrated CMOS circuits." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15640.

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21

Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characterist

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22

Noe, Sidney Scott. "Alternative gate designs for improved radiation hardness in bulk CMOS integrated circuits." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA331678.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1997.<br>"March 1997." Thesis advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 233-235). Also available online.

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23

Yang, Hong. "Circuit Design and Reliability of a CMOS Receiver." Doctoral diss., University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2102.

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This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved cir

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24

Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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25

Ko, Yus. "Design and optimization of 5GHz CMOS power amplifiers with the differential load-pull techniques." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013036.

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26

Madan, Anuj. "Design and reliability of high dynamic range RF building blocks in SOI CMOS and SiGe BiCMOS technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45853.

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The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layou

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27

Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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28

Kindel, Marcus. "Síntese Automática de Células CMOS." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1997. http://hdl.handle.net/10183/18278.

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Este trabalho apresenta o desenvolvimento de uma nova ferramenta para a síntese automática de células, a partir de uma descrição estrutural no nível lógico. A ferramenta esta sendo integrada ao sistema TRAMO3, e visa eliminar a necessidade do use de biblioteca de células na geração de circuitos. Uma revisão sobre síntese de leiaute e metodologias de projeto é apresentada. A metodologia TRANCA é descrita de forma sucinta e os sistemas TRAMO2 e TRAMO3, assim como o roteador MARTE são analisados em detalhe para indicar o contexto onde se insere o trabalho. As principais alternativas para a geraçã

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29

Park, Jinho. "Design of an RF CMOS ultra-wideband amplifier using parasitic-aware synthesis and optimization /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/6086.

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30

Dang, Jin [Verfasser]. "Design and Characterization of K-Band Receiver Front-End Integrated Circuits in 130 nm CMOS / Jin Dang." Aachen : Shaker, 2015. http://d-nb.info/1080762132/34.

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31

Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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32

Larsen, Frode. "Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487857546387163.

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33

Brotman, Susan Rose. "The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4701.

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It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information'

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34

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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35

Pimentel, Henrique Luiz Andrade. "Projeto de um amplificador de baixo ruído em tecnologia CMOS 130nm para frequências de 50MHZ a 1GHz." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67180.

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O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássi

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36

Loikkanen, M. (Mikko). "Design and compensation of high performance class AB amplifiers." Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514261770.

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Abstract Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated

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37

Michal, Vratislav. "Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.

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Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (I

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38

Junqueira, Alexandre Ambrozi. "Risco : microprocessador RISC CMOS de 32 bits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/21530.

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Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um

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39

Kešner, Filip. "Design of Digital Circuits at Transistor Level." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236048.

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This work aims to design process of integrated circuits on the transistor level, specially using evolutionary algorithm. For this purpose it is necessary to choose reasonable level of abstraction during simulation, which is used for evaluation candidate solutions by fitness function. This simulation has to be fast enough to evaluate thousands of candidate solutions within seconds. This work discusses already used techniques for transistor level circuit design and it chooses useful parts for new design of faster and more reliable automated design process, which would be able to design complex l

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40

Bespalko, Ryan Douglas. "Transimpedance amplifier design using 0.18 um CMOS technology." Thesis, Kingston, Ont. : [s.n.], 2007. http://hdl.handle.net/1974/452.

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41

Sen, Padmanava. "Estimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26585.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Dr. Joy Laskar; Committee Member: Dr. Chang- Ho Lee; Committee Member: Dr. Federico Bonetto; Committee Member: Dr. John D. Cressler; Committee Member: Dr. John Papapolymerou; Committee Member: Dr. Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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42

Butz, Natalie [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Design and implementation of cause-based and consequence-based control circuits for active charge balancing in CMOS integrated neural stimulator." Freiburg : Universität, 2021. http://d-nb.info/1240610238/34.

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43

詹國裕. "Design of 2.4GHz Mixer RF CMOS Integrated Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23043642088838562176.

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碩士<br>明新科技大學<br>電子工程研究所<br>93<br>At the present time , due to the wireless communication industry is rapidly developments. The high integration, low voltage, and low power radio frequency integration circuit (RFIC) are necessary and more popular. It is trend to use light, thin, tiny and electricity-saving in wireless communication product. Therefore, it fit the demand of the integration of RFIC, gradually become the most important key components in wireless communication systems. During the last several years, RF front-end circuits using CMOS processes are well-developed, and become more matu

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44

HSU, Chi-Hsiang, and 徐麒翔. "Design of CMOS 5.7GHz Receiver Front-end Integrated Circuits." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/64514369134523395834.

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碩士<br>國立臺灣海洋大學<br>電機工程學系<br>101<br>In this thesis, we research the receiver front-end circuits for unlicensed WiMAX applications which include low noise amplifier (LNA), voltage-controlled oscillator (VCO) and mixer. The proposed circuits are simulated with the Agilent Advanced Design System (ADS) software supported by National Chip Implementation Center (CIC), and are implemented in TSMC 0.18um 1P6M CMOS process. The first chip is a low noise amplifier (LNA) which uses the cascade architecture and inductive source degeneration to improve linearity. The measurement results show that the po

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45

"Design and implementation of linearized CMOS mixer for RF application." 2003. http://library.cuhk.edu.hk/record=b5891513.

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Au-Yeung Chung-Fai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.<br>Includes bibliographical references (leaves 85-91).<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgments --- p.iii<br>Contents --- p.iv<br>Chapter Chapter 1 --- Introduction --- p.1<br>Chapter Chapter 2 --- Basic Theory of Mixer --- p.6<br>Chapter 2.1 --- Definition of mixer's electrical parameters --- p.8<br>Chapter 2.2.1 --- Conversion gain --- p.8<br>Chapter 2.2.2 --- Port-to-port isolation --- p.8<br>Chapter 2.2.3 --- Noise figure --- p.9<br>Chapter 2.2.4 --- 1-dB compression

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46

紀忠志. "Design of 2.4GHz Low noise Amplifier RF CMOS Integrated Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/84485518702785018166.

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碩士<br>明新科技大學<br>電子工程研究所<br>93<br>Because of the operated in higher frequency on RF front end in the wireless communication system, the procession still use the high cost and low integrated use in the front end modules. Up to now the technology is available use the high-integration and low-cost to fit the rapid development of CMOS processes. In this paper, we design three low-noise amplifier circuit performances by inserting the 0.18μm CMOS process parameters of TSMC into the Advanced Design System (ADS) software of Aglient. The first circuit is fully integrated high gain 2.4-GHz LNA CMOS RF

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47

Lin, Po-Hsuan, and 林伯軒. "Design of UWB CMOS RF Receiver Front-end Integrated Circuits." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/stn234.

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碩士<br>國立臺灣海洋大學<br>電機工程學系<br>106<br>In this thesis, the RF receiver front-end circuits for UWB are presented to the system on a chip, which consist of a low noise amplifier, a mixer, and a voltage-controlled oscillator. The circuit components are designed by TSMC 0.18 um 1P6M CMOS Mixed-Signal model and simulated in the Agilent Advanced Design System (ADS) software on EDA Cloud provided by National Chip Implementation Center. A low noise amplifier is the first chip, which adopts current-reuse architecture as the core circuit. To reduce power consumption and increase gain and bandwidth in the o

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48

"Design and implementation of linearized CMOS RF mixers and amplifiers." Thesis, 2007. http://library.cuhk.edu.hk/record=b6074403.

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For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasi

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49

王志生. "Design of High Linearity of 5.8GHz Mixer RF CMOS Integrated Circuits." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/84276267952046148711.

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碩士<br>明新科技大學<br>電子工程研究所<br>94<br>In this paper, we study two types of high linearity 5.8 GHz CMOS down-conversion double-balanced mixers. They are designed by 0.18 μm CMOS process parameters of TSMC, and simulated in Advanced Design System (ADS) of Agilent software. The frequencies of radio (RF), local (LO), and intermediate (IF) for design and simulation are 5.8 GHz, 5.6 GHz, and 200 MHz respectively. The structure of the circuit is a double-balanced mixer, since it has very good LO-RF and LO-IF isolation. In addition, it can suppress the even harmonics of RF and LO signal. Although the IP2 o

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50

Tsai, Hui-Wen, and 蔡惠雯. "DESIGN AND IMPLEMENTATION TO IMPROVE LATCHUP IMMUNITY OF CMOS INTEGRATED CIRCUITS." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/en7qdd.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>Latchup is a common problem in the CMOS IC product design and may lead to the damage or the malfunction of the chip. It is originated from the conducting of the internal parasitic P-N-P-N structure by the applied external voltage or current perturbation. Large current may be generated this time and causes the short through between the junctions and the open for the connections (as contacts, vias, or the metal lines) through the power line to the damaged devices. Besides, to prevent the destroying action and the threat brought by the Electrostatic Discharg

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