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Journal articles on the topic 'Design of CMOS integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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1

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to

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2

WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p

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3

Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or

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4

ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS

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5

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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6

de Sousa, J. J. H. T., F. M. Goncalves, and J. P. Teixeira. "Physical design of testable CMOS digital integrated circuits." IEEE Journal of Solid-State Circuits 26, no. 7 (1991): 1064–72. http://dx.doi.org/10.1109/4.92027.

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7

Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

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Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used compleme

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8

Camplani, Alessandra, Seyedruhollah Shojaii, Hitesh Shrimali, Alberto Stabile, and Valentino Liberali. "CMOS IC radiation hardening by design." Facta universitatis - series: Electronics and Energetics 27, no. 2 (2014): 251–58. http://dx.doi.org/10.2298/fuee1402251c.

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Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design.

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9

Tarim, T. B., and M. Ismail. "Robust design of low power CMOS analogue integrated circuits." IEE Proceedings - Circuits, Devices and Systems 148, no. 4 (2001): 197. http://dx.doi.org/10.1049/ip-cds:20010340.

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10

Shoucair, F. "Design Consideration in High Temperature Analog CMOS Integrated Circuits." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 9, no. 3 (1986): 242–51. http://dx.doi.org/10.1109/tchmt.1986.1136646.

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11

ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

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Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or

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12

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad ar

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13

Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C langu

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14

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of co

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15

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100

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16

Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

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We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron le

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17

Kiela, Karolis, and Romualdas Navickas. "AUTOMATED INTEGRATED ANALOG FILTER DESIGN ISSUES / AUTOMATIZUOTOJO INTEGRINIŲ ANALOGINIŲ FILTRŲ PROJEKTAVIMO YPATUMAI." Mokslas – Lietuvos ateitis 7, no. 3 (2015): 323–29. http://dx.doi.org/10.3846/mla.2015.793.

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An analysis of modern automated integrated analog circuits design methods and their use in integrated filter design is done. Current modern analog circuits automated tools are based on optimization algorithms and/or new circuit generation methods. Most automated integrated filter design methods are only suited to gmC and switched current filter topologies. Here, an algorithm for an active RC integrated filter design is proposed, that can be used in automated filter designs. The algorithm is tested by designing an integrated active RC filter in a 65 nm CMOS technology. Atlikta naujausių integri

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18

Jeong, Kyungsoo, Duckhoon Ro, Gwanho Lee, Myounggon Kang, and Hyung-Min Lee. "A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications." Electronics 7, no. 12 (2018): 429. http://dx.doi.org/10.3390/electronics7120429.

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A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radi

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19

Huang, Tsung-Ching, Ting Lei, Leilai Shao, et al. "Process Design Kit and Design Automation for Flexible Hybrid Electronics." Journal of Microelectronics and Electronic Packaging 16, no. 3 (2019): 117–23. http://dx.doi.org/10.4071/imaps.925849.

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Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (&lt;50 μm) silicon chips on soft, thin, and flexi

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20

Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper present

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21

Ker, Ming-Dou, and Chyh-Yih Chang. "ESD protection design for CMOS RF integrated circuits using polysilicon diodes." Microelectronics Reliability 42, no. 6 (2002): 863–72. http://dx.doi.org/10.1016/s0026-2714(02)00049-5.

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22

Karmani, Mouna, Chiraz Khedhiri, Belgacem Hamdi, Ka Lok Man, and Rached Tourki. "A design for testability approach for nano-CMOS analogue integrated circuits." International Journal of Electronics 100, no. 6 (2013): 837–50. http://dx.doi.org/10.1080/00207217.2012.720957.

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23

Palumbo, G. "The Design of CMOS Radiofrequency Integrated Circuits, 2nd ED - [Book Review]." IEEE Circuits and Devices Magazine 21, no. 6 (2005): 53. http://dx.doi.org/10.1109/mcd.2005.1578590.

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24

Palumbo, G. "The Design of CMOS Radiofrequency Integrated Circuits, 2nd Edition [Book Review]." IEEE Circuits and Devices Magazine 22, no. 4 (2006): 36. http://dx.doi.org/10.1109/mcd.2006.1708388.

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25

ALLSTOT, DAVID J., SANKARAN ANIRUDDHAN, MIN CHU, JEYANANDH PARAMESH, and SUDIP SHEKHAR. "RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 377–428. http://dx.doi.org/10.1142/s0129156405003247.

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Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides c

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26

de Lima Moreto, Rodrigo Alves, Carlos Eduardo Thomaz, and Salvador Pinillos Gimenez. "Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 10 (2017): 1620–32. http://dx.doi.org/10.1109/tcad.2017.2661804.

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27

Chen, Shen Li, and Hsiang Pei Ou. "Design of Three-Phase CDROM Motor Driver Chip by Using a 0.6um CMOS Process." Applied Mechanics and Materials 271-272 (December 2012): 1265–69. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1265.

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This paper deals with the design and analysis of a three-phase CDROM motor driver chip using a 0.6um CMOS process. An analysis of this circuits system, it is found that the driving current can be up to 500mA as in the three-phase DC motor operation. In the CMOS process, a lot of component, i.e., control and power circuits are integrated in the same chip. Here, we will focus on the design of high-current driver part and present the results obtained from the motor operating at different situations.

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28

Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation,

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29

Ul Alam, Arif, Nishatul Majid, and SK Aditya. "Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind." Dhaka University Journal of Science 60, no. 1 (2012): 103–8. http://dx.doi.org/10.3329/dujs.v60i1.10346.

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A good deal of ingenuity can be exercised and a vast amount of time wasted exploring layout topologies to minimize the size of a gate or other circuitry such as an adder or memory element in an integrated circuit. This paper represents a simple and compact layout design for two bit binary parallel ripple carry adder using only CMOS NAND gates with the help of Microwind as a tool for design and simulation. Construction of this adder for fabricating involves the design of 2-input, 3-input, 4-input NAND gates and CMOS NAND inverters. The performance parameters are analyzed from the simulation res

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30

Kompitaya, Pantre, and Khanittha Kaewdang. "An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter." Journal of Circuits, Systems and Computers 25, no. 06 (2016): 1650066. http://dx.doi.org/10.1142/s0218126616500663.

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A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circ

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31

SHABADI, PRASAD, SANKARA NARAYANAN RAJAPANDIAN, SANTOSH KHASANVIS, and CSABA ANDRAS MORITZ. "DESIGN OF SPIN WAVE FUNCTIONS-BASED LOGIC CIRCUITS." SPIN 02, no. 03 (2012): 1240006. http://dx.doi.org/10.1142/s2010324712400061.

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Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we

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32

Ibarra, F. Sandoval, and S. Ortega Cisneros. "Nyquist Model based Thermal Noise AnalysisFrom Passive Components to CMOS Circuits." International Journal of Emerging Technology and Advanced Engineering 11, no. 1 (2021): 1–8. http://dx.doi.org/10.46338/ijetae0121_01.

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The analysis of thermal noise in network components that have resistive properties is presented. Noise analysis, based on the Nyquist model, is calculated as the rms (voltage or current equivalent) noise generated by a transimpedance, which is the concept used by general-purpose circuit simulators like Spice. It shows how this concept is used and understood in RC circuits, and how to evaluate its effect in analog circuits, particularly in the design of CMOS integrated circuits. It is shown that the magnitude of the noise generated by a transistor is not of interest, but the net effect of all s

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33

LEE, JANGJOON, SRIKAR BHAGAVATULA, SWARUP BHUNIA, KAUSHIK ROY, and BYUNGHOO JUNG. "SELF-HEALING DESIGN IN DEEP SCALED CMOS TECHNOLOGIES." Journal of Circuits, Systems and Computers 21, no. 06 (2012): 1240011. http://dx.doi.org/10.1142/s0218126612400117.

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CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for

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SHAN, WEIWEI, YAN LIANG, and DONGMING JIN. "CMOS CIRCUIT DESIGN OF A TAKAGI-SUGENO FUZZY LOGIC CONTROLLER." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 841–56. http://dx.doi.org/10.1142/s0218126609005009.

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This paper presents a low power CMOS analog integrated circuit of a Takagi–Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defu

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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write

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Chen, Shih-Hung, and Ming-Dou Ker. "Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits." Microelectronics Reliability 47, no. 9-11 (2007): 1502–5. http://dx.doi.org/10.1016/j.microrel.2007.07.095.

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Lee, Minwoong, Seongik Cho, Namho Lee, and Jongyeol Kim. "New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis." Electronics 9, no. 3 (2020): 388. http://dx.doi.org/10.3390/electronics9030388.

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A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakag

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Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.

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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical

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Tarim, T. B., M. Ismail, and H. H. Kuntman. "Robust design and yield enhancement of low-voltage CMOS analog integrated circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48, no. 4 (2001): 475–86. http://dx.doi.org/10.1109/81.917984.

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Liu, Lun Cai, Xiao Zong Huang та Wen Gang Huang. "An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process". Applied Mechanics and Materials 251 (грудень 2012): 206–9. http://dx.doi.org/10.4028/www.scientific.net/amm.251.206.

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A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in

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Kladovščikov, Leonid, Marijan Jurgo, and Romualdas Navickas. "Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS." Electronics 8, no. 7 (2019): 813. http://dx.doi.org/10.3390/electronics8070813.

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In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test

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HUNG, YU-CHERNG, SHAO-HUI SHIEH, and CHIOU-KOU TUNG. "A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 89–105. http://dx.doi.org/10.1142/s0218126611007104.

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Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivatio

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Yu, Chang Hong. "Fault Tolerance Design by Accurate SER Estimation Based on Ensemble Transform Matrix." Advanced Materials Research 108-111 (May 2010): 347–52. http://dx.doi.org/10.4028/www.scientific.net/amr.108-111.347.

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With development of CMOS process, the minimum lithographic feature has now scaled down to regime of nano-scale. Integrated circuits (ICs) are becoming increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. With all kinds of faults and errors, soft error is the most common and widespread. The different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the soft error rate (SER) efficiently to make the design more fault tolerant. In this paper, we propose and investigate t

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-

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FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the I

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Lee, Min Chin, Ming Chia Hsieh, and Chi Jing Hu. "Implementation and Design of High PSRR Low Dropout Regulator." Advanced Materials Research 614-615 (December 2012): 1553–57. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1553.

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As the progress with all kinds of mixed-mode signal circuits, the requirements of power management become increasingly stringent. Therefore it takes all kinds of high-performance linear regulator to produce a very clean and stable voltage. Here cascading technique is used to increase the output impedance in this architecture. The output voltage is less susceptible to variation of input voltage, resulting in a clean and stable voltage which is used the operating voltage of internal circuits in a mixed-mode signal integrated circuit chip. This paper using the TSMC 0.35μm CMOS 2P4M process to imp

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Kappert, Holger, Stefan Dreiner, Dirk Dittrich, et al. "High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000154–58. http://dx.doi.org/10.4071/hitec-wa14.

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Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature op

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KUMAR, RANJITH, ZHIYU LIU, and VOLKAN KURSUN. "TECHNIQUE FOR ACCURATE POWER AND ENERGY MEASUREMENT WITH THE COMPUTER-AIDED DESIGN TOOLS." Journal of Circuits, Systems and Computers 17, no. 03 (2008): 399–421. http://dx.doi.org/10.1142/s0218126608004381.

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Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented.

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Kalra, Shruti, та A. B. Bhattacharyya. "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model". Journal of Integrated Circuits and Systems 11, № 1 (2016): 57–68. http://dx.doi.org/10.29292/jics.v11i1.430.

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Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The g

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Asghar, Malik Summair, Saad Arslan, and Hyungwon Kim. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits." Sensors 21, no. 13 (2021): 4462. http://dx.doi.org/10.3390/s21134462.

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To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Ex

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