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Relevant bibliographies by topics / Design of timing

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Academic literature on the topic 'Design of timing'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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Journal articles on the topic "Design of timing"

1

Thiele, Lothar, and Reinhard Wilhelm. "Design for Timing Predictability." Real-Time Systems 28, no. 2/3 (November 2004): 157–77. http://dx.doi.org/10.1023/b:time.0000045316.66276.6e.

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Stevens, K. S., R. Ginosar, and S. Rotem. "Relative timing [asynchronous design]." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 1 (February 2003): 129–40. http://dx.doi.org/10.1109/tvlsi.2002.801606.

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Li, Caipin, and Mingyi He. "Timing design for geosynchronous SAR." Electronics Letters 52, no. 10 (May 2016): 868–70. http://dx.doi.org/10.1049/el.2015.3840.

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Sun, Quanyu. "Design of Beidou timing module." IOP Conference Series: Earth and Environmental Science 508 (July 1, 2020): 012207. http://dx.doi.org/10.1088/1755-1315/508/1/012207.

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Feng, Jia Mei, Yuan Cheng Yao, and Ming Wei Qin. "An Improved Timing Recovery Algorithm Design." Applied Mechanics and Materials 130-134 (October 2011): 2997–3000. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.2997.

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Timing-jitter is an important index of timing recovery algorithm. This paper describes impact-factors of timing-jitter in an AWGN channel and discovers that input noise have great influence on it, proposed an improved timing recovery method for adding a loop gain to reduce it. Simulations demonstrate that a timing recovery with loop gain can have performance superior to that of without it, and got the conclusion that add loop gain at the range of 0.1 to 0.3 both timing jitter and timing recovery points can reach minimum values. Better yet, when choose a loop gain at 0.1, timing jitter decrease from ±0.2 to ±0.08, and system’s error rates also have obverse decrease.

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Zhu, Yu Xin, and Yi Chi Zhang. "Design of Timing System Based on Electronic Design Automation." Applied Mechanics and Materials 380-384 (August 2013): 3404–8. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3404.

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Timing system is widely used in plenty of fields. This paper introduces a method to use PLD programmable devices to design a timing system which has been optimized and then become especially suitable for humans listening habit. The design circuits and simulation waveforms are shown in the paper. The simulation results show that the design is practical and easier to implement.

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Hermeling, Mark, Onno van Roosmalen, and Bran Selic. "Timing Constraints and Object-Oriented Design." IFAC Proceedings Volumes 32, no. 1 (May 1999): 39–44. http://dx.doi.org/10.1016/s1474-6670(17)39962-7.

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Quine, Richard W., James R. Harbridge, Sandra S. Eaton, and Gareth R. Eaton. "Design of a programmable timing unit." Review of Scientific Instruments 70, no. 11 (November 1999): 4422–32. http://dx.doi.org/10.1063/1.1150088.

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Roadifer, Randahl D., and Thomas R. Moore. "Coalbed Methane Pilots--Timing, Design, and Analysis." SPE Reservoir Evaluation & Engineering 12, no. 05 (October 27, 2009): 772–82. http://dx.doi.org/10.2118/114169-pa.

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Summary Four distinct sequential phases form a recommended process for coalbed-methane (CBM)-prospect assessment: initial screening, reconnaissance, pilot testing, and final appraisal. Stepping through these four phases provides a program of progressively ramping work and cost, while creating a series of discrete decision points at which analysis of results and risks can be assessed. While discussing each of these phases in some degree, this paper focuses on the third, the critically important pilot-testing phase. This phased CBM-prospect assessment process allows us toGain local knowledge early at low costProgressively acquire and compile appropriate data to assess the geological situation and reservoir conditions systematicallyIdentify and attempt to fill the most important knowledge gaps that represent the greatest uncertainties and risks to the prospectIncreasingly understand the distributions of key parameters that control reserves, deliverability, and valueStage expenditures and provide multiple decision points through the processUltimately, produce a project with very low development risk In the CBM-prospect assessment process, the pilot test serves the same function as a conventional exploration well. If it proves successful, then the prospect can be considered a discovery and can be appraised for development. By drilling, completing, and producing a cluster of wells in a CBM pilot test, short of proceeding directly to a partial development, we are able to locally dewater and depressurize the coal seam to be tested and, thereby, desorb and deliver measurable volumes of gas. If correctly implemented, the pilot test allows us to assess the local variability of key reservoir parameters, collect the information necessary to simulate the reservoir's producibility, and, thereby, estimate potential project reserves to a reasonable degree of accuracy. This paper contains roughly 30 specific recommendations and the fundamental rationale behind each recommendation to help ensure that a CBM pilot will fulfill its primary objectives of (1) demonstrating whether the subject coal reservoir will desorb and produce consequential gas and (2) gathering the data critical to evaluate and risk the prospect at the next--often most critical--decision point. Importantly, these objectives must be met in a timely manner. To do this, the specifications for the pilot are often not those that will be used for an optimized well or field-development pattern in terms of costs or production. This is intentional. The goals of piloting are different from the goals of development. So, the recommended designs are different. The pilot design recommendations focus on collecting superior data that will quantify key parameters for interpretation and simulation of the reservoir, retaining flexibility in the face of the level of uncertainty remaining after the reconnaissance phase, and arriving at a definitive answer on the coal reservoir's viability in an acceptable time frame. Detailed data-analysis methods for CBM are not discussed here--these are well covered in the literature. Rather, we focus on the importance, use, and potential pitfalls of data collected at the various phases of the assessment process. Examples are used to highlight the purpose and importance of various aspects of the data gathering and analysis. A general history-matching process--valid at the pilot-stage analysis and beyond--is presented as a guide.

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CHEN Jian-jun, 陈建军, 金强宁 JIN Qiang-ning, 章鹏 ZHANG Peng, and 刘凯丽 LIU Kai-li. "FPGA-based TFT LCD timing controller design." Chinese Journal of Liquid Crystals and Displays 30, no. 4 (2015): 647–54. http://dx.doi.org/10.3788/yjyxs20153004.0647.

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Dissertations / Theses on the topic "Design of timing"

1

Heintz, Kathryn D. "A timing simulator /." Online version of thesis, 1988. http://hdl.handle.net/1850/8307.

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Zhou, Shuo. "Static timing analysis in VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3207193.

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Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed May 18, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 110-113).

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Yang, Hai-Gang. "Timing verification in digital CMOS VLSI design." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387095.

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Ozgun, Recep. "Design and timing analysis of wave pipelined circuits." Thesis, Wichita State University, 2006. http://hdl.handle.net/10057/383.

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In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shortest path delays. In some circuit designs there are redundant elements to make the circuit less sensitive to noise, to provide higher signal driving capability, or other purposes. Also, some circuit designs include logic to detect the early completion of a computation, or to guarantee that the worst physical path delay does not equate to the worst computational delay. Prior tools for wave-pipelined circuits do not account for such design features. This research develops a computer-aided design tool to determine the maximum clock speed for wave pipelined circuits with redundant logic or where otherwise the internal circuit timing depends on the input signal values. Moreover, alternative design techniques are proposed to improve the performance of wave pipelined circuits.
Includes bibliographic references (leaves 39-41)
Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006."
Includes bibliographic references (leaves 39-41)

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Ozgun, Recep Meyer Fred J. "Design and timing analysis of wave pipelined circuits." Diss., Click here for available full-text of this thesis, 2006. http://library.wichita.edu/digitallibrary/etd/2006/t064.pdf.

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Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006." Title from PDF title page (viewed on October 29, 2006). Thesis adviser: Fred J. Meyer. Includes bibliographic references (leaves 39-41).

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Daboul, Siad [Verfasser]. "Global Timing Optimization in Chip Design / Siad Daboul." Bonn : Universitäts- und Landesbibliothek Bonn, 2021. http://d-nb.info/1235525341/34.

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Chen, Tsorng-Ming. "Design validation of digital systems." Thesis, University of Southampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.264452.

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Fogaça, Mateus Paiva. "A new quadratic formulation for incremental timing-driven placement." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/164067.

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O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente.
The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.

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Matson, Gary. "Computer aided design of multiple pulley timing belt drives /." Online version of thesis, 1988. http://hdl.handle.net/1850/10411.

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Zhang, Lu. "Timing synchronization algorithm design for MB-OFDM UWB systems /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20ZHANGL.

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Books on the topic "Design of timing"

1

Sapatnekar, Sachin S. Timing. New York: Springer, 2011.

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Timing. Boston: Kluwer Academic Publishers, 2004.

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1961-, Overhauser David, ed. Digital timing macromodeling for VLSI design verification. Boston: Kluwer Academic, 1995.

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Sapatnekar, Sachin S. Design automation for timing-driven layout synthesis. Boston: Kluwer Academic Publishers, 1993.

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Kong, Jeong-Taek. Digital Timing Macromodeling for VLSI Design Verification. Boston, MA: Springer US, 1995.

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Kong, Jeong-Taek, and David Overhauser. Digital Timing Macromodeling for VLSI Design Verification. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2321-5.

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Sapatnekar, Sachin S., and Sung-Mo Kang. Design Automation for Timing-Driven Layout Synthesis. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3178-4.

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Sapatnekar, Sachin S. Design Automation for Timing-Driven Layout Synthesis. Boston, MA: Springer US, 1993.

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9

Perneder, Raimund. Handbook Timing Belts: Principles, Calculations, Applications. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012.

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Kourtev, Ivan S. Timing Optimization Through Clock Skew Scheduling. Boston, MA: Springer US, 2000.

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Book chapters on the topic "Design of timing"

1

Simpson, Philip. "Timing Closure." In FPGA Design, 107–32. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_12.

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Simpson, Philip Andrew. "Timing Closure." In FPGA Design, 191–226. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_14.

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Huber, John P., and Mark W. Rosneck. "Timing." In Successful ASIC Design the First Time Through, 111–28. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4684-7885-3_6.

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Taraate, Vaibbhav. "Timing Analysis." In ASIC Design and Synthesis, 229–43. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4642-0_15.

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Churiwala, Sanjay, and Sapan Garg. "Timing Analysis." In Principles of VLSI RTL Design, 43–71. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9296-3_3.

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Churiwala, Sanjay, and Sapan Garg. "Timing Exceptions." In Principles of VLSI RTL Design, 147–66. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9296-3_7.

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Yoong, Li Hsien, Partha S. Roop, Zeeshan E. Bhatti, and Matthew M. Y. Kuo. "Timing Analysis." In Model-Driven Design Using IEC 61499, 137–59. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-10521-5_7.

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Golshan, Khosrow. "Design Constraints." In The Art of Timing Closure, 77–85. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-49636-4_3.

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Golshan, Khosrow. "Design Signoff." In The Art of Timing Closure, 163–99. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-49636-4_8.

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Baig, Hasan, and Jan Madsen. "Genetic Circuits Timing Analysis." In Genetic Design Automation, 37–60. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52355-8_4.

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Conference papers on the topic "Design of timing"

1

Pulka, Andrzej, and Adam Milik. "VEST - An intelligent tool for timing SoCs verification using UML timing diagrams." In Design Languages (FDL). IEEE, 2008. http://dx.doi.org/10.1109/fdl.2008.4641432.

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Wallace, D. E., and C. H. Sequin. "Plug-In Timing Models for an Abstract Timing Verifier." In 23rd ACM/IEEE Design Automation Conference. IEEE, 1986. http://dx.doi.org/10.1109/dac.1986.1586164.

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Zhou, Shuo, Yi Zhu, Yuanfang Hu, Ronald Graham, Mike Hutton, and Chung-kuan Cheng. "Timing Model Reduction for Hierarchical Timing Analysis." In 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, 2006. http://dx.doi.org/10.1109/iccad.2006.320150.

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De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, and Chingwei Yeh. "Timing driven power gating." In 2006 Design Automation Conference. IEEE, 2006. http://dx.doi.org/10.1109/dac.2006.229189.

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Shrivastava, S., and H. Parameswaran. "Improved Timing Windows Overlap Check Using Statistical Timing Analysis." In 2011 24th International Conference on VLSI Design: concurrently with the 10th International Conference on Embedded Systems Design. IEEE, 2011. http://dx.doi.org/10.1109/vlsid.2011.21.

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Lizheng Zhang, Weijen Chen, Yuhen Hu, J. A. Gubner, and C. C. P. Chen. "Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model." In 2005 42nd Design Automation Conference. IEEE, 2005. http://dx.doi.org/10.1109/dac.2005.193778.

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Burstein, M., and M. N. Youssef. "Timing Influenced Layout Design." In 22nd ACM/IEEE Design Automation Conference. IEEE, 1985. http://dx.doi.org/10.1109/dac.1985.1585923.

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Wu, Pei-Ci, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, and Vidyamani Parkhe. "On Timing Closure." In the The 51st Annual Design Automation Conference. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2593069.2593171.

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Burstein, Michael, and Mary N. Youssef. "Timing influenced layout design." In the 22nd ACM/IEEE conference. New York, New York, USA: ACM Press, 1985. http://dx.doi.org/10.1145/317825.317845.

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Wang, Li-C., Pouria Bastani, and Magdy S. Abadir. "Design-silicon timing correlation." In the 44th annual conference. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1278480.1278580.

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Reports on the topic "Design of timing"

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Wiedwald, J., P. Van Aersau, and E. Bliss. National Ignition Facility sub-system design requirements integrated timing system SSDR 1.5.3. Office of Scientific and Technical Information (OSTI), August 1996. http://dx.doi.org/10.2172/632848.

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Holland, Stephen, and Michael Moore. Market Design in Cap and Trade Programs: Permit Validity and Compliance Timing. Cambridge, MA: National Bureau of Economic Research, May 2012. http://dx.doi.org/10.3386/w18098.

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Araya, Million. Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Final Paper. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1213210.

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Araya, Million. Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - General Abstract. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1213212.

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Araya, Million. Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Oral Presentation. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1213213.

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Roger L. Keller. Design Feature Evaluation No.9 and No.10 Timing of Repository Closure-Maintenance of Underground Featured and Ground Support. Office of Scientific and Technical Information (OSTI), March 1999. http://dx.doi.org/10.2172/762904.

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Burgess, Caitlin, and John R. Skalski. The Design and Analysis of Salmonid Tagging Studies in the Columbia Basin : Volume XVII : Effects of Ocean Covariates and Release Timing on First Ocean-Year Survival of Fall Chinook Salmon from Oregon and Washington Coastal Hatcheries. Office of Scientific and Technical Information (OSTI), May 2001. http://dx.doi.org/10.2172/961874.

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DiGrande, Laura, Sue Pedrazzani, Elizabeth Kinyara, Melanie Hymes, Shawn Karns, Donna Rhodes, and Alanna Moshfegh. Field Interviewer– Administered Dietary Recalls in Participants’ Homes: A Feasibility Study Using the US Department of Agriculture’s Automated Multiple-Pass Method. RTI Press, May 2021. http://dx.doi.org/10.3768/rtipress.2021.mr.0045.2105.

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Objective: The purpose of this study was to assess the feasibility of administering the Automated Multiple-Pass Method (AMPM), a widely used tool for collecting 24-hour dietary recalls, in participants’ homes by field interviewers. Design: The design included computer-assisted personal interviews led by either a nutritionist (standard) or field interviewer. Portion estimators tested were a set of three-dimensional food models (standard), a two-dimensional food model booklet, or a tablet with digital images rendered via augmented reality. Setting: Residences in central North Carolina. Participants: English-speaking adults. Pregnant women and individuals who were fasting were excluded. Results: Among 133 interviews, most took place in living rooms (52%) or kitchens (22%). Mean interview time was 40 minutes (range 13–90), with no difference by interviewer type or portion estimator, although timing for nutritionist-led interviews declined significantly over the study period. Forty-five percent of participants referenced items from their homes to facilitate recall and portion estimation. Data entry and post-interview coding was evaluated and determined to be consistent with requirements for the National Health and Nutrition Examination Survey. Values for the number of food items consumed, food groups, energy intake (average of 3,011 kcal for men and 2,105 kcal for women), and key nutrients were determined to be plausible and within reasonably expected ranges regardless of interviewer type or portion estimator used. Conclusions: AMPM dietary recall interviews conducted in the home are feasible and may be preferable to clinical administration because of comfort and the opportunity for participants to access home items for recall. AMPMs administered by field interviewers using the food model booklet produced credible nutrition data that was comparable to AMPMs administered by nutritionists. Training field interviewers in dietary recall and conducting home interviews may be sensible choices for nutrition studies when response rates and cost are concerns.

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de Caritat, Patrice, Brent McInnes, and Stephen Rowins. Towards a heavy mineral map of the Australian continent: a feasibility study. Geoscience Australia, 2020. http://dx.doi.org/10.11636/record.2020.031.

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Heavy minerals (HMs) are minerals with a specific gravity greater than 2.9 g/cm3. They are commonly highly resistant to physical and chemical weathering, and therefore persist in sediments as lasting indicators of the (former) presence of the rocks they formed in. The presence/absence of certain HMs, their associations with other HMs, their concentration levels, and the geochemical patterns they form in maps or 3D models can be indicative of geological processes that contributed to their formation. Furthermore trace element and isotopic analyses of HMs have been used to vector to mineralisation or constrain timing of geological processes. The positive role of HMs in mineral exploration is well established in other countries, but comparatively little understood in Australia. Here we present the results of a pilot project that was designed to establish, test and assess a workflow to produce a HM map (or atlas of maps) and dataset for Australia. This would represent a critical step in the ability to detect anomalous HM patterns as it would establish the background HM characteristics (i.e., unrelated to mineralisation). Further the extremely rich dataset produced would be a valuable input into any future machine learning/big data-based prospectivity analysis. The pilot project consisted in selecting ten sites from the National Geochemical Survey of Australia (NGSA) and separating and analysing the HM contents from the 75-430 µm grain-size fraction of the top (0-10 cm depth) sediment samples. A workflow was established and tested based on the density separation of the HM-rich phase by combining a shake table and the use of dense liquids. The automated mineralogy quantification was performed on a TESCAN® Integrated Mineral Analyser (TIMA) that identified and mapped thousands of grains in a matter of minutes for each sample. The results indicated that: (1) the NGSA samples are appropriate for HM analysis; (2) over 40 HMs were effectively identified and quantified using TIMA automated quantitative mineralogy; (3) the resultant HMs’ mineralogy is consistent with the samples’ bulk geochemistry and regional geological setting; and (4) the HM makeup of the NGSA samples varied across the country, as shown by the mineral mounts and preliminary maps. Based on these observations, HM mapping of the continent using NGSA samples will likely result in coherent and interpretable geological patterns relating to bedrock lithology, metamorphic grade, degree of alteration and mineralisation. It could assist in geological investigations especially where outcrop is minimal, challenging to correctly attribute due to extensive weathering, or simply difficult to access. It is believed that a continental-scale HM atlas for Australia could assist in derisking mineral exploration and lead to investment, e.g., via tenement uptake, exploration, discovery and ultimately exploitation. As some HMs are hosts for technology critical elements such as rare earth elements, their systematic and internally consistent quantification and mapping could lead to resource discovery essential for a more sustainable, lower-carbon economy.

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