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1

Sapatnekar, Sachin S. Timing. Springer, 2011.

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2

Timing. Kluwer Academic Publishers, 2004.

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3

1961-, Overhauser David, ed. Digital timing macromodeling for VLSI design verification. Kluwer Academic, 1995.

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4

Sapatnekar, Sachin S. Design automation for timing-driven layout synthesis. Kluwer Academic Publishers, 1993.

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5

Kong, Jeong-Taek. Digital Timing Macromodeling for VLSI Design Verification. Springer US, 1995.

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6

Kong, Jeong-Taek, and David Overhauser. Digital Timing Macromodeling for VLSI Design Verification. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2321-5.

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7

Sapatnekar, Sachin S., and Sung-Mo Kang. Design Automation for Timing-Driven Layout Synthesis. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3178-4.

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8

Sapatnekar, Sachin S. Design Automation for Timing-Driven Layout Synthesis. Springer US, 1993.

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9

Perneder, Raimund. Handbook Timing Belts: Principles, Calculations, Applications. Springer Berlin Heidelberg, 2012.

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10

Kourtev, Ivan S. Timing Optimization Through Clock Skew Scheduling. Springer US, 2000.

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11

Kahng, Andrew B. VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Science+Business Media B.V., 2011.

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12

Kahng, Andrew B., Jens Lienig, Igor L. Markov, and Jin Hu. VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9591-6.

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13

Maheshwari, Naresh. Timing Analysis and Optimization of Sequential Circuits. Springer US, 1999.

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14

Hochet, Bertrand, Antonio J. Acosta, and Manuel J. Bellido, eds. Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x.

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15

Maheshwari, Naresh. Timing analysis and optimization of sequential circuits. Kluwer Academic, 1999.

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16

Edlund, Greg. Timing analysis and simulation for signal integrity engineers. Prentice Hall, 2008.

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17

Zhu, Qing K. High-speed clock network design. Kluwer Academic Publishers, 2003.

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18

Ku, David C. High level synthesis of ASICs under timing and synchronization constraints. Kluwer Academic Publishers, 1992.

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19

Chadha, Rakesh. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer-Verlag US, 2009.

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20

ACM Special Interest Group on Design Automation. and Association for Computing Machinery, eds. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems: Doubletree Hotel, Monterey, California, December 2-3, 2002. Association for Computing Machinery, 2002.

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21

Ku, David C. High Level Synthesis of ASICs under Timing and Synchronization Constraints. Springer US, 1992.

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22

Ayala, José L., Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, and Gilles Sicard, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3.

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23

Monteiro, José, and René van Leuken, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9.

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24

Azémard, Nadine, and Lars Svensson, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-74442-9.

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25

van Leuken, René, and Gilles Sicard, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1.

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26

Ayala, José L., Delong Shang, and Alex Yakovlev, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36157-9.

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27

Macii, Enrico, Vassilis Paliouras, and Odysseas Koufopavlou, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/b100662.

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28

Svensson, Lars, and José Monteiro, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9.

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29

Vounckx, Johan, Nadine Azemard, and Philippe Maurine, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083.

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30

Chico, Jorge Juan, and Enrico Macii, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/b12033.

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31

Paliouras, Vassilis, Johan Vounckx, and Diederik Verkest, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930.

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32

Meng, Teresa H. Synchronization design for digital systems. Kluwer Academic Publishers, 1991.

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33

Sivaraman, Mukund. A Unified Approach for Timing Verification and Delay Fault Testing. Springer US, 1998.

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34

Lam, William K. C. Timed Boolean functions: A unified formalism for exact timing analysis. Kluwer Academic Publishers, 1994.

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35

Perry, Motty. The optimal timing of procurement decisions and patent allocations. Maurice Falk Institute for Economic Research in Israel, 1997.

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36

Kourtev, Ivan S. Timing optimization through clock skew scheduling. Kluwer Academic, 2000.

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37

International Workshop on Power and Timing Modelling and Optimization (3rd 1993 La Grande Motte, France). Power and timing modelling for performance of integrated circuits: Proceedings of the Third International Workshop on Power and Timing Modelling and Optimization (PATMOS '93), Oct. 11-12, 1993, La Grande Motte, France. IT Press Verlag, 1993.

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38

Sivaraman, Mukund. A unified approach for timing verification and delay fault testing. Kluwer Academic, 1998.

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39

Heusler, Lucas Sebastian. Transistor sizing for timing optimization of combinational digital CMOS circuits. Hartung-Gorre Verlag, 1990.

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40

The animator's eye: Adding life to animation with timing, layout, design, color and sound. Focal Press, 2012.

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41

Motus, Leo. Timing analysis of real-time software: A practical approach to the specification and design of real-time embedded software with an emphasis on timing correctness. Pergamon, 1994.

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42

Glick, Robert R. Six Sigma design of a wideband digital communication system. Addison-Wesley, 1992.

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43

Kinniment, David. Synchronization and arbitration in digital systems. J. Wiley & Sons, 2007.

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44

Kinniment, David. Synchronization and arbitration in digital systems. J. Wiley & Sons, 2007.

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45

Aghdasi, Farhad. Self-clocked asynchronous controllers. University of Zimbabwe Publications, 1996.

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46

David, Harris. Skew-tolerant circuit design. Morgan Kaufmann Publishers, 2001.

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47

Motus, L. Timing analysis of real-time software: A practical approach to the specification and design of real-time ... Pergamon, 1994.

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48

1961-, Hochet Bertrand, Acosta Antonio J. 1966-, and Bellido Manuel J. 1964-, eds. Integrated circuit design: Power and timing modeling, optimization and simulation ; 12th international workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 ; proceedings. Springer, 2002.

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49

Wolf, Fabian. Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes. Springer US, 2002.

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50

Mengali, Umberto. Synchronization techniques for digital receivers. Plenum Press, 1997.

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