Dissertations / Theses on the topic 'Design of timing'

Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed May 18, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 110-113).

In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shortest path delays. In some circuit designs there are redundant elements to make the circuit less sensitive to noise, to provide higher signal driving capability, or other purposes. Also, some circuit designs include logic to detect the early completion of a computation, or to guarantee that the worst physical path delay does not equate to the worst computational delay. Prior tools for wave-pipelined circuits do not account for such design features. This research develops a computer-aided design tool to determine the maximum clock speed for wave pipelined circuits with redundant logic or where otherwise the internal circuit timing depends on the input signal values. Moreover, alternative design techniques are proposed to improve the performance of wave pipelined circuits.
Includes bibliographic references (leaves 39-41)
Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006."
Includes bibliographic references (leaves 39-41)

Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006." Title from PDF title page (viewed on October 29, 2006). Thesis adviser: Fred J. Meyer. Includes bibliographic references (leaves 39-41).

O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente.
The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Sloan School of Management, 2008.
Includes bibliographical references (p. 288-290).
As companies compete to gain market share, increase profits and affect growth they often turn to concurrent engineering in an effort to bring new products to the market more quickly. Despite many anecdotal success stories, implementation of concurrent engineering can often prove difficult. As the pressure to bring new products to market increases, companies often compress their design iteration cycle times in an effort to develop products more quickly. In many cases, design cycles may overlap creating situations where learning opportunities (e.g. through testing) are missed and/or ignored. More perversely, compressing design iteration cycles can cause the creation of "phantom errors" and unnecessary rework as concurrent design activities iterate at different speeds. In this research, I use a system dynamics approach to develop a stylized simulation model of the design-build-test iteration cycle to explore the effects of cycle timing on learning. Specifically, I look at the frequency and timing of integration (build) test events and their effect on new product delivery time, quality, and development cost. This research adds to the existing literature in new product development, concurrent engineering, and system dynamics. Ultimately, the results serve to inform new product development project managers of the implications of design iteration timing on project performance and assist in the scheduling of integration events.
by Daniel J. McCarthy.
Ph.D.

In recent years, the subject of wide-area synchronized measurements has gained a significant amount of attention from the power system researchers. All of this started with the introduction of the Phasor Measurement Unit (PMU), which added a new perspective in the field of wide-area measurement systems (WAMS). With the ever evolving technologies over the years and the need for a more cost effective solution for synchronized frequency measurements, the Frequency Monitoring Network (FNET) was developed and introduced by the Power IT laboratory at Virginia Tech. The FNET is comprised of many Frequency Disturbance Recorders (FDR) geographically distributed throughout the United States. The FDR is a dedicated data acquisition device deployed at the distribution level, which allows for a lower cost and easily deployable WAMS solution. With Internet connectivity and GPS timing synchronization, the FDR provides high accuracy frequency, voltage magnitude and voltage angle data to the remote servers. Although the current FDR design is up to the standard in terms of the measurement accuracy and portability, it is of interest to further the research into alternative architectures and leverage the ever advancing technologies in high speed computing. One of the purposes of this dissertation is to present novel design options for a new generation of FDR hardware design. These design options will allow for more flexibility and to lower reliance on some vendor specific components. More importantly, the designs seek to allow for more computation processing capabilities so that more accurate frequency and angle measurements may be obtained. Besides the fact that the accuracy of frequency and angle measurement is highly dependent on the hardware and the algorithm, much can be said about the role of timing synchronization and its effects on accurate measurements. Most importantly, the accuracy of the frequency and angle estimation is highly dependent on the sampling time of local voltage angles. The challenges to accurate synchronized sampling are two folds. One challenge has to do with the inherent fallbacks of the GPS receiver, which is relatively high cost and limited in availability when the satellite signal is degraded. The other challenge is related to the timing inaccuracies of the sampling pulses, which is attributed to the remainder that results from the imperfect division of the processor counter. This dissertation addresses these issues by introducing the implementation of the high sensitivity (indoor) GPS and network timing synchronization, which aims to increase the availability of frequency measurements in locations that would not have been possible before. Furthermore, a high accuracy timing measurement system is introduced to characterize the accuracy and stability of the conventional crystal oscillator. To this end, a new method is introduced in close association with some prior work in generating accurate sampling time for FDR. Finally, a new method is introduced for modeling the FDR based on the sampling time measurements and some results are presented in order to motivate for more research in this area.
Ph. D.

Driver violations of traffic signals are a major cause of intersection vehicle crashes. The duration of yellow intervals is highly associated with driver yellow/red time stopping behavior. Rainy weather and wet pavement surface conditions may result in changes in both driver behavior and vehicle performance. The research presented in this thesis quantifies the impact of wet pavement surface and rainy weather conditions on driver perception-reaction times (PRTs) and deceleration levels, which are used in statistical models for the design of yellow intervals. A new dataset with a total of 648 stop-run records were collected as part of the research effort during rainy weather and wet pavement surface conditions at the Virginia Department of Transportation's Smart Road facility. This experiment was conducted at a 72.4 km/h (45 mi/h) approach speed where participant drivers encountered a yellow indication initiation. The participant drivers were randomly selected in different age groups (under 40 years old, 40 to 59 years old, and 60 years of age or older) and genders (female and male). Combined with an existing dataset that was collected by the same research group under clear weather conditions during the summer of 2008, statistical models for driver PRT and deceleration levels are developed, considering roadway surface and environmental parameters, driver attributes (age and gender), roadway grade, and time to the intersection at the onset of yellow. Using the state-of-the-practice procedures with the modeled PRT and deceleration levels, inclement weather yellow timings are then developed as a function of different factors (e.g., driver age/gender, roadway grade, speed limits, and precipitation levels). The results indicate that an increase in the duration of change interval is required for wet roadway surface and rainy weather conditions. Lookup tables are developed with different reliability levels to provide practical guidelines for the design of yellow signal timings in wet and rainy weather conditions. These recommended change durations can be integrated within the Vehicle Infrastructure Integration (VII) initiative to provide customizable driver warnings prior to a transition to a red indication.
Master of Science

In this thesis we use a novel refinement-based technique to formally verify data transfer in an asynchronous timing framework. Novel data transfer models are proposed to represent the implicit relationship between clock and data validity events. We construct comprehensive implementation models for a previously published GALS architecture for on-chip systems [MVK+99]. Applying our techniques on this claimed to be hazard-free architecture, we find several hazards, and other dangers, together with additional delay constraints to avoid some of the detected dangers.
We further exam re-design issues of an existing GALS system as compact design, internal structure optimization and reduced power consumption. Exhaustive verifications are applied to re-designed asynchronous wrapper circuits using our proposed refinement-based technique to ensure hazard-free operation.
We explore a strategy to resolve relative timing conflicts by implementing detected chain constraints as new circuit components to be integrated with the original design. This method is applied on two design cases to demonstrate its benefits and tradeoffs.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.

Traffic signal systems serve as one of the most powerful control tools in improving the efficiency of surface transportation travel. Traffic operations on arterial roads are particularly complex because of traffic interruptions caused by signalized intersections along the corridor. This dissertation research presents a systematic framework of integrated traffic control in an attempt to break down the complexities into several simpler sub-problems such as pattern recognition, environment-mobility relationships and multi-objective optimization for multi-criterial signal timing design. The overall goal of this dissertation is to develop signal timing plans, including a day plan schedule, cycle length parameters, splits and offsets, which are suitable for real traffic conditions with consideration of multi-criterial performance of the surface transportation system. To this end, the specific objectives are to: (1) identify appropriate time-of-day breakpoints and intervals to accommodate traffic pattern variations for day plan schedule of signal timing; (2) explore the relationship between environmental outcomes (e.g., emissions) from emission estimators and mobility measures (e.g., delay and stops) for different types of intersections; (3) optimize signal timing parameters for multi-criteria objectives (e.g., minimizing vehicular delay, number of stops, marginal costs of emissions and total costs), with the comparison of performance metrics for different objectives, at the intersection level; (4) optimize arterial offsets for different objectives at the arterial level and compare the performance metrics of different objectives to recommend suitable objectives for integrated multi-criteria signal timing design in arterial traffic operations. An extensive review of the literature, which covers existing tools, traffic patterns, traffic control with environmental concerns, and related optimization methods, shows that both opportunities and challenges have emerged for multi-criteria traffic signal timing design. These opportunities include large quantities of traffic condition data collected by system detectors or non-intrusive data collection platforms as well as powerful tools for microscopic traffic modeling and instantaneous emission estimation. The challenge is how to effectively deal with these big data, either from field collection or detailed simulation, and provide useful information for decision makers in practice. Methodologically, there's a tradeoff between the accuracy of objective function values and the computational efficiency of simulation and optimization. To address this need, in this dissertation, traffic signal timing design that systematically enables the use of integrated data and models are investigated and analyzed in the four steps/studies. The technology of identifying time-of-day breakpoints in the first study shows a mathematical way to classify dynamic traffic patterns by understanding dynamic traffic features and instabilities at a macroscopic level on arterials. Given the limitations of using built-in emissions modules within current traffic simulation and signal optimization tools, the metamodeling-based approach presented in the second study makes a methodological contribution. The findings of the second study on environment-mobility relationships set up the base for extensive application of two-stage optimization in the third and fourth studies for sustainable traffic operations and management. The comparison of outputs from an advanced estimator with those from the current tool also addresses improving the emissions module for more accurate analysis (e.g., benefit-cost analysis) in practical signal retiming projects. The third study shows that there are tradeoffs between minimizing delay and minimizing marginal costs of emissions. When total cost (including cost of delay, fuel consumption and emissions) is set as a single objective function, that objective clears the way for relatively reliable results for all the aspects. In the fourth study, the improvements in marginal cost of emissions and total cost by dynamic programming procedure are obvious, which indicates the effectiveness of using total link cost as an objective at the corridor level. In summary, this dissertation advocates a sustainable traffic control system by simultaneously considering travel time, fuel consumption and emissions. The outcomes of this integrated multi-criteria signal timing design can be easily implemented by traffic operators in their daily life of retiming signal timing.

ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada
Data-aided symbol synchronization for bursty communications utilizes a predetermined modulation sequence, i.e., a preamble, preceding the payload. For effective symbol synchronization, this preamble must be designed in accordance with the modulation format. In this paper, we analyze preambles for shaped offset quadrature phase-shift keying (SOQPSK) waveforms. We compare the performance of several preambles by deriving the Cram´er-Rao bound (CRB), and identify a desirable one for the Telemetry Group variant of SOQPSK. We also demonstrate, via simulation, that the maximum likelihood estimator with this preamble approaches the CRB at moderate signal-to-noise ratio.

Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.

L'anàlisi i el disseny dels sistemes de control de temps real és una tasca complexa, que requereix la integració de dues disciplines, la dels sistemes de control i la dels sistemes de temps real. Tradicionalment però, els sistemes de control de temps real s'han dissenyat diferenciant, de forma independent, dues fases, primerament el disseny del controlador, i després, la seva implementació en un computador. Això ha desembocat en solucions no òptimes tant en termes de planificabilitat del sistema i com en el rendiment dels sistemes controlats.
Normalment, els mètodes i models de la teoria de control de temps discret no consideren durant la fase de disseny dels controladors les limitacions que es puguin derivar de la implementació. En la fase de disseny s'assumeix que els algorismes de control s'executaran en processadors dedicats i que els processadors seran prou ràpids i determinístics per no haver-se de preocupar del comportament temporal que aquests algorismes de control tindran en temps d'execució. Tot i així, quan els recursos - per exemple, processadors - són limitats, apareixen variacions temporals en l'execució dels algorismes de control. En concret, en els sistemes de planificació de tasques de temps real, un algorisme de control s'implementa en una tasca periòdica caracterizada per restriccions temporals estàndards com períodes i terminis. És sabut que, en la planificació de tasques de temps real, les variacions temporals en l'execució d'instàncies de tasques és permesa sempre i quan les restriccions de planificabilitat estiguin garantides. Aquesta variabilitat per tasques de control viola l'estricte comporament temporal que la teoria de control de temps discret pressuposa en l'execució dels algorismes de control.
Això té dos efectes negatius: la variabilitat temporal en l'execució de les tasques de control degrada el rendiment del sistema controlat, fins i tot causant inestabilitat. A més, si es minimitza la probabilitat d'aparició d'aquesta variabilitat en l'execució de les tasques de control a través d'especificacións més limitants, la planificabilitat del conjunt de tasques del sistema disminueix.
Cal tenir en compte que la teoria de control no dóna directrius de com incloure, en la fase de disseny dels controladors, aquesta variabilitat en l'execució de tasques que es deriva de les limitacions d'implementació. A més, la teoria de sistemes de temps real no proporciona ni models de tasques ni restriccions temporals que puguin ser usats per garantir l'execució periòdica, i sense variabilitats temporals, de tasques sense sobrelimitar la planificabilitat dels sistema.
En aquesta tesi es presenta un entorn integrat i flexible de planificació i de control per a l'anàlisi i el disseny de sistemes de control de temps real que dóna solucions als problemes esmentats anteriorment (baixa planificabilitat en el sistema i degradació del rendiment dels sistemes controlats). Mostrem que, fusionant les activitats de la comunitat de temps real amb les de la comunitat de control, això és, integrant la fase de disseny de controladors amb la fase d'implementació en un computador, es millora tant la planificabilitat del sistema com el rendiment dels sistemes controlats.
També es presenta una nova aproximació al disseny de controladors de temps discret que té en compte les limitacions derivables de la implementació i relaxa les tradicionals assumpcions dels controladors de temps discret (mostreig i actuació equidistants). En lloc d'especificar, en la fase de disseny, únics valors pel període de mostreig i pel retard temporal, especifiquem un conjunt de valors tant per l'un com per l'altre. Aquesta nova aproximació al disseny de controladors es basa en la idea d'ajustar, en temps d'execució, els paràmetres del controlador d'acord amb el comportament temporal específic de la implementació (per exemple, d'acord amb la variabilitat en l'execució de les tasques deguda a la planificació). Els llaços de control resultants esdevenent sistemes variants en el temps, amb mostreig irregular i retards temporals variables. Per a aquests sistemes, i utilitzant formulació en l'espai d'estat, presentem una anàlisi completa d'estabilitat, així com l'anàlisi de la resposta.
També mostrem com, a partir de les propietats temporals d'aquesta nova aproximació al disseny de controladors, podem obtenir restriccions temporals més flexibles per a les tasques de control. Les restriccions temporals estàndards, per a les tasques periòdiques en els sistemes de temps real, són constants per a totes les instàncies d'una tasca. Això és, només un sol valor per a una restricció és aplicable a totes les instàncies. Les noves restriccions temporals que presentem per a tasques de control no forcen a aplicar un valor específic, sinó que permeten aplicar valors diferents a cada instància d'una tasca, tenint en compte, per exemple, la planificabilitat d'altres tasques.
Aquestes restriccions temporals flexibles per a tasques de control ens permeten obtenir planificacions viables i sistemes de control estables a partir de conjunts de tasques (incloent tasques de control i d'altres) que no eren planificables en usar mètodes estàndards tant de planificació de temps real com de disseny de controladors. A més, associant informació de rendiment de control a aquestes noves restriccions temporals per a tasques de control, mostrem com podem prendre decisions de planificació que, anant més enllà de complir amb les restriccions temporals, milloren el rendiment dels sistemes controlats quan aquests sofreixen perturbacions.
The analysis and design of real-time control systems is a complex task, requiring the integration and good understanding of both control and real-time systems theory. Traditionally, such systems are designed by differentiating two separate stages: first, control design and then its computer implementation, leading to sub-optimal solutions in terms of both system schedulability and controlled systems performance.
Traditional discrete-time control models and methods consider implementation constraints only to a very small extent. This is due to the fact that in the control design stage, controllers are assumed to execute in dedicated processors and processors are assumed to be fast and deterministic enough not to worry about the timing that the controlling activities may have on the implementation. However, when resources (e.g., processors) are limited, timing variations in the execution of control algorithms occur. Specifically, a control algorithm in traditional real-time scheduling is implemented as a periodic task characterized by standard timing constraints such as period and deadline. In real-time scheduling, timing variations in task instance executions (i.e., jitters) are allowed as far as the schedulability constraints are preserved. Consequently, the resulting jitters for control task instances do not comply with the strict timing demanded by discrete-time control theory.
This has two pervasive effects: the presence of jitters for control tasks degrades the controlled system performance, even causing instability. On the other hand, minimizing the likelihood of jitters for control tasks by over-constraining the control task specification reduces the schedulability of the entire task set.
It is worth mentioning that control theory offers no advice on how to include, into the design of controllers, the effects that implementation constraints have in the timing of the control activities (e.g., scheduling inherent jitters). Also, real-time theory lacks task models and timing constraints that can be used to guarantee a periodic task execution free of jitters without over-constraining system schedulability.
In this thesis we present a flexible integrated scheduling and control analysis and design framework for real-time control systems that solves the problems outlined above: poor system schedulability and controlled systems performance degradation. We show that by merging the activities of the control and real-time communities, that is, by integrating control design with computer implementation, both system schedulability and controlled systems performance are improved.
We present a new approach to discrete-time controller design that takes implementation constraints into account and relaxes the equidistant sampling and actuation assumptions of traditionally designed discrete-time controllers. Instead of specifying a single value for the sampling period and a single value for the time delay at the design stage, we specify a set of values for both the sampling period and for the time delay. This new approach for the controller design relies on the idea of adjusting controller parameters at run time according to the specific implementation timing behaviour, i.e., scheduling inherent jitters. The resulting closed-loop systems are based on irregularly sampled discrete-time system models with varying time delays. We have used state space formulation to present a complete stability and response analysis for such models.
We also show how to derive more flexible timing constraints for control tasks by exploiting the timing properties imposed by this new approach to discrete-time controller design. Real-time scheduling standard timing constraints for periodic tasks are constant for all task instances. That is, a single value of a constraint (e.g., period or deadline) holds for all task instances. Our flexible timing constraints for control tasks do not set specific values. Rather, they provide ranges and combinations to choose from (at each control task instance execution), taking into account, for example, schedulability of other tasks.
That is, these more flexible timing constraints for control tasks allow us to obtain feasible schedules and stable control systems from task sets (including control and non-control tasks) that are not feasible using traditional real-time scheduling and discrete-time control design methods. In addition, by associating control performance information with these new timing constraints for control tasks, we show how scheduling decisions, going beyond meeting timing constraints, can be taken to improve the performance of the controlled systems when they are affected by perturbations.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Schimmel, David, Committee Member ; Meliopoulos, A. P. Sakis, Committee Member ; Mooney, Vincent, Committee Chair ; Prvulovic, Milos, Committee Member ; Yalamanchili, Sudhakar, Committee Member. Includes bibliographical references.

This thesis report presents a new design of a synchronization unit for high power impulse magnetron sputtering (HiPIMS) applications used for depositing thin films. The proposed system is composed of two major hardware parts: a microcontroller unit (MCU) and a field-programmable gate array (FPGA). The control range of the new system is increased by at least ten times compared to existing synchronization unit designed by Ionautics AB.In order to verify the system and benchmark its innovations, several batches of the thin film have been deposited using the new technology. It is shown that HiPIMS with synchronized pulsed substrate bias can effectively improve coating performance. Pulsed substrate bias with user-defined pulse width and delay time is possible to use in the new control mode proposed by this master thesis work; Bias mode. As a result, this master thesis work enables users to flexibly control the HiPIMS processes.

碩士
國立中正大學
電機工程學系
85
AbstractThe development and widespread use of digital transmission, in combination with digital switching, has led to all-digital networks that require timing and synchronization. This thesis is concerned with the design of the Timing Generation Unit (TGU) in digital transmission system application. A digital Phase Locked Loop (PLL) is presented, which consists of external reference input, jitter reduction loop, and microprocessor-controlled PLL. We use PLL technique to improve timing impairments.In this thesis, the hardware of microprocessor-controlled PLL has been designed and implemented. The application of FPGA device and D/A converter is included. An algorithm for the microprocessor-controlled PLL subsystem is proposed. For future research, one has to implement the algorithm and verify the functions of the microprocessor- controlled PLL subsystem.

博士
國立成功大學
電機工程學系
105
Due to the prevalence of portable electronic products, lower power attracts more attention for circuit designs. However, as technology advances, an SOC design can contain more and more components, which lead to a higher power density. Hence, lower power becomes one of the most important issues in modern VLSI designs. Reducing power consumption not only can enhance battery life but also can avoid performance degradation induced by the overheating problem. There have been many lower power design techniques proposed to reduce system power consumption. Among these techniques, the multi-bit flip-flop and the power-gated are considered as the most effective approaches. Although these two methods both can reduce power consumption, they also increase implementation complexity of the physical design. For instance, we have to replace several single-bit flip-flops by a single multi-bit flip-flop when the multi-bit flip-flop technique is applied to a design. But the timing in an original layout may be affected if an improper set of single-bit flip-flops is selected or a new inserted multi-bit flip-flop is placed at improper location. This will result in performance degradation or even failure in the functionality. Besides, when a power-gated technique is applied to a design, it may cause severe rush current if the turned-on sequence of power switches or their timing are not properly controlled, and thus the reliability of a system is degraded and the response time is increased. This dissertation presents two design methodologies which respectively target on implementing multi-bit flip-flops and power-gated techniques in the physical design. Since both of two techniques may induce timing-related issues, our approaches show the methodologies to resolve these problems and make them feasible in real VLSI designs. The experimental results have demonstrated the efficiency and effectiveness of our approaches. For the multi-bit flip-flop technique, our algorithm can achieve power reduction and simultaneously minimize wirelength without violating timing constraint. For the power gated technique, the proposed methodology can avoid occurrence of large rush current; hence, the reliability of a design is maintained.

博士
國立交通大學
電子工程學系 電子研究所
103
Timing analysis and optimization are two crucial processes in the modern IC design flow. Timing analysis verifies the timing performance of a design by calculating the circuit delay, checking timing constraints, and identifying timing critical paths, while timing optimization achieves timing closure of a design through improving identified timing critical paths, determining operable clock frequencies, etc. However, with rapidly growing design complexities and increasing on-chip variations, timing analysis and optimization encounter new design challenges. To facilitate the computation, conventional timing analysis divides a design into sets of timing paths blocked by flip-flops and then performs delay calculation and timing verification on each timing path independently. For nanometer design, the independent analysis may generate over-optimistic results on consecutive critical paths (i.e., criticality-dependent paths). In addition, to guarantee the timing performance under worst-case conditions, conventional timing analysis applies different operating conditions on the launch and capture clock paths during delay calculation. Thus, the conventional analysis induces artificially pessimistic results on the common part of the launch and capture clock paths (i.e., common path pessimism). On the other hand, for timing optimization, hold time fixing is an essential step for achieving timing closure in the design flow. Nevertheless, this task becomes much severer in timing error resilient circuits for high performance design, which eliminate a conservative timing guardband by error detection and correction. In this dissertation, we propose novel solutions to overcome these challenges. For eliminating the over-optimism on the criticality-dependent paths, in this dissertation, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a criticality-dependency-aware static timing analysis flow, which is seamlessly integrated with the common timing analysis flow. For removing the common path pessimism on clock paths, instead of exhaustive exploration on all paths in a design, we propose a timing analysis framework considering common path pessimism removal based on block-based static timing analysis and branch-and-bound. Along with the branch-and-bound mechanism, we further propose timing graph reduction, dynamic bounding and parallel computing to speed up the path retrieval. On the other hand, we develop a hold time fixing (shortest path padding) framework to enable the timing error detection and correction mechanism of resilient circuits. To shorten the resilient circuit design process, we first propose a feasibility checking criterion to determine the target clock period. Unlike greedy heuristics with a local view adopted by recent prior work, we determine the padding values and locations with a global view. Moreover, we utilize spare cells, offering the amount of discrete delay, and the dummy metal, offering an abundant and tunable resource of capacitance, to achieve the derived padding values at the post-layout stage.

隨著半導體工藝技術的不斷進步 (technology scaling) ，更多的設計資源不得不用於確保集成電路的時序正確性。這種“面向最壞情況(worstcase-oriented) 的芯片設計方法導致了悲觀保守的芯片設計方案，增加了性能及功耗開銷，減少了工藝進步帶來的效益。
“優於最壞情況(better-than-worst-case) 的芯片設計方法允許犧牲一定的芯片可靠性 (reliability) 來提高性能以及降低功耗，從而提高計算的能量效率 (energy efficiency) 。“優於最壞情況設計方法的核心思想在於放松對芯片可靠性的硬性需求。既然時序錯誤 (timing error) 在關鍵路徑中的發生頻率並不高，我們可以允許錯誤發生，從而節約用於防止錯誤發生所需要的高額開銷。而當錯誤發生時，再利用錯誤檢測和更正方法(error detection and correction) 來消除錯誤造成的影響。這種無須保證計算過程永遠正確無誤的方法通常被稱作“ 時序推測 (timing speculation) 。然而，不幸的是，由於傳統的“面向最壞情況的設計方法往往導致芯片中存在所謂的“關鍵路徑壁壘(wall of critical paths) ，時序推測技術的有效性在一定程度上受限。
為了解決上述問題，我們首先研究了時序推測技術的前提與前景，也就是研究了如何估計時序推測技術能夠帶來的最小和最大效益。此外，我們也研究了時序推測芯片 (timing-speculative circuit) 中的若幹設計優化問題。首先，由於引入時序推測技術能夠提高多電壓 (multi-supply voltage)技術的靈活性，我們闡述了時序推測芯片中的多電壓設計問題，並創造性地提出了一種基於動態規劃 (dynamic programming) 的算法來解決這個問題。此外，我們提出了時序推測芯片中的時鐘差異規劃 (clock skew scheduling) 問題。在考慮了時序錯誤率 (timing error rate) 等因素的影響後，我們設計了新穎有效的方法來解決該問題。最後，鑒於工藝差異(process variation) 和老化效應 (wearout effect) 對芯片時序的影響，而且這種影響很難在設計階段被消除，我們提出了一種實時的時序差異調整(clock skew tuning) 架構。利用精心設計的硬件結構，我們可以實時地收集時序錯誤的信息，相應地調整時鐘差異，從而極大地減弱了時序不確定性對芯片性能的影響。
As circuit non-idealities inevitably worsen with technology scaling, more design resource has to be incorporated to ensure integrated circuit (IC) timing correctness. Such worst-case-oriented design methodology results in pessimistic designs with considerable power and performance overheads, lessening the benefits provided by technology scaling.
Better-than-worst-case (BTWC) design methodology that allows reliability to be traded off against power and performance was proposed to dramatically improve the computation energy-efficiency. The basic idea behind BTWC design methodology is that, since circuit non-idealities mainly manifest themselves as infrequent timing errors on critical paths of the circuit, we can over-clock operating frequency and/or over-scale supply voltage of the chip to a critical point, where timing errors occur, and achieve error-resilient computations by performing timing error detection and correction. This approach is generally referred to as timing speculation, with which it is not necessary to guarantee “always correct operations. Unfortunately, there is usually a “wall of critical paths in the final implementation of a circuit caused by conventional worst-case-oriented design methodology, suggesting that, given a fixed circuit design, the effectiveness of timing speculation is limited by a fixed threshold beyond which the circuit performance/energy efficiency will drop significantly.
To address the above problem, this thesis first proposes to study the premises and prospects of timing speculation by analyzing the minimum and maximum potential benefits that are achievable by timing speculation techniques. After answering the question posed by the conflict between conventional techniques and timing speculation, this thesis investigates multiple design and optimization problems in timing-speculative circuits. Firstly, as introducing timing speculation capability into circuits can naturally extend the flexibility of multi-supply voltage (MSV) designs to a new horizon, this thesis formulates the MSV design problem for timing-speculative circuits and develops a novel algorithm based on dynamic programming to solve it. Secondly, this thesis develops a general formulation of clock skew scheduling (CSS) problem for timing-speculative circuits, wherein timing error rate and its corresponding impact are explicitly considered, and proposes novel algorithms to tackle this problem. Finally, considering the impact of timing uncertainties caused by process variation and wearout effects, which is very difficult to be modeled and addressed at design stage, this thesis also develops a novel online clock skew tuning framework for timing-speculative circuits. By utilizing an elaborately-designed hardware architecture to collect timing error information and tune clock skews at runtime, variation effects can be effectively mitigated.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Ye, Rong.
Thesis (Ph.D.) Chinese University of Hong Kong, 2014.
Includes bibliographical references (leaves 131-142).
Abstracts also in Chinese.

碩士
實踐大學
工業產品設計學系碩士班
104
In both fields of science and humanities, “time” is a mysterious subject that has been continuously investigated. In order to survive in modern society, we are asked to be efficient and competitive, and such a dynamic generates modern plagues such as insomnia, melancholia, and generalized anxiety disorder (GAD). Therefore, knowing how to relax and release the stress became a primordial aspect of modern life. Time is an axis filled with our feelings, memories and dreams. Time is an essential part of human sensibility, and it is therefore not surprising that it is the driving force behind many of our projects, through the entire spectrum of our means of expression. This study focuses on time, and its spirit, in order to discover how its emotional aspects can be applied on product design. We will first see in this study how time is perceived by science, as well as ordinary people and pop culture. We will further explain how time is a semiotic object, that is, a means to transmit information. We will also analyze how the modern product design process can be seen as a metaphor of time. All the elements above, once combined, will help us define the relationship between time and product design. Products presented in this study have been part of exhibitions and competitions, in order to get the necessary feedback from the user’s emotional and functional experience.

碩士
國立雲林科技大學
電機工程系
103
The design of the timing generator plays a very important role in the automatic test equipment (ATE). The timing generator requires a higher operating speed and precise timing trigger signal. In this thesis, a new architecture of the timing generator which contains coarse and fine stages and divider is proposed to provide the dynamic switching so as to choose the arbitrary timing output. With the aid of delay-locked loop (DLL) the closed-loop control of precise timing is achieved. In the thesis, the fundamental structure of the automatic test equipment is introduced at first. Then, the basic architecture and operating principles of delay-locked loop is explained. The design of the coarse and fine stages of timing generators are also described. Finally, the new architecture of the overall timing generator is proposed. The circuit design utilized 0.18μm process to validate its functionality.

碩士
國立東華大學
電機工程學系
104
As the feature size of chips shrinks with advance of semiconductor technology, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by variation of process, supply voltage, temperature (PVT). Furthermore, device aging can also cause timing errors. With such problems, conventional worst-case designs suffer poor system performance. When timing errors happen, the computing result from the integrated circuit is incorrect. Although we can employ worst-case frequency for insuring correctness, the performance is sacrificed significantly. Hence, design of timing-error-resilient VLSI circuit with aggressive design approach is more and more important. This thesis proposes a technique for aggressive VLSI design of timing-error resilient sorting hardware, which has an error detection and fault tolerance function. Even if the circuit timing errors occur, the design can still operate and produce the correct output. Although this design is at the expense of a small amount of chip area cost and power consumption, it can achieve reliability for the circuit, while keeps high performance. We have applied the technique to three sorting algorithms, including Bubble Sort, Odd-Even Sort, and Bitonic Sort. Two versions of the sorting hardware are implemented for the three sorters for comparison: one is original sorting hardware and the other is with timing-error-tolerant capability. The implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.

碩士
國立雲林科技大學
電機工程系
105
The market demand for automatic test equipment (ATE) requires a higher data transfer rate and precision timing to control the device under test (DUT) and test equipment for the test data comparison. The most basic function of ATE is able to complete the digital data transmission correctly. Common logic/functional tests are related to time delay adjustments and must be able to produce corresponding clock signals, including programmable delay, timeset memory and associated circuit to produce the desired timing. This thesis is dedicated to the design of the timing generator that can be applied in ATE. This thesis first introduces the basic architecture of ATE and the required data formats. Then, the structure of the timing generator is mainly divided into four parts: the timeset memory, the coarse timing generator, the counter and the fine timing generator. The coarse timing generator utilizes delay-locked loop (DLL) to realize the instantaneous switching function which set by the time data from the memory to select output timing. The fine timing generator is designed with an open-loop style which takes the advantage of the look-up table to achieve a very precise resolution. The proposed timing generator is designed and implemented in TSMC CMOS 0.18μm 1P6M process. The input operating frequency range of DLL is 0.9G ~ 1.2GHz. And the output frequency range of the timing generator is 1.76M ~ 600MHz. After normalization, the fine resolution can achieve 2ps.

碩士
國立東華大學
資訊工程學系
104
Due to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting worse and worse. One of the challenges we are faced with is timing errors of the circuits. Timing errors may happen when transmitted data arrive later than the timing clock or simply has not enough setup time. With VLSI circuit in advanced manufacturing process, timing errors either result in reduced operational reliability of circuits, or we have to tolerate the much slower clock pessimistically. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is even more important for advanced microprocessors in modern technology for many applications in recently years. 　　This master thesis employs timing-error-tolerant circuits in our designed 5-stage pipelined microprocessor with a 32-bit reduced MIPS instruction set. We implement our design using the cell-based IC design flow with Verilog hardware description language. We have run extensive simulation to validate the timing-error-tolerant capability. We then use logic synthesis to generate the circuit, and static timing analysis to verify that the timing delay meets our goal. The final step is to do automatic place and route, physical verification. We measure the cost we have to pay for the timing-error-tolerant capability. It is shown that our design can improve test coverage of the microprocessor with a reasonable cost.

碩士
國立東華大學
電子工程研究所
98
With the rapid progress of semiconductor process in recent years, we have been able to put more than hundreds of millions transistors into a single chip. The circuit characteristics in a large-scale chip have therefore changed significantly, while the transistor count and clock frequency of the chip keep increasing. As the transistors size and working voltage are getting smaller and lower, the connection design between IP blocks within the chip has become increasingly complex. On such advanced chip, signal transmission is no longer as stable and reliable as before. Since the signal is more susceptible to wire delay, noise, soft error, and synchronization, these factors affects the occurrence of timing errors. This thesis describes a timing-error-tolerant design of pipeline circuits. In such architecture, the pipeline stage buffer is replaced with a new design circuit to support timing error resilience. The organization of the circuit tolerates the timing errors with the ability to detect and correct such problems in the pipeline. We have applied the technique to systolic arrays. Two systolic architectures for matrix multiplication are designed with our proposed techniques, including linear and hexagonal systolic arrays. We use hardware description language to design and simulate them, and verify the timing error tolerance of the circuits. Furthermore, the circuit synthesis and physical design tools are also employed to realize our design. The results show that in order to achieve timing error resilience, we need to pay a portion for circuit speed and chip area. However, with the data width increasing, such overhead decreases and can be hidden and negligible for designs with high data width.

碩士
國立東華大學
電子工程研究所
98
With the rapid and sophisticated development of semiconductor manufacturing, designing chips has become increasingly challenging. Chip designers are now faced with much more complicated nanometer-based circuits with not only finer manufacturing process but also higher possibilities of unexpected variations caused by the leakage of current. There are many potential problems to be addressed on this issue, such as crosstalk, delay defects, and the sensitivity of noise. In addition, the stability of temperature and voltage of the circuit also affects the reliability of signals. Factors such as timing errors or soft errors can cause circuit failures. The need to avoid these problems and to enhance the circuit reliability starting from the designing stage is very important. When an error occurs, the speed and accuracy of error detection and data recovery are critical issues on designing reliable circuits. This thesis investigates the timing-error-resilient structure on synchronous digital systems design. The focus is on how to use delays to detect and correct the signal errors. Two possibilities for timing-error-resilient structures will be studied: one is automatic error-free design, and the other is elastic datapath design. Experiments are performed to validate our ideas through logic simulation, synthesis, and physical layout.

碩士
國立清華大學
通訊工程研究所
93
Abstract Orthogonal frequency division multiplexing (OFDM) differs greatly from the traditional single carrier communication system. It is a multicarrier system with parallel transmission scheme by using a special set of orthogonal carrier frequencies. The advantages of OFDM include that Intersymbol Interference (ISI) becomes small relatively, bigger transmission rate of data, better spectral efficiency, and easy implementation by Fast Fourier Transform (FFT), etc. Therefore, OFDM becomes the main stream of the wireless communication. The WiMAX (IEEE802.16-2004) published in 2004 is an OFDM system. However, the performance of OFDM system will be reduced seriously by the carrier frequency offset and the timing offset. In other words, the advantages of OFDM only base on the well synchronization schemes. In this thesis, we will focus on the timing synchronization algorithm design which includes symbol timing synchronization and sampling frequency synchronization. The simulation result shows that our proposed algorithm has better performance and is suitable for OFDM based systems. Our proposed algorithm also provides low complexity for hardware implementation.

碩士
國立清華大學
資訊工程學系
86
In this paper, we present an RTL time-budgeting method for early design planning. We formulate the RTL time-budgeting method into a slack distribution problem. We present three algorithms, namely the Lagrange-Multipliers-based algorithm, the balanced slack distribution algorithm, and the AT-based slack distribution algorithm. We propose an integrated RTL/logic-synthesis and physical-synthesis design flow to exploit the RTL time-budgeting problem. Experimental results have demonstrated that our proposed algorithms can effectively provide timing budgets at RTL.

隨著工藝尺寸的縮小，集成電路的時序行為變得越來越難以預測，某原因在於各種偏差效應，比如製造偏差、供電電壓波動以及溫度變化。對於傳統的“確保正確“的設計方式，我們需要留出很大的餘量，這就減少了工藝進步帶來的好處。時序監測C Timing Speculation) 因為具有錯誤檢測和更正機制而成為一種很有前景的解決辦法。採用這種方式，電路可以工作在有不太頻繁時序錯誤的情況下。而對於這種時序監視的設計方式，現有的優化方法大多主要是在電路結構確定之後的一些小的改動。因為這些方法無法對電路結構進行改變，所以它們的效果很有限。因此，我們在這篇論文里提出了在電路綜合(synthesis)過程中的一些優化方法，這些方法是能夠改變電路結構的。我們提出的優化方法主要集中在優化電路的硬件開銷和電路性能的方面。我們提出的方法主要包括兩個設計階段。
第一個階段是在邏輯綜合(Logic synthesis) 的時候.在邏輯綜合的時候，我們有很大的自由度去根據時序監測的特性來改變電路的結構。如果結合了特殊的實現方法，電路出現時序錯誤的頻率就會得到降低，從而提高了電路的性能。
第二個階段是在邏輯綜合之後的后綜合(Post-synthesis) 階段。為了減少時序監測的硬件上的開銷，我們提出了基於retiming 手法的再綜合(resynthesis) 方法.這種方法可以減少可疑寄存器(suspicious FF) 的數量從而降低硬件開銷。另外這種辦法也可以提高電路的吞吐量(throughput) 。為了進一步對電路進行優化，我們挨著又提出了基於rewiring 手法的電路吞吐量優化方法。此外，利用這種方法我們還可以消除部份電路里的短通路(short path) 從而進一步減少電路的硬件開銷。在這個階段，我們仍然具有改變電路結構的靈活性，因此我們的方法具有很好的效果。
With technology scaling, the timing behavior of integrated circuits (ICs) becomes more unpredictable due to various variation effects, such as manufacturing variability, voltage fluctuations and temperature changes. A large design guard band is therefore reserved to ensure “always correct“ operation for traditional designs, disminishing the benefits of technology scaling. Timing speculation with error detection and correction mechanisms is a promising solution to tackle the above problem. With this technique, circuit can work under infrequent timing errors. The existing optimization techniques for timing speculated circuits are mainly based on some small modifications after the circuit structure is determined. Without the ability to change circuit structure, the efficiency is limited. Therefore, in this thesis we propose optimization techniques during the process of synthesis so that the flexibility is provided to make circuit structural change. Our optimization fo¬cuses on hardware cost and circuit performance and the proposed techniques are included in two design steps.
First step is logic synthesis. During the process of logic synthesis, there is large flexibility to change the circuit structure by considering the features of timing speculation. With intentional strategy the timing error probability can be reduced so as to improve the circuit throughput.
Second step is post-synthesis techniques after logic synthesis. To reduce the hardware cost for timing speculation, we propose a re-synthesis method based on the idea of retiming to reduce the number of suspicious FFs where timing errors mainly happen. This technique can also help to improve the circuit throughput if carefully implemented. To further improve the throughput, we also propose to use rewiring technique which is also called redundancy addition and removal (RAR) to optimize circuit for throughput. Furthermore, this technique can also be used to break down short paths so as to save the hardware cost. During this step, flexibility is also provided to make circuit structural change so that the efficiency is guaranteed.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Liu, Yuxi.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 70-76).
Abstracts also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Timing Speculation --- p.1
Chapter 1.1.1 --- Circuit Timing Problem --- p.1
Chapter 1.1.2 --- Possible Solution --- p.3
Chapter 1.1.3 --- Timing Speculation is Promising --- p.4
Chapter 1.1.4 --- Razor Flip-flop --- p.5
Chapter 1.2 --- Problems for Timing Speculation --- p.6
Chapter 1.2.1 --- Hardware Cost of Timing Speculation --- p.7
Chapter 1.2.2 --- Performance of Timing Speculation --- p.8
Chapter 1.3 --- Thesis Motivation and Organization --- p.9
Chapter 1.4 --- Thesis Contributions --- p.11
Chapter 2 --- Logic Synthesis for Timing Speculation --- p.13
Chapter 2.1 --- Introduction --- p.13
Chapter 2.2 --- Preliminaries --- p.14
Chapter 2.2.1 --- Timing Speculation --- p.14
Chapter 2.2.2 --- AIG-Based Logic Synthesis --- p.15
Chapter 2.3 --- Logic Synthesis for Timing Speculation --- p.16
Chapter 2.3.1 --- Proposed Optimization Metric --- p.17
Chapter 2.3.2 --- Proposed Logic Synthesis Solution --- p.19
Chapter 2.4 --- Experimental Results --- p.24
Chapter 2.4.1 --- Experimental Setup --- p.24
Chapter 2.4.2 --- Results and Discussion --- p.25
Chapter 2.5 --- Conclusion --- p.30
Chapter 3 --- Post-Synthesis Optimization for Timing Speculation --- p.31
Chapter 3.1 --- Optimization for Timing Speculation by Retiming --- p.32
Chapter 3.1.1 --- Introduction --- p.32
Chapter 3.1.2 --- Preliminaries and Motivation --- p.33
Chapter 3.1.3 --- Reducing Suspicious FFs by Retiming --- p.35
Chapter 3.1.4 --- Reducing Timing Error Probability by Retiming --- p.41
Chapter 3.1.5 --- Padding Short Paths --- p.43
Chapter 3.2 --- Optimization for Timing Speculation by Rewiring --- p.47
Chapter 3.2.1 --- Introduction --- p.47
Chapter 3.2.2 --- Preliminaries --- p.48
Chapter 3.2.3 --- Timing Optimization by Rewiring --- p.52
Chapter 3.2.4 --- Reduce Hardware Cost by Rewiring --- p.60
Chapter 3.3 --- Experimental Results --- p.62
Chapter 3.4 --- Conclusion --- p.66
Chapter 4 --- Conclusion --- p.68
Bibliography --- p.76

碩士
國立東華大學
電子工程研究所
96
Abstract Owing to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting more and more severe. One of the challenges we are faced with is timing errors. As the clock rate is higher, the probability of timing errors gets higher too. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is more important when the system-on-chip era has become practical for many applications. This thesis proposes a new error resilient design for pipelined VLSI circuits to tolerate timing errors. In our design, a technique is presented to detect and correct the timing errors. Basically, we modify the pipeline buffer by adding appropriate control circuits to adjust to the timing error event. We have validated our idea by applying our technique to two example digital signal processing designs: an FIR filter and an IIR filter. We have simulated the two designs and implemented them with cell-based design flow. The results show that our designs add nearly no delay at a reasonable area cost.

碩士
國立清華大學
電機工程學系
93
Recently embedded memories are the most widely used cores in system-on-chip (SOC). They often occupy most of the chip area and dominate the overall yield of the chip. For the sake of improving the manufacturing yield of the chip, memory Built-In Self-Repair (BISR) has become essential. Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of an address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves a significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. During memory access, read operations to the main memory and spare memory are executed in parallel. However, the write operation to spare memory is divided into two steps. Data is first written into the write buffer, then into the spare memory when the next write operation arrives. Therefore, there is one clock cycle to compare the access address with the address stored in the repair registers. With the proposed address remapping scheme and the redundancy architecture, the timing penalty of our BISR scheme is the same with that of Built-In Self-Test (BIST) circuit — only one multiplexer delay for both the inputs and outputs.

碩士
國立臺北科技大學
機電整合研究所
100
The variable valve timing mechanism in this research includes: an outer case, a locking device, a roller, a returning device and hydraulic circuits. The innovations of the new design are: using single design to satisfy the practical needs of flow intake and outlet and using a returning spring to counterbalance the moment of camshaft resistant force to bring torque reduce the working pressure of hydraulic system. Comparing with the previous designs, the new design possesses following merits: lower the manufacturing and assembling costs and reduce the working oil pressure to save energy. This research collected, classified, and analyzed existing patents. This research developed reference orientations according to the functional patterns and structures of the collected patents. Proper mechanism was chosen according to the above information. Method of dimensional synthesis was used. Performance requirements and design specifications were developed. 3D CAD software was used to construct 3D model and to analyze the working conditions. and Interference check were done. A stable and practical variable valve timing mechanism was developed and booked for new patent.

碩士
國立臺北科技大學
機電整合研究所
95
The main research of the thesis is based on the cell-based digital IC design flow, By using the TSMC 2P4M cell library, we design a TFT LCD timing control IC , that is used to analyze the mathematical model of the color space conversion . Note that the proposed conversion can meet both video format and transmission standards. After the Gamma correction has been completed, we can obtain a variety of Gray level through the color space converter theorem. In this paper, the Verilog HDL is used to design the ASIC. First of all, the Verilog code has been verified with ModelSim software and FPGA hardware. After both the processes of RTL simulation and the Gate level simulation have been made, the designed code will be transferred into ASIC. The proposed control architecture contributes to the advancement of the digital control performance and the realization of control algorithm.

由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。
為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。
With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience.
To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Yuan, Feng.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 88-100).
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2
Chapter 1.2 --- Contributions and Thesis Outline --- p.5
Chapter 2 --- Background --- p.7
Chapter 2.1 --- Sources of Timing Uncertainty --- p.7
Chapter 2.1.1 --- Process Variation --- p.7
Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9
Chapter 2.1.3 --- Aging Effect --- p.10
Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10
Chapter 2.3 --- False Path --- p.12
Chapter 2.3.1 --- Path Sensitization Criteria --- p.12
Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13
Chapter 2.4 --- Manufacturing Testing --- p.14
Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14
Chapter 2.4.2 --- Scan-Based DfT --- p.15
Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17
Chapter 2.5 --- Timing Error Tolerance --- p.19
Chapter 2.5.1 --- Timing Error Detection --- p.19
Chapter 2.5.2 --- Timing Error Recover --- p.20
Chapter 3 --- Timing-Independent False Path Identification --- p.23
Chapter 3.1 --- Introduction --- p.23
Chapter 3.2 --- Preliminaries and Motivation --- p.26
Chapter 3.2.1 --- Motivation --- p.27
Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28
Chapter 3.3.1 --- Path Sensitization Criterion --- p.28
Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30
Chapter 3.3.3 --- Proposed Examination Procedure --- p.31
Chapter 3.4 --- False Path Identification --- p.32
Chapter 3.4.1 --- Overall Flow --- p.34
Chapter 3.4.2 --- Static Implication Learning --- p.35
Chapter 3.4.3 --- Suspicious Node Extraction --- p.36
Chapter 3.4.4 --- S-Frontier Propagation --- p.37
Chapter 3.5 --- Experimental Results --- p.38
Chapter 3.6 --- Conclusion and Future Work --- p.42
Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43
Chapter 4.1 --- Introduction --- p.43
Chapter 4.2 --- Preliminaries and Motivation --- p.45
Chapter 4.2.1 --- Motivation --- p.46
Chapter 4.3 --- Proposed Methodology --- p.48
Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50
Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51
Chapter 4.5 --- Experimental Results --- p.59
Chapter 4.5.1 --- Experimental Setup --- p.59
Chapter 4.5.2 --- Results and Discussion --- p.60
Chapter 4.6 --- Conclusion --- p.64
Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65
Chapter 5.1 --- Introduction --- p.65
Chapter 5.2 --- Prior Work and Motivation --- p.67
Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69
Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70
Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72
Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75
Chapter 5.4.1 --- Overall Flow --- p.76
Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77
Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79
Chapter 5.5 --- Experimental Results --- p.81
Chapter 5.5.1 --- Experimental Setup --- p.81
Chapter 5.5.2 --- Results and Discussion --- p.82
Chapter 5.6 --- Conclusion --- p.85
Chapter 6 --- Conclusion and Future Work --- p.86
Bibliography --- p.100

System on chip design steadily evolves toward different non-overlapping abstraction levels. Very different competence and design tools will be needed at each level. One specific level of abstraction will deal with interconnect technologies, with a pronounced trend towards networks on chip. It is projected that, within five years, the large majority of end-user SoC products will consist of heterogeneous embedded processors, built on multi-processor SoC platforms (MP-SoC). There is a tremendous amount of research required to characterize the various topologies and their effectiveness for different application domains. A common issue with all network-on-chip topologies is communication latency. Due to the increase of global wire delay with technology scaling, pipelining is required to hide the latency associated with the exchange of data across the chip. The building blocks of a network-on-chip are intelligent switches, which provide a data transport mechanism across the chip. Their design is critical due to different architectural and circuit level trade-offs. This work is novel in that it addresses the issues of quantifying the delay of different pipeline stages in an on-chip topology, and evaluates the effectiveness of a given topology in forthcoming technology nodes.

碩士
中原大學
資訊工程研究所
91
As the process technology enters the deep sub-micron era, the side-effect is become more and more serious. The number of components in VLSI design is over the handing of current commercial tool and the circuit connection deep influence the chip performance. Now, routing problem not only consider routability but also timing convergence and reduce noise. This paper propose a timing driven multilevel routing method. We consider critical path give priority to route and use multilevel framework to route rest net by congestion driven global route and timing driven detailed route. The different with post multilevel routing is our multilevel routing only adopt coarsen stage. We use coarsen stage to reduce our routing search time and we process fail net in coarsen stage instead of uncoarsen stage. When we route critical path, we use elmore delay model as guide to reduce the timing delay at critical path. Experimental results show that our timing delay which adopt timing driven improve form 20% to 80% than normal multilevel routing. The results prove that we consider critical path can reduce the timing delay obviously. Our routability is over 99% in these test cases which row utilization is about 50%. In the experimental flow, we use the real circuit case as our input, and integrate with commercial CAD design flow.

The multi-net Global Routing Problem (GRP) in VLSI physical design is a problem of routing a set of nets subject to limited resources and delay constraints. Various state-of-the-art routers are available but their main focus is to optimize the wire length and minimize the over ow. However optimizing wire length do not necessarily meet timing constraints at the sink nodes. Also, in modern nano-meter scale VLSI process the consideration of process variations is a necessity for ensuring reasonable yield at the fab. In this work, we try to nd a fundamental strategy to address the timing-driven Steiner tree construction (i.e., the routing) problem subject to congestion constraints and process variation. For congestion mitigation, a gradient based concurrent approach (over all nets) of Erzin et. al., rather than the traditional (sequential) rip-and-reroute is adopted in or- der to propagate the timing/delay-driven property of the Steiner tree candidates. The existing sequential rip-up and reroute methods meet the over ow constraint locally but cannot propagate the timing constraint which is non-local in nature. We build on this approach to accommodate the variation-aware statistical delay/timing requirements. To further reduce the congestion, the cost function of the tree generation method is updated by adding history based congestion penalty to the base cost (delay). Iterative use of the timing-driven Steiner tree construction method and history based tree construction procedure generate a diverse pool of candidate Steiner trees for each net. The gradient algorithm picks one tree for each net from the pool of trees such that congestion is e ciently controlled. As the technology scales down, process variation makes process dependent param- eters like resistance, capacitance etc non-deterministic. As a result, Statistical Static Timing Analysis or SSTA has replaced the traditional static timing in nano-meter scale VLSI processes. However, this poses a challenge regarding the max/min-plus algebra of Dijkstra like approximation algorithm that builds the Steiner trees. A new approach based on distance between distributions for nding maximum/minimum at the nodes is presented in this thesis. Under this metric, the approximation algorithm for variation aware timing driven congestion constrained routing is shown to be provably tight and one order of magnitude faster than existing approaches (which are not tight) such as the MVERT. The results (mean value) of our variation aware router are quite close to the mean of the several thousand Monte Carlo simulations of the deterministic router, i.e the results converge in mean. Therefore, instead of running so many deterministic Monte Carlo simulations, we can generate an average design with a probability distribution reasonably close to that of the actual behaviour of the design by running the proposed statistical router only once and at a small fraction of the computational e ort involved in physical design in the nano regime VLSI. The above approximation algorithm is extended to local routing, especially non- Manhattan lambda routing which is increasingly being allowed by the recent VLSI tech- nology nodes. Here also, we can meet delay driven constraints better and keep related wire lengths reasonable.