Dissertations / Theses on the topic 'Design pattern detection'

Design pattern detection is useful for a range of software comprehension and maintenance tasks. Tools that rely on static or dynamic analysis alone can produce inaccurate results, especially for patterns that rely on the run-time information. Some tools provide facilities for the developer to refine the results by adding their own knowledge. Currently, however, the ability of tools to accommodate this knowledge is very limited; it can only pertain to the detected patterns and cannot provide additional knowledge about the source code, or about its behaviour. In this thesis, we propose an approach to combine existing pattern detection techniques with a structured feedback mechanism. This enables the developer to refine the detection results by feeding-in additional knowledge about pattern implementations and software behaviour. The motivation is that a limited amount of user input can complement the automated detection process, to produce results that are more accurate. To evaluate the approach we applied it to a selection of openly available software systems. The evaluation was carried in two parts. First, an evaluation case study was carried out to detect pattern instances in the selected systems with the help of the user knowledge. Second, a user study of a broader range of expert users of design patterns was conducted in order to investigate the impact of their knowledge on the detection process, and to see whether it is realistic that the user can identify useful knowledge for the detection process. The evaluation results indicate that the proposed approach can yield a significant improvement in the accuracy whilst requiring a relatively small degree of user input from the developer. Moreover, the results show that expert users can supplement the design pattern detection process with a useful feedback that can enhance the detection of design pattern instances in the source code.

The main objective of design pattern detection is to gain better comprehension of a software system, and of the kind of problems addressed during the development of the system itself. Design patterns have informal specifications, leading to many implementation variants caused by the subjective interpretation of the pattern by developers. This thesis applies a supervised classification approach to make the detection more subjective, bringing to developers the patterns they want to find, ranked by a confidence value.

Automated fault diagnosis in induction machines is a difficult task and normally requires background information of electrical machines. Here a different methodology to the condition monitoring problem is devised. The approach is based entirely on Digital Signal Processing (DSP) and Statistical Pattern Recognition (PR). Description of machine conditions is extracted from empirical data. The main tasks that must be carried out by a PR-based condition monitoring system are: condition identification, knowledge reinforcement and knowledge creation for previously unseen conditions. The DSP operations are employed to quickly isolate sensor faults and to remove noise using data acquired from a single channel. DSP transformations may seem promising in making the monitoring system portable. Most importantly, they can compensate for operational changes in the machine. These changes affect the supply line currents and the primary signal quantities to be measured, i.e. the current and the axial leakage flux. The data which is input to the statistical monitoring system may be transformed, in the form of features, or remain unaltered. The system exploits the statistical properties of the feature vectors. The particular features, namely the LAR coefficients, convey short-term, high-resolution spectral information. For a long record, the feature vector sequence may provide information about changes in the record spectral characteristics, with time. Many induction machine processes are stationary and they can be properly be dealt with by a simple statistical classifier, e.g. a Gaussian model. For nonstationary processes, the system may employ a more comprehensive tool, namely the Hidden Markov Model. which may track the changing behaviour of the process in question. Initially a limited number of machine conditions are available to the process engineer. By identifying their boundaries, new faulty conditions could be signalled for and adopted into the database.

Sewer and oil pipeline spillage issues have become major causes of pollution in urban and rural areas usually caused by blockages in the water storage and drainage system, and oil spillage of underground oil pipelines. An effective way of avoiding this problem will be by deploying some mechanism to monitor these installations at each point in time and reporting unusual liquid activity to the relevant authorities for prompt action to avoid a flooding or spillage occurrence. This research work presents a low cost energy efficient liquid level monitoring technique using Radio Frequency Identification Technology. Passive UHF RFID tags have been designed, modelled and optimized. A simple rectangular tag, the P-shaped tag and S-shaped tag with UHF band frequency of operation (850-950 MHz) has been designed and modelled. Detailed parametric analysis of the rectangular tag is made and the optimised design results analysed and presented in HFSS and Matlab. The optimised rectangular tag designs are then deployed as level sensors in a gully pot. Identical tags were deployed to detect 4 distinct levels in alternate positions and a few inches in seperation distance within the gully pot height (Low, Mid, High and Ultra high). The radiation characteristic of tag sensors in deployment as modelled on HFSS is observed to show consistent performance with application requirements. An in-manhole chamber antenna for an underground communication system is analysed, designed, deployed and measured. The antenna covers dual-band impedance bandwidths (i.e. 824 to 960 MHz, and 1710 to 2170 MHz). The results show that the antenna prototype exhibits sufficient impedance bandwidth, suitable radiation characteristics, and adequate gains for the required underground wireless sensor applications. Finally, a Linearly Shifted Quadrifilar Helical Antenna (LSQHA) designed using Genetic Algorithm optimisation technique for adoption as an RFID reader antenna is proposed and investigated. The new antenna confirms coverage of the RFID bandwidth 860-960 MHz with acceptable power gain of 13.1 dBi.

In this thesis the study of different innovative antenna systems is presented. The antenna designs that have been analyzed and that are described in this thesis can be divided in three main groups based on their application: phased-array antennas working on surfaces that change shape in time, millimeter-wave antennas for skin cancer diagnosis, and gaseous plasma antennas for satellite communications. As far as the first topic is concerned, the research activity presented in this thesis focuses on the study of the strengths and limitations of a specific pattern recovery technique: the projection method. This technique has been adopted to retrieve the radiation properties of linear and planar arrays placed on surfaces whose shape changes in time according to different geometrical deformation; moreover, its effectiveness was assessed for both broadside and beam steering arrays, leading to a novel and simpler formulation of this pattern recovery technique for arrays whose beam is tilted towards different directions. The results have been obtained both through full-wave numerical simulations in CST Microwave Studio and through measurements performed in collaboration with the North Dakota State University (NDSU), Fargo, North Dakota, USA. Regarding skin cancer diagnosis, a novel substrate integrated waveguide probe for early-stage skin cancer detection has been designed as well: this probe is cheap and easy to fabricate and can achieve high accuracy in detecting small early-stage skin cancer, thus providing a tool with the potential of being adopted as a real aid for skin cancer diagnosis. The probe has been tested both through full-wave numerical simulations and through measurements on a skin phantom realized at The University of Queensland with the support of the Microwave Team. The study about gaseous plasma antennas for satellite communications has been mainly numerical. Different designs have been conceived with the aim of exploiting the advantages of using plasma elements while at the same time avoiding the limitations related to this novel technology. A practical implementation of these designs is now the subject of a collaboration with CISAS B. Colombo, an aerospace research center of the University of Padova.

One of the goals of Software Engineering is to reduce, or at least to try to control, the defectiveness of software systems during the development phase. Software engineers need to have empirical evidence that software metrics are related to software quality. Unfortunately, software quality is quite an elusive concept, software being an immaterial entity that cannot be physically measured in traditional ways. In general, software quality means many things. In software, the narowest sense of product quality is commonly recognized as absence or low incidence of bugs in the product. It is also the most basic meaning of confermance to requirements, because if the software contains too many functional defects, the basic requirement of providing the desired function is not met. To increase overall customer satisfaction as well as satisfaction toward various quality attributes, the quality attributes must be taken into account in the planning and design of software. To improve quality during development, we need models of the develompment process, and within the process we need to select and deploy specific methods and approaches, and employ proper tools and technologies. It is necessary to know measures of the characteristics and quality parameters of the development process and its stages, as well as metrics and models to help ensure that the development process is under control to meet the product’s quality objectives. Software quality metrics tend to measure whether software is well structured, not too simple and not too complex, with cohesive modules that minimize their coupling. Many quality metrics have been proposed for software, depending also on the paradigm and languages used there are metrics for structured programming, object-oriented programming, aspect-oriented programming, and so on. The use of traditional metrics as quality indicators is very dicult. The Lines of Code (LOC) metric (very related to faults), is dicult to use, you can not say to a team of developers to develop classes by imposing a predefined number of lines of code. The use of the micro patterns (introduced by Gil and Maman) metrics, that capture concepts of good or bad programming (like anti patterns) can help developers to focus on those classes that belong to categories of micro patterns prone to fault. The relationship between traditional metrics and micro patterns is useful for enabling these new metrics to evaluate software quality. Micro patterns are similar to design patterns, but their characteristic is that they can be identified automatically, and are at a lower level of abstraction with respect to design patterns. This thesis tackles the problem of measuring software quality in Object Oriented (OO) systems by using such novel approaches based on micro patterns that can be a useful metrics in order to measure the quality of software by showing that certain categories of micro patterns are more fault prone than others, and that the classes that do not correspond to any category of micro patterns are more likely to be faulty. Many empirical studies were performed to validate empirically CK suite under these two aspects, showing an acceptable correlation between CK metrics values and software fault-proneness and diculty of maintenance. In OO, micro patterns can help to identify the portions of code that should be improved (for example those where encapsulation is not respected), and highlight other portions that make up good design practices. The design patterns, defined in the early nineties were an important breakthrough at analysis and design level, but are dicult to be automatically supported at the coding level. There are tools claiming to help finding the usage of design patterns in code, but in practice they are used in a very limited way. On the contrary, micro patterns are defined at coding level, and it is relatively easy to recognize them automatically, thus being able to implement formal conditions on the structure of the class. Thesis overview The thesis is organized according to this scheme: • Chapter 2 provides an overview of the concept of software metrics; • Chapter 3 presents an overview of the design patterns catalogs; • Chapter 4 discusses the micro patterns catalog using the definitions made by Gil and Maman; • Chapter 5 discusses the interpretation of Micro Patterns given by Arcelli and Maggioni; • Chapter 6 present the study of the evolution of five particular micro patterns (anti patterns) in different releases of the Eclipse and NetBeans systems, and the correlations between anti patterns and faults. The analysis confirms previous findings regarding the high coverage of micro patterns onto the system classes, and show that anti patterns not only represent bad Object Oriented programming practices, but may also be associated to the production of worse quality software, since they present a significantly enhanced fault proneness. • Chapter 7 present a study that aims to show, through empirical studies of open source software systems, which categories of micro patterns are more correlated to faults. Gil and Maman demonstrated, and subsequent studies confirmed, that 75% of the classes of a software system are covered by micro patterns. In this chapter is also analyzed the relationship between faults and the remaining 25% of classes that do not match with any micro pattern. We found that these classes are more likely to be faultprone than the others. We also studied the correlation among all the micro patterns of the catalog, in order to verify the existence of relationships between them. • Chapter 8 present a study on micro patterns in different releases of two software systems developed with Object Oriented technologies and Agile process. In this chapter we present some empirical results on two case studies of systems devel- oped with Agile methodologies, and compare them to previous results obtained for non Agile systems. In particular we have verified that the distribution of micro patterns in a software system developed using Agile methodologies does not differ from the distribution studied in other systems, and that the micro patterns fault-proneness is about the same. We also analyzed how the distribution of micro patterns changes in different releases of the same software system. We demonstrate that there is a relationship between the number of faults and the classes that do not match with any micro patterns. We found that these classes are more likely to be fault-prone than the others even in software developed with Agile methodologies • Chapter 9 present the Java tool used in order to extract from the source code the informations about micro patterns distributions. • Chapter 10 discusses the related works in the field.

The objective of this research is to design and develop a reconfigurable string matching co-processor using field-programmable gate array (FPGA) technology that is capable of matching thousands of complex patterns at gigabit network rates for network intrusion detection systems (NIDS). The motivation for this work is to eliminate the most significant bottleneck in current NIDS software, which is the pattern matching process. The tasks involved with this research include designing efficient, high-performance hardware circuits for pattern matching and integrating the pattern matching co-processor with other NIDS components running on a network processor. The products of this work include a system to translate standard intrusion detection patterns to FPGA pattern matching circuits that support all the functionality required by modern NIDS. The system generates circuits efficient enough to enable the entire ruleset of a popular NIDS containing over 1,500 patterns and 17,000 characters to fit into a single low-end FPGA chip and process data at an input rate of over 800 Mb/s. The capacity and throughput both scale linearly, so larger and faster FPGA devices can be used to further increase performance. The FPGA co-processor allows the task of pattern matching to be completely offloaded from a NIDS, significantly improving the overall performance of the system.

Design patterns have a key role in software development process. They describe both structure and the behavior of classes and their relationships. Maintainers can benefit from knowing the design choices made during the implementation. This thesis presents a Multiple Level Detection Approach (MLDA) to recover design pattern instances from the Java source code. MLDA is able to recover design pattern instances based on a generated class-level representation of an investigated system. Specifically, MLDA presents what is the so-called Structural Search Model (SSM) which incrementally builds the structure of each design pattern based on the generated source code model. Moreover, MLDA uses a rule-based approach to match the method signatures of the candidate design instances to that of the subject system. As the experiment results illustrate, MLDA is able to recover 23 design patterns with a reasonable detection accuracy. Furthermore, this thesis presents a metrics-based approach to address the impact of design pattern instances on software understandability and maintainability. This approach classifies system classes into two groups: pattern classes and non-pattern classes. The experimental results show that pattern classes have better inheritance and size metrics than do nonpattern classes. Unfortunately, no safe conclusion can be drawn regarding the impact of design patterns on software understandability and maintainability, since non-pattern classes have better coupling and cohesion metrics than do pattern classes.

REST (REpresentational State Transfer) is commonly used for designing APIs. Two main categories of REST API quality have been identified in previous research: linguistic and design quality. Linguistic quality revolves around the design of the URIs. Design quality revolves around the metadata and body in HTTP requests and responses. For enabling and simplifying communications with REST, both linguistic and design quality are important, however, previous research has shown that even major APIs using REST are not always following best practices for linguistic and design quality. This study investigates if there is a statistical relation between linguistic and design quality. We selected 326 API endpoints from ten public APIs for this study. This study has reused and improved a Java-based tool in previous research for detecting aspects of linguistic quality in the APIs endpoints. For this study, we also developed a tool based on Node.js for detecting aspects of design quality in the API endpoints. These two tools are applied on the same API endpoints to be able to study the statistical relation. A Chi-Square test, implemented with R, showed that there is a significant statistical relation in our findings between linguistic and design quality. Pairwise phi-coefficient comparisons, implemented with Python, between each combination of the linguistic and design aspects used in this study identified eight weak and two moderate relations among the linguistic and design quality aspects. However, sample tests showed that the Java-based tool for detecting linguistic quality were not accurate, which made us fail to answer our problem formulation.

REST (Representational state transfer) is an architectural style for distributed hypermedia systems. The simplicity of REST allows straightforward communication between HTTP clients and servers using URIs (Uniform Resource Identifiers) and HTTP methods, e.g., GET, POST, PUT, and DELETE. To do the communication effectively between clients and servers, there is a set of best design practices (design and linguistic patterns) shall be followed, and a set of poor design practices (design and linguistic antipatterns) shall be avoided. This study aims to determine whether there is a relationship between design and linguistic quality in Google RESTful APIs. To find this relation, a tool is developed to detect patterns and antipatterns in REST APIs both in terms of design and linguistic quality. The input of this tool is qualitative data (Google APIs) and its output is quantitative data. Using this quantitative data, a statistical study is then performed to detect the relation. The tests that are conducted to obtain the final results are Chi-squared and Phi Coefficient tests. The result of Chi-squared that considered all the groups of patterns and antipatterns shows that there is a statistically significant relation between design and linguistic quality. However, when we assess the individual pair of patterns and antipatterns, our Phi Coefficient tests show that for most of the cases, there is no or negligible relationship between linguistic and design patterns and antipatterns.

Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent seulement quelques contres-exemples qui mettent en evidence l'erreur. Les concepteurs utilisent ces contre-exemples pour diagnostiquer manuellement leur conception. Le diagnostic manuel est un processus tres lent et tres couteux. Le temps de diagnostic peut etre egal, voire superieur, au temps de conception. Nous presentons dans cette these de nouveaux algorithmes pour la localisation et la correction automatique des erreurs simples de conception dans les circuits logiques sous l'hypothese d'une seule erreur. Les erreurs traitees ici sont : le remplacement d'un composant dans les circuits combinatoires et sequentiels, et une erreur de connexion dans les circuits combinatoires. Le modele d'une seule erreur exige une strategie de verification frequente, dans laquelle la conception est verifiee apres chaque modification, pour que la probabilite d'insertion de plus d'une erreur ne soit pas trop elevee. Notre approche consiste a simuler et analyser automatiquement le circuit sous l'application de vecteurs de test que nous produisons specialement pour accelerer le diagnostic. Nous avons realise deux logiciels prototypes bases sur ces algorithmes. Ccds est l'outil de diagnostic pour les circuits combinatoires, et scds est l'outil de diagnostic pour les circuits sequentiels. Ces outils sont actuellement integres dans l'environnement de preuves prevail#t#m.

Preclinical PET systems image animal models of chronic human disease that are used to evaluate new therapeutic strategies for the treatment of cancer and other diseases. Once these animals are out of a controlled environment for PET imaging, they typically can not be taken back as they may have been exposed to outside disease. A highly compact PET system is thus required to be developed that can operate within a bio-safety cabinet inside a barrier facility. We investigated using 100-mm-long LYSO scintillator crystals oriented in the axial direction and read out at both ends by position sensitive photomultiplier tubes (PSPMTs) to construct a compact PET. The optimization of light collection for axial encoding of events was carried out using different reflector materials and surface treatments of 3 × 2 × 100 mm3 and 2 × 2 × 100 mm3 polished crystals. The detector response was examined by irradiating the crystals at discrete positions using an electronically collimated 511 keV photon beam. The ratio of two PSPMT signals was used to find the axial-resolution while their sum was used to determine the energy resolution. We then explored the effects of creating systematic band patterns of surface roughing on 1 to 4 long surfaces of the crystals to modulate light-transport with the goal of further improving axial-resolution. These experimental results were used to benchmark DETECT2000 Monte Carlo simulations for our detector geometry. The axial-positioning calibration was carried out by evaluating a uniform flood-irradiation method and comparing with the collimated-irradiation method using 2 × 2 × 100 mm3 crystal detectors. The best axial-positioning resolution of 3.4 mm was achieved in this study for 2 × 2 × 100 mm3 Teflon-wrapped crystals with banding-patterns on only two opposite surfaces, fulfilling the design criteria of our proposed PET. The benchmarked DETECT2000 models can now be used to predict the performance of a complete detector module design. The calibration methods agreed if the trigger threshold energies were adjusted to give similar single event rates in both PSPMTs for uniform flood-irradiation. The implementation of flood-irradiation method in our complete PET scanner will provide a simple axial-positioning calibration.

Since the advent of the Internet, we have been observing a fast-paced development within the computing world. One of the major innovations in recent years is the “Internet of Things”, which brings interconnectedness between devices and humans to unprecedented heights. This technological breakthrough enabled the emergence of a new sub-field within Learning Analytics, Multimodal Learning Analytics, which makes use of several types of data sources to study learning-related processes. As computers and sensors become increasingly cheaper and more accessible,  research within this new sub-field grows, yet some gaps remain unexplored. Additionally, there is a research bias toward computer-assisted learning environments, rather than physical ones. At the same time, the current labor market is highly competitive, and possessing profession-related skills is not sufficient to land a job. Besides these skills, there is an increasing demand for social skills, such as communication, teamwork, and collaboration. However, there is a gap between the skills that are trained in an academic setting and the ones that are required by the labor market. Having this background in mind, this work aims at designing and evaluating an IoT sensor system capable of tracking patterns observed under social interactions within a group, and more specifically, in terms of the distance between group members while solving a task. Another important aspect of this study is the system's cost-effectiveness so that it can be employed in a scalable and sustainable manner. To achieve this goal, a multimethodological approach for Design Science Research was adopted, which implied the combination of several methods such as sketching, prototyping, and testing. As a result, this study contributes both to the research area of Multimodal Learning Analytics, and to educational practices.

In general, computer software vulnerabilities are defined as special cases where an unexpected behavior of the system leads to the degradation of security properties or the violation of security policies. These vulnerabilities can be exploited by malicious users or systems impacting the security and/or operation of the attacked system. Since the literature on vulnerabilities is not always available to developers and the used tools do not allow detecting and avoiding them; the software industry continues to be affected by security breaches. Therefore, the detection of vulnerabilities in software has become a major concern and research area. Our research was done under the scope of the SHIELDS European project and focuses specifically on modeling techniques and formal detection of vulnerabilities. In this area, existing approaches are limited and do not always rely on a precise formal modeling of the vulnerabilities they target. Additionally detection tools produce a significant number of false positives/negatives. Note also that it is quite difficult for a developer to know what vulnerabilities are detected by each tool because they are not well documented. Under this context the contributions made in this thesis are: Definition of a formalism called template. Definition of a formal language, called Vulnerability Detection Condition (VDC), which can accurately model the occurrence of a vulnerability. Also a method to generate VDCs from templates has been defined. Defining a second approach for detecting vulnerabilities which combines model checking and fault injection techniques. Experiments on both approaches

Thesis (M.Sc.)--York University, 2004. Graduate Programme in Computer Science.<br>Typescript. Includes bibliographical references (leaves 163-167). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL: http://gateway.proquest.com/openurl?url%5Fver=Z39.88-2004&res%5Fdat=xri:pqdiss &rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:MR11919

碩士<br>國立中正大學<br>電機工程研究所<br>89<br>In this thesis, we put forward three different kinds of parallel processing architectures. As to the high-speed image detection, generally, there are either symmetric figures or those without complicated designs; e.g., designs whose figures comprise shapes such as circles, diamonds, triangles, etc. In the first design, we detect the number of the edge points at the round locus by adopting the method of pre-storing the image templates and working with the multi-processor architecture. In the second design, we demonstrate our ability to quickly spread the information at the edge points by employing a new detection method from the mesh-connected processor, and by working in broadcasting. Simplifying the processor element of the former design, we can enjoy wider aspect of application in the final design. In our designs, each processor element has been simplified so that only one adder or one comparator is required, consequently, easing modification it would be considerably easy. Time efficiency is considerably improved.

碩士<br>國立中正大學<br>電機工程研究所<br>99<br>The development of network is growing up quickly that accompanied by the many applications and many attacks. For the reason, it is necessary to establish the intrusion detection and prevention systems on the router or switch that can detect and prevent the network intrusions in the large scale institutions. If the speed of intrusion detection and prevention system is not faster than or equal to line rate, it is become to the bottleneck of network bandwidth. In this thesis, we proposed an intrusion detection and prevention system. It is a hardware software co-design implementation with NetFPGA and Snort. With this feature, it is high flexibility and high detection efficiency. The core of hardware architecture is the pipelined Bloom Filters with separation of rule sets, so it can be avoid the high density of rule spaces that reduce the accuracy of matching. In the practical design, we also implement the chip with ASIC flow. In the APR stage, it can run up to 495 MHz. Our proposed design can deal with the needs of high speed without the bottleneck of network bandwidth.

碩士<br>國立海洋大學<br>電機工程學系<br>91<br>The main purpose of an intrusion detection system (IDS) is to monitor the traffics on the network, sniff out malicious activities, block attacks on the computers, and alert the system administrators when necessary. A well-known example of the IDS is Snort, a freeware which uses misuse detection to sense network intrusions. The detection is primarily based on pattern matching for the contents of the incoming packets. A match with any of the predetermined string patterns signifies a potential intrusion attempt. Pattern matching operations are highly CPU-bound and require a large amount of memory accesses. When the network traffic is heavy, a certain amount of packets are likely to elude the screening of Snort. To facilitate the pattern matching operations of an IDS, we propose in this thesis a multi-pattern matching hardware architecture. For performance considerations, we adopt the Aho-Corasick algorithm for pattern matching and use binary search to reduce memory references. The hardware is implemented with a VHDL-based FPGA design flow emphasizing design scalability and reusability. On our current FPGA platform, the circuit operates at a baud rate of 500 kByte/s, which is suitable for most ADSL applications. For high-speed network environments, our design allows easy multiplication into a parallel pattern-matching engine and will be able to provide performance enhancements required for a variety of applications.

As we move deep into nanometer regime of CMOS VLSI (45nm node and below), the device noise margin gets sharply eroded because of continuous lowering of device threshold voltage together with ever increasing rate of signal transitions driven by the consistent demand for higher performance. Sharp erosion of device noise margin vastly increases the likelihood of intermittent failures (also known as parametric failures) during device operation as opposed to permanent failures caused by physical defects introduced during manufacturing process. The major sources of intermittent failures are capacitive crosstalk between neighbor interconnects, abnormal drop in power supply voltage (also known as droop), localized thermal gradient, and soft errors caused by impact of high energy particles on semiconductor surface. In nanometer technology, these intermittent failures largely outnumber the permanent failures caused by physical defects. Therefore, it is of paramount importance to come up with efficient test generation and test application methods to accurately detect and characterize these classes of failures. Soft error rate (SER) is an important design metric used in semiconductor industry and represented by number of such errors encountered per Billion hours of device operation, known as Failure-In-Time (FIT) rate. Soft errors are rare events. Traditional techniques for SER characterization involve testing multiple devices in parallel, or testing the device while keeping it in a high energy neutron bombardment chamber to artificially accelerate the occurrence of single events. Motivated by the fact that measurement of SER incurs high time and cost overhead, in this thesis, we propose a two step approach: ⟨i⟩ a new filtering technique based on amplitude of the noise pulse, which significantly reduces the set of soft error susceptible nodes to be considered for a given design; followed by ⟨ii⟩ an Integer Linear Program (ILP)-based pattern generation technique that accelerates the SER characterization process by 1-2 orders of magnitude compared to the current state-of-the-art. During test application, it is important to distinguish between an intermittent failure and a permanent failure. Motivated by the fact that most of the intermittent failures are temporally sparse in nature, we present a novel design-for-testability (DFT) architecture which facilitates application of the same test vector twice in a row. The underlying assumption here is that a soft fail will not manifest its effect in two consecutive test cycles whereas the error caused by a physical defect will produce an identically corrupt output signature in both test cycles. Therefore, comparing the output signature for two consecutive applications of the same test vector will accurately distinguish between a soft fail and a hard fail. We show application of this DFT technique in measuring soft error rate as well as other circuit marginality related parametric failures, such as thermal hot-spot induced delay failures. A major contribution of this thesis lies on investigating the effect of multiple sources of noise acting together in exacerbating the noise effect even further. The existing literature on signal integrity verification and test falls short of taking the combined noise effects into account. We particularly focus on capacitive crosstalk on long signal nets. A typical long net is capacitively coupled with multiple aggressors and also tend to have multiple fanout gates. Gate leakage current that originates in fanout receivers, flows backward and terminates in the driver causing a shift in driver output voltage. This effect becomes more prominent as gate oxide is scaled more aggressively. In this thesis, we first present a dynamic simulation-based study to establish the significance of the problem, followed by proposing an automatic test pattern generation (ATPG) solution which uses 0-1 Integer Linear Program (ILP) to maximize the cumulative voltage noise at a given victim net due to crosstalk and gate leakage loading in conjunction with propagating the fault effect to an observation point. Pattern pairs generated by this technique are useful for both manufacturing test application as well as signal integrity verification for nanometer designs. This research opens up a new direction for studying nanometer noise effects and motivates us to extend the study to other noise sources in tandem including voltage drop and temperature effects.

碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>88<br>Curve detection is an important research area in computer vision. In developing efficient and effective curve detection methods, it is necessary to conduct large numbers of experiments on randomly generated images. Such a process can be very tedious and time consuming. In this thesis, a platform for developing curve detection methods based on randomized Hough transform (RHT) is designed and implemented. The objective is to expedite the process of developing RHT-based curve detection methods. In so doing, we have made use of design patterns to create a framework that provides support for random image generation and result visualization. With this platform, developers can easily plug in new RHT-based methods and conduct experiments. To demonstrate this, two examples using RHT and coaxal transform are given.

A business application automates a collection of business processes. A business process describes how a set of logically related tasks are executed, ordered and managed by following business rules to achieve business objectives. An “online book purchase” business process contains several tasks such as buying a book, ordering a book, and sending out promotions. In this ever changing business environment, both of business applications and business processes are modified to accommodate changed business requirements and improve the performance of the organization. These continuous modifications introduce problems in the following two aspects: 1) Business process definitions are rarely updated to reflect the current business processes deployed in business applications. 2) Business processes may be cloned (e.g., copied and slightly modified) to handle special circumstances or promotions. Identifying these clones and removing them help improve the efficiency of an organization. However, business processes are defined with textual languages that cannot be automatically understood. To maintain business process definitions up to date, we present our techniques that automatically recover business processes from UIs of business applications and identify clones in the recovered business processes. We leverage UI design patterns, which present the best practices of UI designs, to capture business processes from UIs. To refine the recovered business processes and mark the functionally equivalent tasks, we use existing code clone detection tools, such as CCFinder and CloneDR, to detect clones in business applications, and lift clones from code level to business process level. The effectiveness of our techniques is demonstrated through a case study on 15 large open source business applications.<br>Thesis (Master, Computing) -- Queen's University, 2008-10-28 11:06:31.41

碩士<br>國立中正大學<br>電機工程研究所<br>93<br>In this thesis, we propose three kinds of array processors that detect the vertical symmetry axis for patterns in the image. Based on the detected symmetry axis, the symmetric pattern can be further extracted. In the first design, we use two n-bit shift-registers to process n bits of input image data in one row, and connect the image data in the near-coincident positions of the two shift-registers to the two-input AND gates. By shifting the data of two shifter registers in two opposite directions, all the midpoints of edge-point pairs in the same row can be generated. To have a faster processor response, the second design links all the possible pairings of the row image data by the 2-input AND gates. It makes use of the hardwired-OR circuits to combine the AND-gate outputs for the same midpoint position through the ingenious IC layout placement. Thus, without costing too much chip area, we can acquire all the midpoints of the given row generated within one clock period. In the third design, we input the edge-point image data column by column (that is, pixel by pixel sequentially with respect to each row). By connecting the input shift-register of each row to another shift-register that shifts in the reverse direction, the encountering of all the edge-point pairs in the same row can be achieved. Though the hardwired-OR circuit combining the pairing AND gates, the alternating shifts of the two shift-registers sequentially generate the midpoints of all edge-pairs in each row. With the collection of midpoint information, our parallel circuits accumulate the midpoint count at each column position of the image. If the count value of a column position is greater than the given threshold, then this coordinate is taken as where the pattern’s vertical symmetry axis locates. Based on the location of detected symmetry axis, our system retrieves the image data of each corresponding two columns on two sides of the axis. And by taking some logical operations, the symmetric patterns can be extracted. In order to correctly evaluate the ease of layout placement, chip area, and the actual performance for the above array processors, we realize the major parts of our designs as IC chips. We adopt the TSMC 0.35μ Mixed Signal (2P4M) CMOS technology and the full custom design to implement the second and third array processor design. The IC layout and Hspice simulation of the second design have been complete and successful, while the fabricated chip of the third array processor design has been physically tested and verified to be successful. Keywords： Array Processor, Symmetry Axis, Symmetric Patterns , Parallel Processing

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>The aim of this thesis is to design a measurement system that can be used to quantify and store the situation of nasal obstruction. The condition of the nasal obstruction usually do not fit in with patients’ feelings, so there is a need to find an objective measurement method to inspect the condition of nasal obstruction quantitatively. It also helps doctors to understand patients’ nasal obstruction condition. There are many kinds of apparatuses to measure the condition of nasal obstruction, and most of the apparatuses measure the pressure or the flow rate of air in nasal cavity. In this study, we adopt the condenser microphone as the detecting component. The expiratory air will flow through the condenser microphones array. The data are processed and stored in the registers of 8051 single-chip, and then delivered to computer via the RS-232 interface. We can compare the previous saved data and the current measured data. Then we can assess whether the nasal obstruction has improved or not.