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Journal articles on the topic 'Design Rule Check (DRC)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Nandy, S. K. "Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment." VLSI Design 1, no. 2 (1994): 155–67. http://dx.doi.org/10.1155/1994/54126.

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In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.

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Nandy, S. K., and R. B. Panwar. "Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors." VLSI Design 1, no. 2 (1994): 127–54. http://dx.doi.org/10.1155/1994/96830.

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Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

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Luo, Zhen, Margaret Martonosi, and Pranav Ashar. "An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking." VLSI Design 10, no. 3 (2000): 249–63. http://dx.doi.org/10.1155/2000/71046.

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Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking and a general scalable architecture for DRC. W

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Rajapriyadharshini, B., V. Renisha, S. Shivani, Kumar S. Bharath, and P. Latha. "Analog / Full Custom IC Design of Wilson Current Mirror." International Journal of Microsystems and IoT 2, no. 12 (2024): 1440–46. https://doi.org/10.5281/zenodo.15455573.

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This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modif

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Jun, Shi. "Deep sub-micron ESD GGNMOS layout design and optimization." MATEC Web of Conferences 198 (2018): 04009. http://dx.doi.org/10.1051/matecconf/201819804009.

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In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Des

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Huang, Chih-Yi, Lihong Cao, Keng-Tuan Chang, and Chen-Chao Wang. "High Density Package Design Platform and Assembly Design Kit." International Symposium on Microelectronics 2021, no. 1 (2021): 000234–38. http://dx.doi.org/10.4071/1085-8024-2021.1.000234.

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Abstract With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package

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Белявцев, А. В., А. В. Русанов, and Т. С. Шайкина. "RC OSCILLATOR FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 20, no. 1 (2024): 45–50. http://dx.doi.org/10.36622/1729-6501.2024.20.1.007.

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предложен сложно-функциональный (СФ/IP) блок RC-генератора, построенный на МОП-транзисторах. Генератор является блоком тактирования для большого числа электронных устройств, не требовательных к стабильности частоты, но чувствительных к размеру. Данный блок предназначен для применения в составе интегральных схем стабилизаторов напряжения. Приведено описание электрической схемы генератора, его основные электрические характеристики и результаты моделирования (зависимости частоты генератора и его тока потребления от температуры и напряжения питания схемы, получены значения нестабильности частоты и

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Белявцев, А. В., А. В. Русанов та Д. О. Лялин. "СФ‑БЛОКИ ПРИЕМНИКА И ПЕРЕДАТЧИКА LVDS ДЛЯ ТЕХНОЛОГИЧЕСКОГО ПРОЦЕССА 180 НМ". ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 21, № 1 (2025): 107–13. https://doi.org/10.36622/1729-6501.2025.21.1.016.

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представлены два сложно-функциональных (СФ/IP) блока для интегральных схем: приемник и передатчик низковольтной дифференциальной передачи сигналов (Low voltage differntial signal - LVDS). Раздел статьи, посвященный передатчику LVDS, содержит подробное описание структурной схемы СФ‑блока и электрических схем его составных частей, результаты моделирования, временные диаграммы работы и основные электрические параметры устройства. Отдельное внимание уделено особенностям схемотехнических решений, использованных при проектировании. Раздел, посвященный СФ‑блоку приемника LVDS, содержит краткое описан

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Poluektov, Aleksandr, Dmitriy Shehovcov, I. Skorkin, and Pavel Chubunov. "Integrating the Calibre software product into the Cadence Virtuoso environment and increasing the intelligent properties of CAD IC design." Modeling of systems and processes 16, no. 4 (2023): 71–80. http://dx.doi.org/10.12737/2219-0767-2023-16-4-71-80.

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The article discusses the technology for integrating Caliber into the Cadence Virtuoso environment and describes the impact of this integration on the productivity of engineers. The possibility of ensuring optimal interaction between developers and increasing the overall efficiency of the design team is considered, leading to end-to-end design optimization. The integration of Caliber and Cadence Virtuoso represents an important step in Electronic Design Development (EDA) and can solve a number of problems while improving the efficiency of the verification and analysis process. Here are a few a

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Русанов, А. В., Л. В. Сопина, and А. В. Бунина. "BANDGAP REFERENCE VOLTAGE SOURCE FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 19, no. 4 (2023): 71–76. http://dx.doi.org/10.36622/vstu.2023.19.4.009.

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предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключев

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Gaddipati, Kavya. "Balancing Performance and Area in High-Speed Analog Layout Design: Systematic Approaches to DRC/LVS Optimization." European Journal of Computer Science and Information Technology 13, no. 21 (2025): 37–47. https://doi.org/10.37745/ejcsit.2013/vol13n213747.

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This article explores systematic approaches to navigating the critical balance between performance and area in high-speed analog layout design. It shows methodologies for efficient debugging of Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations, which represent fundamental verification steps in the analog design workflow. The article presents structured techniques for prioritizing and resolving verification issues, including hierarchical debugging approaches and automation tools for repetitive checks. Additionally, it gives area optimization strategies such as shared diffu

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M, G. Srinivasa. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology (IJEAT) 13, no. 5 (2024): 12–16. https://doi.org/10.35940/ijeat.E4447.13050624.

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<strong>Abstract:</strong> The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuos

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Goeritno, Arief, Dian Anwar, Syaiful Syaiful, Ritzkal Ritzkal, Ahya Ibadina Syahida, and Rezi Setria. "IMPLEMENTASI LITERASI TERHADAP APLIKASI EASILY APPLICABLE GRAPHICAL LAYOUT EDITOR BERBASIS PENDIDIKAN ISLAM." TA'DIBUNA: Jurnal Pendidikan Agama Islam 1, no. 1 (2018): 79. http://dx.doi.org/10.30659/jpai.1.1.79-106.

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On Islamic education for students of SMK Elektronika, it has been done summary material about application with image brands (brand image) Easily Applicable Graphical Layout Editor (EAGLE) by literacy approach. EAGLE application is one of the principals of fundamental Islamic education in the material form. The literacy of EAGLE application material, including general explanation and important notes to the EAGLE application. A common explanation of the EAGLE application which is one of the many applications for the draft in the manufacture of pieces of printed boards (printed cicuit board, PCB)

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Zargari, Amir Hosein Afandizadeh, Marzieh AshrafiAmiri, Minjun Seo, Sai Manoj Pudukotai Dinakarrao, Mohammed E. Fouda, and Fadi Kurdahi. "CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering." Information 14, no. 12 (2023): 656. http://dx.doi.org/10.3390/info14120656.

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Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate-level information of an IC. In general, the RE process can be done for validation as well as Intellectual Property (IP) stealing intentions. In addition, RE also facilitates different illicit activities such as the insertion of hardware Trojan, pirating, or counterfeiting a design, or developing an attack. In this work, we propose an approach to introduce cognitive perturbations, with the aid of adversarial machine

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M G Srinivasa and Bhavana M S. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology 13, no. 5 (2024): 12–16. http://dx.doi.org/10.35940/ijeat.e4447.13050624.

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The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for

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16

Venkatesh, G. K., S. Bhargavi, Basavaraj V. Hiremath, and C. Anil Kumar. "Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology." International Journal of Circuits, Systems and Signal Processing 15 (July 28, 2021): 730–44. http://dx.doi.org/10.46300/9106.2021.15.81.

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The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as w

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Rikan, Behnam S., David Kim, Kyung-Duk Choi, et al. "T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process." Sensors 22, no. 2 (2022): 507. http://dx.doi.org/10.3390/s22020507.

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This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over

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Srivatsan Nurani Subramanyam. "AI-Driven DRC Routing Convergence in IC Design : A Paradigm Shift in Semiconductor Development." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 5 (2024): 744–55. http://dx.doi.org/10.32628/cseit241051064.

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This article explores the transformative impact of Artificial Intelligence (AI) on Integrated Circuit (IC) design, particularly in Design Rule Checking (DRC) and routing convergence. As semiconductor technology advances to smaller nodes, traditional design methodologies struggle with increasing complexity, time-to-market pressures, and stringent manufacturing constraints. Integrating AI-driven approaches offers promising solutions, dramatically reducing design cycles, improving yield, and enabling continued scaling. The article discusses the challenges of modern IC design, the critical role of

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Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.

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INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of prov

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Загидуллина, О. Р., та А. С. Надин. "ИССЛЕДОВАНИЕ LDE-ЭФФЕКТОВ И МЕТОДОВ АТТЕСТАЦИИ ФАЙЛОВ DRC ДЛЯ СУБМИКРОННЫХ ТЕХНОЛОГИЙ 90-28 НМ". NANOINDUSTRY Russia 96, № 3s (2020): 619–22. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.619.622.

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С уменьшением проектных норм увеличивается влияние LDE-эффектов. Как следствие, повышается сложность разработки командных файлов DRC и их верификации. В статье рассмотрены базовые методы верификации командных файлов: регрессионное тестирование, параметризованные и квалификационные ячейки. Данные методы позволяют исключить ошибки в командных файлах, появление которых может привести к необходимости повторения полного цикла работ по проектированию и изготовлению кристалла. With the continuous scaling down of CMOS technologies the influence of Layout Dependent Effects increases. As a result, the c

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Toms, Ozalle Marie, Gloria Campbell-Whatley, Shannon Stuart, and Tia Schultz. "The effects of check-in check-out on the academic planning and behavior of African American males." Journal for Multicultural Education 12, no. 3 (2018): 278–93. http://dx.doi.org/10.1108/jme-03-2017-0016.

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Purpose The Check-in Check-out (CICO) program is a Tier II behavioral intervention that has received empirical support as an effective way to reduce problem behaviors (Hawken and amp; Horner, 2003; March and amp; Horner, 2002). The purpose of this study is to use an intervention that combined CICO with social skill instruction and academic planning with three African-American ninth-grade males identified with emotional and behavioral disorders. A concurrent baseline across participants design was used to evaluate participants’ performance on academic planning and behavior. Results indicate tha

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Золотухин, Ф. С., А. С. Надин та И. Е. Трифанихина. "РАЗРАБОТКА ПРОТОТИПА ПРОГРАММНОГО МОДУЛЯ АВТОМАТИЗИРОВАННОЙ ГЕНЕРАЦИИ КВАЛИФИКАЦИОННЫХ ЯЧЕЕК ДЛЯ КОНТРОЛЯ ПРАВИЛ ПРОЕКТИРОВАНИЯ ИС". NANOINDUSTRY Russia 96, № 3s (2020): 721–25. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.721.725.

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Разработан прототип программного модуля генератора квалификационных ячеек для автоматизированного контроля геометрических правил проектирования DRC. Проведено тестирование прототипа генератора в реальных рабочих условиях проектирования. The paper presents a prototype of software module of the QA-cells Generator for automated Design Rule Checking. The QA-Cells Generator has been tested in the real workplace within actual microelectronic industrial design.

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Islam, Riadul. "Feasibility Prediction for Rapid IC Design Space Exploration." Electronics 11, no. 7 (2022): 1161. http://dx.doi.org/10.3390/electronics11071161.

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The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This res

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Parikh, Raj, and Khushi Sandip Parikh. "Mathematical Foundations of AI-Based Secure Physical Design Verification." Indian Journal of VLSI Design 5, no. 1 (2025): 1–7. https://doi.org/10.54105/ijvlsid.a1230.05010325.

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Concerns about hardware security are raised by the increasing dependence on third-party Semiconductor Intellectual Property in system-on-chip design, especially during physical design verification. Traditional rule-based verification methods, such as Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checking, together with side-channel analysis indicated apparent deficiencies in dealing with new forms of threat. The impossibility of distinguishing dependable from malicious insertions in ICs makes it hard to prevent such dangers as hardware Trojans (HTs); side-channel vulnerabilities re

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Khushi, Sandip Parikh. "Mathematical Foundations of AI-Based Secure Physical Design Verification." Indian Journal of VLSI Design (IJVLSID) 5, no. 1 (2025): 1–7. https://doi.org/10.54105/ijvlsid.A1230.05010325.

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<strong>Abstract:</strong> Concerns about hardware security are raised by the increasing dependence on third-party Semiconductor Intellectual Property in system-on-chip design, especially during physical design verification. Traditional rule-based verification methods, such as Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checking, together with side-channel analysis indicated apparent deficiencies in dealing with new forms of threat. The impossibility of distinguishing dependable from malicious insertions in ICs makes it hard to prevent such dangers as hardware Trojans (HTs); side

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HARASHIMA, Ichiro, Koji SHIROYAMA, Kazuhiro AOYAMA, and Tuyoshi KOGA. "3320 A Study of General Rule Representation Model for Design Parameter Check." Proceedings of the JSME annual meeting 2008.4 (2008): 217–18. http://dx.doi.org/10.1299/jsmemecjo.2008.4.0_217.

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Mythili, M., D. Badiger Sujata, Singh Jayati, and Rangam Totakura Venkata. "A Review Report on Multi-Voltage Rule Check and Formal Verification of ASIC Design." Journal of VLSI Design and its Advancement 3, no. 2 (2020): 1–11. https://doi.org/10.5281/zenodo.3890999.

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<em>In order to decrease the power dissipation in ASIC design, Multi-voltage design techniques such as Power gating, Clock gating, Power down mode, Multi-threshold, etc. are employed. To help designers verify the correct implementation of these low power design techniques, Multi-voltage Rule Check is used. The implementation of different Multi-voltage design elements such as Isolation Cell, Level Shifter Cell, Retention Cell and power aware design is explained using Unified power format (UPF). And in the design process from Register-transfer level (RTL) to Graphic Database System (GDSII)

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Harada, Takashi, Manabu Kusumoto, and Takahiro Yaguchi. "Development of EMI Rule Check Tool for Supporting Printed Circuit Board Layout Design." Journal of Japan Institute of Electronics Packaging 14, no. 6 (2011): 477–84. http://dx.doi.org/10.5104/jiep.14.477.

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Bekki, Khadhir, and Hafida Belachir. "Towards a Flexible and Adaptable Modeling of Business Processes." International Journal of Information Technology and Web Engineering 6, no. 2 (2011): 57–67. http://dx.doi.org/10.4018/jitwe.2011040105.

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This article proposes a flexible way in business process modeling and managing. Today, business process needs to be more flexible and adaptable. The regulations and policies in organizations, as origins of change, are often expressed in terms of business rules. The ECA (Event-condition-action) rule is a popular way to incorporate flexibility into a process design. To raise the flexibility in the business processes, the authors consider governing any business activity through ECA rules based on business rules. For adaptability, the separation of concerns supports adaptation in several ways. To

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Khalil, Mazin R., and Saja B. Mahmood. "Proportional-Integral -Derivative Controller Using Embedded System Design Techniques." Tikrit Journal of Engineering Sciences 21, no. 2 (2013): 44–51. http://dx.doi.org/10.25130/tjes.21.2.06.

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This paper aims to design a proportional-integral-derivative(PID)controller to be configured on fieldprogrammable gate arrays(FPGAs) using Embedded Design Techniques(EDTs). Soft-core processorsystem is built using Integrated Software Environment (ISE 10.1)supplied by Xilinx and configured onSpartan 3E slice. The system is programmed by C language to act as PID controller .Trapezoidal rule isused for integration and finite difference method is used for derivative calculation .The designedcontroller is connected to a Matlab /Simulink of a DC motor model to check its functionality.

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Thomas, P. R., and A. D. Brown. "Performance analysis of an IC-mask design rule check and net extraction software suite." IEE Proceedings G Circuits, Devices and Systems 136, no. 4 (1989): 205. http://dx.doi.org/10.1049/ip-g-2.1989.0036.

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Singh, Rambir, and Asheesh K. Singh. "Design and Analysis of an Improved Approximated Fuzzy Logic Controller for Shunt Active Power Filter." International Journal of Fuzzy System Applications 2, no. 3 (2012): 69–89. http://dx.doi.org/10.4018/ijfsa.2012070105.

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This paper presents the design and analysis of an improved approximated simplest fuzzy logic controller (IASFLC). A cascade combination of simplest 4-rule fuzzy logic controller (FLC) and an nth degree polynomial is proposed as an IASFLC to approximate the control characteristics of a 49-rule FLC. The scheme is based on minimizing the sum of square errors between the control outputs of a 49-rule FLC and a simplest 4-rule FLC in the entire range of universe of discourse (UOD). The coefficients of compensating polynomial are evaluated by solving instantaneous square error equations at various te

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Acito, Bill. "Advanced Package Design: Inter-Domain Design Methodologies." International Symposium on Microelectronics 2019, no. 1 (2019): 000284–88. http://dx.doi.org/10.4071/2380-4505-2019.1.000284.

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Abstract Just as we transitioned from simplistic lead frames to large ball grid arrays decades ago, we find ourselves again at another inflection point in design. Originally a derivative of PCB design, IC package design finds itself straddling both PCB-style design and traditional IC design. Dimensions have shrunk to place IC package design squarely in the same design dimensions as integrated circuits. Likewise, with Moore's law rapidly losing steam to support SoC's as a system integration vehicle, advanced package technologies have been asked to fill the system enablement gap. We now see adva

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Lin, Zhifeng, Zhenghua Gu, Zhipeng Huang, Xiqiong Bai, Lixuan Luo, and Geng Lin. "Hotspot Detection with Machine Learning Based on Pixel-Based Feature Extraction." Scientific Programming 2022 (August 23, 2022): 1–11. http://dx.doi.org/10.1155/2022/7803329.

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The complexity of physical verification increases rapidly with fast shrinking technology nodes. Considering only design rule checking (DRC) constraints or lithography models cannot capture the side physical effects in the fabrication process well. Thus, it is desirable to consider a more general physical verification problem with various types of hotspots. In this paper, we apply machine learning which is based on pixel-based feature extraction to deal with the generalized hotspot detection problem. First, a two-dimensional discrete Fourier transformation-based pixel extraction method is propo

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Xiao, Qing, and Shaowu Zhou. "Comparing unscented transformation and point estimate method for probabilistic power flow computation." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 3 (2018): 1290–303. http://dx.doi.org/10.1108/compel-09-2017-0393.

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Purpose Unscented transformation (UT) and point estimate method (PEM) are two efficient algorithms for probabilistic power flow (PPF) computation. This paper aims to show the relevance between UT and PEM and to derive a rule to determine the accuracy controlling parameters for UT method. Design/methodology/approach The authors derive the underlying sampling strategies of UT and PEM and check them in different probability spaces, where quadrature nodes are selected. Findings Gauss-type quadrature rule can be used to determine the accuracy controlling parameters of UT. If UT method and PEM selec

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Xu, Xurong. "Exploration of English Composition Diagnosis System Based on Rule Matching." International Journal of Emerging Technologies in Learning (iJET) 13, no. 07 (2018): 161. http://dx.doi.org/10.3991/ijet.v13i07.8603.

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To discuss the grammar checking system and to solve the low accuracy of the system and bad effect, the grammar checking algorithm and the accuracy were improved. On this basis, a grammar checking system was designed and developed. The grammar checking module adopted the grammar checking design based on multi-rules and used multi-layer grammar rules to provide error correction function for common English grammar. To improve the grammar checking accuracy of grammar checking module, the grammatical model based on statistics was introduced by the system. In addition, N-gram model was applied to ev

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Shahid, Rooma, Abdullah Jan, Ayesha Fazal, Alaina Tariq Mughal, Fareena Ghaffar, and Sundas Mehmood. "Intra-Observer Variation of Space Available in the Mandibular Dental Arch by Two Different Measuring Tools-Vernier Calliper and Brass Wire with a Millimetre Ruler." Pakistan Armed Forces Medical Journal 73, no. 2 (2023): 389–401. http://dx.doi.org/10.51253/pafmj.v73i2.5615.

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Objective: To check the variation of space available in the mandibular dental arch using different tools, i.e., Vernier caliper and brass wire with a millimeter ruler. Study Design: Comparative cross-sectional study. Place and Duration of Study: Department of Orthodontics, Armed Forces Institute of Dentistry (AFID), Rawalpindi Pakistan, from Sep to Dec 2019. Methodology: Seventy-five dental casts of patients, with an age range between 12-25 years were included in the study. The variation of the space available using two different measuring tools (Vernier calliper and brass wi

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Yılmaz, Cengiz, and Hüseyin Atilla Dikbaş. "A Building Information Modeling Based Automated Rule-Checking Application for Zoning Regulation Compliance: The Case of Turkiye." Firat University Journal of Experimental and Computational Engineering 4, no. 2 (2025): 424–45. https://doi.org/10.62520/fujece.1691523.

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The aim of this study is to develop an automated rule-checking application that enables the rapid, transparent, and efficient verification of building design data, created through Building Information Modeling (BIM), in compliance with zoning regulations during the design and approval phases of construction projects in Turkiye. In this context, rules expressed in regulatory texts were transformed into a format adaptable to software using propositional logic, and decision structures were created. Distinctive parameters based on the rules to be checked were assigned to the BIM environment. Model

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Takarajima, Itaru, Kiyoshi Akama, Ikumi Imani, and Hiroshi Mabuchi. "Design of Nondeterministic Program Termination Based on the Equivalent Transformation Computation Model." Journal of Advanced Computational Intelligence and Intelligent Informatics 10, no. 3 (2006): 349–61. http://dx.doi.org/10.20965/jaciii.2006.p0349.

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We studied the termination of nondeterministic programs, which play an important, basic role in program synthesis, and provide a foundation for proving program termination. The class of programs we consider here is based on the <I>equivalent transformation (ET)</I> computation model. Computation with this model involves the succesive application of rules to sets of clauses. Since the ET model has more expressive terms and rules than other programming languages, program termination is difficult to prove: we must take into account all possible changes of terms made by various rules.

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Power, R. J. D., and M. F. Dal Martello. "The use of the definite and indefinite articles by Italian preschool children." Journal of Child Language 13, no. 1 (1986): 145–54. http://dx.doi.org/10.1017/s0305000900000350.

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ABSTRACTIn deciding whether to use a definite or indefinite referring expression a speaker must apply a pragmatic rule: the definite article is usually appropriate if the listener is already familiar with the referent, and the indefinite article if not. Several studies have investigated at what age this rule is mastered by children. The most satisfactory procedure so far adopted is a task in which the subject must narrate a pictorially-presented story to another child who cannot see the pictures. It has been found that 5-year-old children already follow the correct rule quite well, except that

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Wang, Ming Hui, Yong Quan Yu, and Bi Zeng. "Neuro-Fuzzy Controller for Rudder Roll Stabilization of Ships." Applied Mechanics and Materials 66-68 (July 2011): 1278–85. http://dx.doi.org/10.4028/www.scientific.net/amm.66-68.1278.

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The uncertainty of ship models and interferences can lead to reduce the effectiveness of conventional roll stabilization controller depending upon accurate mathematical model.This paper proposes the design of neuro-fuzzy controller for rudder roll stabilization. Learning ability of neural network is utilized to optimize the fuzzy controller. Hybrid learning rule which is a combination of backpropagation algorithm and least square estimator is utilized to realized parameter adjustment of fuzzy control rule and membership function in order to improve the adaptive capacity of controller. The simu

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PRASAD, BIREN. "Survey of life-cycle measures and metrics for concurrent product and process design." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 14, no. 2 (2000): 163–76. http://dx.doi.org/10.1017/s0890060400142052.

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Concurrent Engineering needs a series of measures (or measurement criteria) that are distinct to each process, and a set of metrics to check (and validate) the outcome when two or more of the life-cycle processes are overlapped or required to be executed in parallel. Because product realization involves concurrent processes that occur across multiple disciplines and organizations, appropriate measures and the methods of qualifying metrics are essential. Inevitably, such concurrent processes generate design conflicts among multiple life-cycle concerns. Individual assurances of satisfying life-c

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Sobhkhiz, Soroush, Yu-Cheng Zhou, Jia-Rui Lin, and Tamer E. El-Diraby. "Framing and Evaluating the Best Practices of IFC-Based Automated Rule Checking: A Case Study." Buildings 11, no. 10 (2021): 456. http://dx.doi.org/10.3390/buildings11100456.

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This research reviews recent advances in the domain of Automated Rule Checking (ARC) and argues that current systems are predominantly designed to validate models in post-design stages, useful for applications such as e-permitting. However, such a design-check-separated paradigm imposes a burden on designers as they need to iteratively fix the fail-to-pass issues. Accordingly, the study reviews the best-practices of IFC-based ARC systems and proposes a framework for ARC system development, aiming to achieve proactive bottom-up solutions building upon the requirements and resources of end-users

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Gandjour, Afschin, Nadja Chernyak, Andrea Icks, and Amiram Gafni. "Public acceptance of different approaches to determine drug reimbursement prices and whether it is influenced by framing." International Journal of Public Sector Management 27, no. 6 (2014): 501–11. http://dx.doi.org/10.1108/ijpsm-06-2013-0083.

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Purpose – In Germany, the Institute for Quality and Efficiency in Health Care (Institut für Qualität und Wirtschaftlichkeit im Gesundheitswesen (IQWiG)) makes recommendations for reimbursement prices of drugs based on an evaluation of the relationship between incremental costs and effects. In 2009, the German government (“Koalitionsvertrag”) announced its intention to evaluate the transparency and acceptability of IQWiG's work. The purpose of this paper is to conduct a survey of a sample of the German population: to check the acceptance of the IQWiG's decision rule compared to a decision rule

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Choi, Jungsik, Sejin Lee, and Inhan Kim. "Development of Quality Control Requirements for Improving the Quality of Architectural Design Based on BIM." Applied Sciences 10, no. 20 (2020): 7074. http://dx.doi.org/10.3390/app10207074.

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Building information modeling (BIM) technology has been utilized increasingly in quantitative ways in the architecture, engineering, and construction disciplines. However, owing to increasing requirements for improvement in qualitative factors in BIM-based design projects, it has become necessary to develop a checking and evaluation process for BIM-based architectural design. The purpose of this study is to develop and apply BIM-based quality control requirements for improving the quality of architectural design. To achieve this, the research investigated case studies for BIM data quality cont

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Sommers, Alexander, Shahram Rahimi, Tonya McCall, et al. "A Hybrid Expert System for Estimation of the Manufacturability of a Notional Design." Applied Computational Intelligence and Soft Computing 2024 (March 26, 2024): 1–17. http://dx.doi.org/10.1155/2024/4985090.

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The more “manufacturable” a product is, the “easier” it is to manufacture. For two different product designs targeting the same role, one may be more manufacturable than the other. Evaluating manufacturability requires experts in the processes of manufacturing, “manufacturing process engineers” (MPEs). Human experts are expensive to train and employ, while a well-designed expert system (ES) could be quicker, more reliable, and provide higher performance and superior accuracy. In this work, a group of MPEs (“Team A”) externalized a portion of their expertise into a rule-based expert system in c

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Wu, Xi, and Yafeng Wang. "Improving Polar-Coded SCMA System by Information Coupling and Parity Check." Sensors 20, no. 23 (2020): 6740. http://dx.doi.org/10.3390/s20236740.

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In this paper, the uplink information-coupled polar-coded sparse code multiple access (PC-SCMA) system is proposed. For this system, we first design the encoding method of systematic joint parity check and CRC-aided (PCCA) polar code. Using the systematic PCCA-polar code as base code, the partially information-coupled (PIC) polar code is constructed. Then, a joint iterative detection and successive cancellation list (SCL)-decoding receiver is proposed for the PC-SCMA system. For the receiver, the coupled polar decoder’s extrinsic messages are calculated by the Bayes rule and soft cancellation

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CHAE, HEUNG SEOK, JOON-SANG LEE, and JUNGHO BAE. "AN APPROACH TO CHECKING BEHAVIORAL COMPATIBILITY BETWEEN WEB SERVICES." International Journal of Software Engineering and Knowledge Engineering 18, no. 02 (2008): 223–41. http://dx.doi.org/10.1142/s0218194008003647.

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This paper proposes an approach to checking behavioral compatibility between Web services. If Web service B can be used in replacement of Web service A in such a way that the replacement is transparent to clients, Web service B is compatible to Web service A. We use state machines with guarded transitions to specify behaviors of Web services. To check compatibility between two Web services, we propose an extended version of the conventional methods rule, which has been used in object-oriented paradigm. To support our approach, we have implemented a tool. First, the tool constructs a state mach

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Li, Ping, Songtao Guo, Jiahui Wu, and Quanjun Zhao. "BlockREV: Blockchain-Enabled Multi-Controller Rule Enforcement Verification in SDN." Security and Communication Networks 2022 (January 11, 2022): 1–16. http://dx.doi.org/10.1155/2022/7294638.

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Compared with the classical structure with only one controller in software-defined networking (SDN), multi-controller topology structure in SDN provides a new type of cross-domain forwarding network architecture with multiple centralized controllers and distributed forwarding devices. However, when the network includes multiple domains, lack of trust among the controllers remains a challenge how to verify the correctness of cross-domain forwarding behaviors in different domains. In this paper, we propose a novel secure multi-controller rule enforcement verification (BlockREV) mechanism in SDN

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Tedjosurya, Dian Puspita, and Suharjito Suharjito. "MODEL OF MOBILE TRANSLATOR APPLICATION OF ENGLISH TO BAHASA INDONESIA WITH RULE-BASED AND J2ME." CommIT (Communication and Information Technology) Journal 8, no. 1 (2014): 28. http://dx.doi.org/10.21512/commit.v8i1.593.

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Along with the development of information technology in recent era, a number of new applications emerge, especially on mobile phones. The use of mobile phones, besides as communication media, is also as media of learning, such as translator application. Translator application can be a tool to learn a language, such as English to Bahasa Indonesia translator application. The purpose of this research is to allow user to be able to translate English to Bahasa Indonesia on mobile phone easily. Translator application on this research was developed using Java programming language (especially J2ME) be

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