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Relevant bibliographies by topics / Digit-Serial Arithmetic

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Academic literature on the topic 'Digit-Serial Arithmetic'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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Journal articles on the topic "Digit-Serial Arithmetic"

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Nielsen, Asger, and Peter Kornerup. "MSB-First Digit Serial Arithmetic." JUCS - Journal of Universal Computer Science 1, no. (7) (1995): 527–47. https://doi.org/10.3217/jucs-001-07-0527.

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We develop a formal account of digit serial number representations by describing them as strings from a language. A prefix of a string represents an int erval approximating a number by enclosure. Standard on-line representations are shown to be a special case of the general digit serial representations. Matrices are introd uced as representations of intervals and a finite-state transducer is used for mapping str ings into intervals. Homographic and bi-homographic functions are used for representing basi c arithmetic operations on digit serial numbers, and finally a digit serial represen tation

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BASHAGHA, A. E., and M. K. IBRAHIM. "DIGIT-SERIAL SQUARING ARCHITECTURE." Journal of Circuits, Systems and Computers 04, no. 01 (1994): 99–108. http://dx.doi.org/10.1142/s0218126694000077.

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A digit-serial squaring architecture based on radix-2n arithmetic is presented to carry out squaring digit serially. In this paper, the conventional binary squaring algorithm is modified and a radix-2n squaring algorithm which is used to design the proposed architectures is presented. The resulting basic cell is the Digital Controlled Add/shiFt (DCAF) cell. The advantage of using radix-2n arithmetic is that it specifies the functionality of the DCAF cell only and, hence, there is no restriction on the type of adder to be used. It can be a ripple carry adder, a carry lookahead adder, a pipeline

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Corbett, P., and R. Hartley. "Designing systolic arrays using digit-serial arithmetic." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39, no. 1 (1992): 62–65. http://dx.doi.org/10.1109/82.204111.

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Bisdounis, L., D. E. Metafas, A. M. Maras, and C. Mavridis. "VLSI implementation of digit-serial arithmetic modules." Microprocessing and Microprogramming 39, no. 2-5 (1993): 251–54. http://dx.doi.org/10.1016/0165-6074(93)90099-7.

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Ibrahim, Muhammad Sohail, Muhammad Usman, and Jeong-A. Lee. "ECHO: Energy-Efficient Computation Harnessing Online Arithmetic—An MSDF-Based Accelerator for DNN Inference." Electronics 13, no. 10 (2024): 1893. http://dx.doi.org/10.3390/electronics13101893.

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Deep neural network (DNN) inference demands substantial computing power, resulting in significant energy consumption. A large number of negative output activations in convolution layers are rendered zero due to the invocation of the ReLU activation function. This results in a substantial number of unnecessary computations that consume significant amounts of energy. This paper presents ECHO, an accelerator for DNN inference designed for computation pruning, utilizing an unconventional arithmetic paradigm known as online/most significant digit first (MSDF) arithmetic, which performs computations

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Nilsson, Peter. "Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS." VLSI Design 2009 (January 17, 2009): 1–10. http://dx.doi.org/10.1155/2009/749272.

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This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely, bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative

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Satyanarayana, J. H., and B. Nowrouzian. "A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms." Journal of Circuits, Systems and Computers 07, no. 06 (1997): 517–35. http://dx.doi.org/10.1142/s0218126697000395.

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This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths. In the resulting optimization technique, the cost associated with the final digital filter data-path is minimized subject to user-specified constraints on the number of physical arithmetic functional units employed. The proposed technique is capable of obtaining global area-optimal, time-optimal, or combined area-cum-time-optimal data-paths, where the optimality takes into account not

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Issad, M., M. Anane, B. Boudraa, A. M. Bellemou, and N. Anane. "Efficient FPGA Implementation of Modular Multiplication and Exponentiation." Malaysian Journal of Computing and Applied Mathematics 3, no. 1 (2020): 1–13. http://dx.doi.org/10.37231/myjcam.2020.3.1.37.

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This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated in Hardware (HW) as Programmable System on Chip (PSoC). The processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between execution time, occupied area and flexibility. In order to satisfy this constraint, Montgomery Power Ladder and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and for the MM implementatio

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Tjandra, Yozef, and Sanga Lawalat. "PARALLEL NUMERICAL COMPUTATION: A COMPARATIVE STUDY ON CPU-GPU PERFORMANCE IN PI DIGITS COMPUTATION." Jurnal Pilar Nusa Mandiri 18, no. 2 (2022): 93–100. http://dx.doi.org/10.33480/pilar.v18i2.3291.

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As the usage of GPU (Graphical Processing Unit) for non-graphical computation is rising, one important area is to study how the device helps improve numerical calculations. In this work, we present a time performance comparison between purely CPU (serial) and GPU-assisted (parallel) programs in numerical computation. Specifically, we design and implement the calculation of the hexadecimal -digit of the irrational number Pi in two ways: serial and parallel. Both programs are based upon the BBP formula for Pi in the form of infinite series identity. We then provide a detailed time performance an

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Issad, M., B. Boudraa, M. Anane, and A. M. Bellemou. "Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination." Journal of Circuits, Systems and Computers 28, no. 13 (2019): 1950229. http://dx.doi.org/10.1142/s0218126619502293.

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This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than th

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Dissertations / Theses on the topic "Digit-Serial Arithmetic"

1

Natter, William. "Design and implementation of digit-serial online multiply-accumulate arithmetic operations." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ60479.pdf.

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Singh, Manpreet. "Power Characterization of a Digit-Online FPGA Implementation of a Low-Density Parity-Check Decoder for WiMAX Applications." Thesis, 2014. http://hdl.handle.net/10012/8529.

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Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integ

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Book chapters on the topic "Digit-Serial Arithmetic"

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Hartley, Richard, and Keshab K. Parhi. "Online Arithmetic." In Digit-Serial Computation. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2327-7_13.

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Hartley, Richard, and Keshab K. Parhi. "Canonic Signed Digit Arithmetic." In Digit-Serial Computation. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2327-7_12.

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Nielsen, Asger Munk, and Peter Kornerup. "MSB-First Digit Serial Arithmetic." In J.UCS The Journal of Universal Computer Science. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/978-3-642-80350-5_44.

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Hariri, Arash, and Arash Reyhani-Masoleh. "Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields." In Arithmetic of Finite Fields. Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-69499-1_9.

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Ercegovac, Miloš D., and Tomás Lang. "Digit-Serial Arithmetic." In Digital Arithmetic. Elsevier, 2004. http://dx.doi.org/10.1016/b978-155860798-9/50011-7.

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Hitch, Graham J. "The phonological loop as a neural network." In Memory in Science for Society. Oxford University PressOxford, 2023. http://dx.doi.org/10.1093/oso/9780192849069.003.0008.

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Abstract The phonological loop was the first subsystem to be explored in the multicomponent model of working memory and remains arguably the best understood. This chapter describes how evidence about verbal short-term memory converged on the idea of the loop as a rapidly decaying phonological store refreshed by subvocal rehearsal. It describes how the loop accounts for systematic cross-linguistic differences in digit span, is used to store temporary information in cognitive skills such as mental calculation, and, most importantly, vocabulary acquisition. However, the initial description did no

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Conference papers on the topic "Digit-Serial Arithmetic"

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Balsara, Poras T., and Robert M. Owens. "Systolic & semi-systolic digit serial multipliers." In 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH). IEEE, 1987. http://dx.doi.org/10.1109/arith.1987.6158682.

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Natter, W. G., and B. Nowrouzian. "Digit-serial online arithmetic for high-speed digital signal processing applications." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.986900.

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Li, Yao, Jianxin Zhu, and George Eichmann. "On-the-fly conversion of a modified signed digit into two’s complement binary number representation." In OSA Annual Meeting. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.mhh2.

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An attractive nonbinary parallel arithmetic scheme uses the so-called modified sign digit (MSD), also known as the radix-two redundantnumber system. Using the MSD, carry-free addition, subtraction, and multiplication can be performed. However, because the conventional MSD to two’s-complement-binary (TCB) conversion scheme is a serial processing technique, the overall processing speed is limited. Using a new conversion algorithm and the polarization switching technique, we propose an optical carry-free MSD to TCB conversion method. The availability of this converter will lead to a large speed i

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