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Journal articles on the topic 'Digit-Serial Arithmetic'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Nielsen, Asger, and Peter Kornerup. "MSB-First Digit Serial Arithmetic." JUCS - Journal of Universal Computer Science 1, no. (7) (1995): 527–47. https://doi.org/10.3217/jucs-001-07-0527.

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We develop a formal account of digit serial number representations by describing them as strings from a language. A prefix of a string represents an int erval approximating a number by enclosure. Standard on-line representations are shown to be a special case of the general digit serial representations. Matrices are introd uced as representations of intervals and a finite-state transducer is used for mapping str ings into intervals. Homographic and bi-homographic functions are used for representing basi c arithmetic operations on digit serial numbers, and finally a digit serial represen tation

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2

BASHAGHA, A. E., and M. K. IBRAHIM. "DIGIT-SERIAL SQUARING ARCHITECTURE." Journal of Circuits, Systems and Computers 04, no. 01 (1994): 99–108. http://dx.doi.org/10.1142/s0218126694000077.

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A digit-serial squaring architecture based on radix-2n arithmetic is presented to carry out squaring digit serially. In this paper, the conventional binary squaring algorithm is modified and a radix-2n squaring algorithm which is used to design the proposed architectures is presented. The resulting basic cell is the Digital Controlled Add/shiFt (DCAF) cell. The advantage of using radix-2n arithmetic is that it specifies the functionality of the DCAF cell only and, hence, there is no restriction on the type of adder to be used. It can be a ripple carry adder, a carry lookahead adder, a pipeline

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3

Corbett, P., and R. Hartley. "Designing systolic arrays using digit-serial arithmetic." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39, no. 1 (1992): 62–65. http://dx.doi.org/10.1109/82.204111.

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4

Bisdounis, L., D. E. Metafas, A. M. Maras, and C. Mavridis. "VLSI implementation of digit-serial arithmetic modules." Microprocessing and Microprogramming 39, no. 2-5 (1993): 251–54. http://dx.doi.org/10.1016/0165-6074(93)90099-7.

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5

Ibrahim, Muhammad Sohail, Muhammad Usman, and Jeong-A. Lee. "ECHO: Energy-Efficient Computation Harnessing Online Arithmetic—An MSDF-Based Accelerator for DNN Inference." Electronics 13, no. 10 (2024): 1893. http://dx.doi.org/10.3390/electronics13101893.

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Deep neural network (DNN) inference demands substantial computing power, resulting in significant energy consumption. A large number of negative output activations in convolution layers are rendered zero due to the invocation of the ReLU activation function. This results in a substantial number of unnecessary computations that consume significant amounts of energy. This paper presents ECHO, an accelerator for DNN inference designed for computation pruning, utilizing an unconventional arithmetic paradigm known as online/most significant digit first (MSDF) arithmetic, which performs computations

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6

Nilsson, Peter. "Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS." VLSI Design 2009 (January 17, 2009): 1–10. http://dx.doi.org/10.1155/2009/749272.

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This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely, bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative

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7

Satyanarayana, J. H., and B. Nowrouzian. "A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms." Journal of Circuits, Systems and Computers 07, no. 06 (1997): 517–35. http://dx.doi.org/10.1142/s0218126697000395.

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This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths. In the resulting optimization technique, the cost associated with the final digital filter data-path is minimized subject to user-specified constraints on the number of physical arithmetic functional units employed. The proposed technique is capable of obtaining global area-optimal, time-optimal, or combined area-cum-time-optimal data-paths, where the optimality takes into account not

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8

Issad, M., M. Anane, B. Boudraa, A. M. Bellemou, and N. Anane. "Efficient FPGA Implementation of Modular Multiplication and Exponentiation." Malaysian Journal of Computing and Applied Mathematics 3, no. 1 (2020): 1–13. http://dx.doi.org/10.37231/myjcam.2020.3.1.37.

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This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated in Hardware (HW) as Programmable System on Chip (PSoC). The processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between execution time, occupied area and flexibility. In order to satisfy this constraint, Montgomery Power Ladder and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and for the MM implementatio

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9

Tjandra, Yozef, and Sanga Lawalat. "PARALLEL NUMERICAL COMPUTATION: A COMPARATIVE STUDY ON CPU-GPU PERFORMANCE IN PI DIGITS COMPUTATION." Jurnal Pilar Nusa Mandiri 18, no. 2 (2022): 93–100. http://dx.doi.org/10.33480/pilar.v18i2.3291.

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As the usage of GPU (Graphical Processing Unit) for non-graphical computation is rising, one important area is to study how the device helps improve numerical calculations. In this work, we present a time performance comparison between purely CPU (serial) and GPU-assisted (parallel) programs in numerical computation. Specifically, we design and implement the calculation of the hexadecimal -digit of the irrational number Pi in two ways: serial and parallel. Both programs are based upon the BBP formula for Pi in the form of infinite series identity. We then provide a detailed time performance an

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10

Issad, M., B. Boudraa, M. Anane, and A. M. Bellemou. "Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination." Journal of Circuits, Systems and Computers 28, no. 13 (2019): 1950229. http://dx.doi.org/10.1142/s0218126619502293.

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This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than th

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11

Giannouli, Vaitsa, and Magda Tsolaki. "Financial Incapacity of Patients with Mild Alzheimer’s Disease: What Neurologists Need to Know about Where the Impairment Lies." Neurology International 14, no. 1 (2022): 90–98. http://dx.doi.org/10.3390/neurolint14010008.

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Research in the last decade has focused on assessing financial capacity and incapacity mainly in old age, but new research has turned to address the question of how financial incapacity can be predicted by cognitive factors. The aim of this study was to identify which cognitive domains predict financial capacity and the relevant cognitive skills of patients with mild Alzheimer’s disease (AD) in order to assist neurologists in functional assessment and further patient referral. In this study, 109 patients diagnosed with mild AD were examined with a number of neuropsychological tests: Mini-Menta

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12

Sandry, Joshua, Jessica Paxton, and James F. Sumowski. "General Mathematical Ability Predicts PASAT Performance in MS Patients: Implications for Clinical Interpretation and Cognitive Reserve." Journal of the International Neuropsychological Society 22, no. 3 (2016): 375–78. http://dx.doi.org/10.1017/s1355617715001307.

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AbstractObjectives: The Paced Auditory Serial Addition Test (PASAT) is used to assess cognitive status in multiple sclerosis (MS). Although the mathematical demands of the PASAT seem minor (single-digit arithmetic), cognitive psychology research links greater mathematical ability (e.g., algebra, calculus) to more rapid retrieval of single-digit math facts (e.g., 5+6=11). The present study evaluated the hypotheses that (a) mathematical ability is related to PASAT performance and (b) both the relationship between intelligence and PASAT performance as well as the relationship between education an

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13

Krieg, Edward F., David W. Chrislip, Carlos J. Crespo, W. Stephen Brightwell, Richard L. Ehrenberg, and David A. Otto. "The Relationship between Blood Lead Levels and Neurobehavioral Test Performance in NHANES III and Related Occupational Studies." Public Health Reports 120, no. 3 (2005): 240–51. http://dx.doi.org/10.1177/003335490512000305.

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Objectives. The goals of this study were two-fold: ( 1) to assess the relationship between blood lead levels and neurobehavioral test performance in a nationally representative sample of adults from the third National Health and Nutrition Evaluation Survey and ( 2) to analyze the results from previously published studies of occupational lead exposure that used the same neurobehavioral tests as those included in the survey. Methods. Regression models were used to test and estimate the relationships between measurements of blood lead and performance on a simple reaction time, a symbol-digit subs

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14

Monica, Kommalapati, Dereddy Anuradha, Syed Rasheed, and Barnala Shereesha. "VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder." International Journal of Intelligent Engineering and Systems 14, no. 1 (2021): 22–31. http://dx.doi.org/10.22266/ijies2021.0228.03.

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Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have d

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15

Кожевников, Алексей, and Aleksey Kozhevnikov. "TONE DEVICE SYNTHESIS FOR MODULE MULTIPLICATION." Bulletin of Bryansk state technical university 2019, no. 3 (2019): 65–70. http://dx.doi.org/10.30987/article_5c8b5ceb59c001.39557524.

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The application of the systems of residual classes (SRC) allows carrying out arithmetic operations of addition and multiplication more efficiently which are basic in DSP at the expense of small digit capacity of deductions. An additional growth of an operating speed gives a transition from a digital processing to a tone one, that is, to number encoding in the SRC by discrete phases of tone signals of one frequency. The application of an instrumentation framework on the superconductor basis shows an outlook of the special processor formation on the basis of principles marked earlier with the pr

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16

Zeghid, Medien, Anissa Sghaier, Hassan Yousif Ahmed, and Osman Ahmed Abdalla. "Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices." Electronics 12, no. 19 (2023): 4110. http://dx.doi.org/10.3390/electronics12194110.

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The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multipl

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17

Nešić, Milkica, Svetlana Čičević, Vladimir Nešić, Jelena Kostić, and Milan Ćirić. "Gender Differences in Prosodic Characteristics of Speech in the Task of Serial Subtracting of Sevens." Acta Facultatis Medicae Naissensis 30, no. 1 (2013): 5–13. http://dx.doi.org/10.2478/v10283-012-0030-6.

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Summary Significant differences in speech between genders are contained in nonsegmental correlates, i.e. in the prosody and paralinguistics. Pronunciation differences between genders are more numerous than those in grammatical form. This study aims to detect temporal prosodic patterns and investigate gender differences in performing serial sevens subtraction (SSS). One hundred students of medicine (equal number of males and females) voluntarily participated in the investigation. SSS was performed by asking the participant to perform mental arithmetic consisting of repeatedly subtractions of se

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18

Kalbande, Abhijit Gajendra, and Saurabh Ashok Ghogare. "Design of Digit Serial FIR Filter." Gurukul International Multidisciplinary Research Journal, April 30, 2025. https://doi.org/10.69758/gimrj/2504i5vxiiip0001.

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Abstract- Today filter is the most important component in digital signal processing system from last few decade, on low complexity bit-parallel multiple constant multiplication (MCM) more efficient algorithm and architecture has been developed which are used in DSP system but it offer more complexity as compared to digit serial MCM filter due to which we are interested in design of digit serial MCM filter it has low cost and offers more delay. In this paper we address more the problem of optimizing the area required for to design filter and also we introduce high level synthesis algorithm and

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19

Kattner, Florian, Sarah Hanl, Linda Paul, and Wolfgang Ellermeier. "Task-specific auditory distraction in serial recall and mental arithmetic." Memory & Cognition, October 14, 2022. http://dx.doi.org/10.3758/s13421-022-01363-6.

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AbstractPrevious studies suggest that task-irrelevant changing-state sound interferes specifically with the processing of serial order information in the focal task (e.g., serial recall from short-term memory), whereas a deviant sound in the auditory background is supposed to divert central attention, thus producing distraction in various types of cognitive tasks. Much of the evidence for this distinction rests on the observed dissociations in auditory distraction between serial and non-serial short-term memory tasks. In this study, both the changing-state effect and the deviation effect were

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20

Frougny, Christiane, Marta Pavelka, Edita Pelantova, and Milena Svobodova. "On-line algorithms for multiplication and division in real and complex numeration systems." Discrete Mathematics & Theoretical Computer Science Vol. 21 no. 3, Discrete Algorithms (2019). https://doi.org/10.23638/dmtcs-21-3-14.

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A positional numeration system is given by a base and by a set of digits. The base is a real or complex number $\beta$ such that $|\beta|&gt;1$, and the digit set $A$ is a finite set of digits including $0$. Thus a number can be seen as a finite or infinite string of digits. An on-line algorithm processes the input piece-by-piece in a serial fashion. On-line arithmetic, introduced by Trivedi and Ercegovac, is a mode of computation where operands and results flow through arithmetic units in a digit serial manner, starting with the most significant digit. In this paper, we first formulate a

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21

Nisar, Malik Zohaib, Muhammad Sohail Ibrahim, Saeid Gorgin, Muhammad Usman, and Jeong-A. Lee. "DSLR-CNN: Efficient CNN Acceleration using Digit-Serial Left-to-Right Arithmetic." IEEE Access, 2024, 1. http://dx.doi.org/10.1109/access.2024.3502918.

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22

E.Mallikarjuna. "Design and Implementation of FIR FILTER using MCM Architecture." J. of Advancement in Engineering and Technology Voulme 3, Issue 2 (2015). https://doi.org/10.5281/zenodo.890243.

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To Design the low complexity bit-parallel multiple constant multiplications (MCM) operation, many efficient algorithms and architectures have been introduced in the last two decades. The MCM operation has been dominates the complexity of many digital signal processing systems. On the other hand, the digit-serial MCM design has becoming more popular and this design offers alternative low complexity MCM operations albeit at the cost of an increased delay. In this paper we are introducing high level synthesis algorithms, design architectures and CAD tools and also we address the problem of optimi

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23

Issad, M., M. Anane, B. Boudraa, and A. M. Bellemou. "Efficient and Scalable Hardware Implementation of Montgomery Modular Multiplication." Journal of Circuits, Systems and Computers, January 24, 2022. http://dx.doi.org/10.1142/s0218126622501377.

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Modular multiplication (MM) is an important arithmetic operation in public key cryptography (PKC). In this paper, we present the FPGA implementation of the MM using Montgomery MM (MMM) algorithm. The execution performances of this operation depend on the radix-[Formula: see text] and the operands length. In fact, when increasing the radix-[Formula: see text], the MMM algorithm requires multiplications of digit by operand. On the other hand, when a long modulus is used, the hardware implementation of the MMM needs a large area. Our objective in this work is to realize a scalable architecture ab

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