Relevant bibliographies by topics / Digital-analog converter

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Digital-analog converter'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "Digital-analog converter"

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Melikyan, V. Sh, V. D. Hovhannisyan, M. T. Grigoryan, A. A. Avetisyan, and H. T. Grigoryan. "Real Number Modeling Flow of Digital to Analog Converter." Proceedings of Universities. Electronics 26, no. 2 (April 2021): 144–53. http://dx.doi.org/10.24151/1561-5405-2021-26-2-144-153.

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This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output signal’s voltage difference between RNM and SPICE models is less than 2 mV.
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Pandya, Priyesh, and Vikas Gupta. "Enhancing Analog to Digital Converter Resolution Using Oversampling Technique." International Journal of Engineering Research 3, no. 4 (April 1, 2014): 245–48. http://dx.doi.org/10.17950/ijer/v3s4/413.

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Evtikhiev, N. N., S. S. Karinskiĭ, D. I. Mirovitskiĭ, and V. T. Popkov. "Optoelectronic interferometric analog–digital converter." Soviet Journal of Quantum Electronics 17, no. 2 (February 28, 1987): 140–46. http://dx.doi.org/10.1070/qe1987v017n02abeh006544.

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Ivanov, Yu I. "Pulse-time digital-analog converter." Measurement Techniques 30, no. 8 (August 1987): 739–41. http://dx.doi.org/10.1007/bf00865654.

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Borisyuk, L. A., and S. U. Klimovich. "Logarithmic analog-to-digital converter." Measurement Techniques 32, no. 5 (May 1989): 398–401. http://dx.doi.org/10.1007/bf00866209.

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Groshev, V. Ya. "Functional analog-to-digital converter." Measurement Techniques 31, no. 6 (June 1988): 533–36. http://dx.doi.org/10.1007/bf00867520.

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Yang Wang, Yang Wang, Hongming Zhang Hongming Zhang, Yujie Dou Yujie Dou, and Minyu Yao Minyu Yao. "Experimental evaluation of resolution enhancement of a phase-shifted all optical analog-to-digital converter using an electrical analog-to-digital converter array." Chinese Optics Letters 11, no. 8 (2013): 082301–82303. http://dx.doi.org/10.3788/col201311.082301.

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Grechishnikov, V. M., and E. G. Komarov. "Increasing the information capacity of a fiber-optic multi-sensor converter of binary mechanical signals into electrical signals." Izmeritel`naya Tekhnika, no. 9 (2020): 15–23. http://dx.doi.org/10.32446/0368-1025it.2020-9-15-23.

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The design and operation principle of a multi-sensor Converter of binary mechanical signals into electrical signals based on a partitioned fiber-optic digital-to-analog Converter with a parallel structure is considered. The digital-to-analog Converter is made from a set of simple and technological (three to five digit) fiber-optic digital-to-analog sections. The advantages of the optical scheme of the proposed. Converter in terms of metrological and energy characteristics in comparison with single multi-bit converters are justified. It is shown that by increasing the number of digital-analog sections, it is possible to repeatedly increase the information capacity of a multi-sensor Converter without tightening the requirements for its manufacturing technology and element base. A mathematical model of the proposed Converter is developed that reflects the features of its operation in the mode of sequential time conversion of the input code vectors of individual fiber-optic sections into electrical analogues and the formation of the resulting output code vector.
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Lukić, Jelena, and Dragan Denić. "A Novel Design Of An NTC Thermistor Linearization Circuit." Metrology and Measurement Systems 22, no. 3 (September 1, 2015): 351–62. http://dx.doi.org/10.1515/mms-2015-0035.

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Abstract A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.
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Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.
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Dissertations / Theses on the topic "Digital-analog converter"

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Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.

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This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.

The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.

In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.

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Khilo, Anatol. "Integrated optical analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43035.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. [133]-137).
An optically-sampled frequency-demultiplexed wideband analog-to-digital converter (ADC) which has potential to exceed the performance of electronic ADCs by orders of magnitude is studied analytically and numerically. The accuracy of the ADC as a function of its parameters is analyzed and impact of various imperfections of ADC components on its operation is evaluated. A universal error compensation algorithm for improving the conversion accuracy is proposed. On the way to implementation of the integrated optical ADC, two of its critical components - ring resonator filter bank and fiber-to-chip coupler -are designed. A novel coupler from a standard single mode fiber to a strongly confining silicon waveguide is proposed. The results of characterization of the filter bank and fiber-to-chip coupler fabricated on the silicon-on-insulator platform are presented and analyzed.
by Anatol Khilo.
S.M.
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Luschas, Susan 1975. "Radio frequency digital to analog converter." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28277.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 124-126).
Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (f), where k>l. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrow-band sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.
by Susan Luschas.
Ph.D.
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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.
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Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.

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This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics. After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimizing the conversion time as well as keeping the precision of the floating point A/D converter (FP-ADC) by implementing the parallel architecture with Field Programmable Gate Arrays (FPGA). The thesis presents the design and practical implementation of the parallel FP-ADC, based on a FPGA and other hybrid components-of-the-shelf. The correctness of the design was verified by computer simulation, while the functionality of the implemented FP-ADC was tested on a test bench controlled by a PC. (Abstract shortened by UMI.)
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Wu, Yang 1974. "Monolithic nyquist rate analog to digital converter with digital calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29549.

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Nyquist rate analog to digital converter have always been an essential component in complex systems ranging from digital oscilloscope, radar, to modern telecommunication equipments. The fast-paced development in these complex systems has necessitated methods to improve resolution and power consumption of the analog to digital converters. The aim of this thesis is to offer one such method. The method involves the application of a digital DC reference source. The digital reference source will be proposed and used to remove mismatch, reduce comparator offset, thus improving the resolution of both flash and pipeline ADCs, while consuming no static power. The design of pipeline ADCs is also the emphasis of this work.
The digital reference source consists of flip-flops and RC low-pass filters. By programming flip-flops with appropriate digital bit streams, accurate DC reference levels can be generated. The generated DC reference levels replace the need for reference ladder in Flash ADCs. Furthermore, with programmability provided by the digital reference source, the generated reference levels can be modified to reduce comparator offset. The comparator offset reduction algorithm is also applied to pipeline ADCs to reduce non-linear distortion.
The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented.
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Breevoort, Cornelius Marius. "A 9-bit, pipelined GaAs analog-digital converter." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15036.

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Orchanian, Shant. "Split Non-Linear Cyclic Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/324.

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Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively loaded differential pair to achieve this gain. The design reduces die size, power usage, and analog complexity. To correct for this inherent non- linearity, a Split ADC concept is employed to enable digital background calibration and a correction algorithm to account for this non- linearity. The Integrated circuit is designed, laid out, and simulated using the Cadence Integrated Circuit Front to Back design suite (ICFB) in the 0.18um Jazz CMOS process.
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Gulati, Kush. "A low-power reconfigurable analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8701.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 197-200).
This thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design.
(cont.) At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0.82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power.
by Kush Gulati.
Ph.D.
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Mangione, Paul Louis. "A high-speed, folding, analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35436.

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Books on the topic "Digital-analog converter"

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(Firm), Motorola. QADC: Queued analog-to-digital converter reference manual. Phoenix, Arizona: Motorola, 1995.

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Singor, Henry W. High performance current scaling digital-to-analog converter design. Ottawa: National Library of Canada, 1990.

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Uster, Markus. Current-mode analog-to-digital converter for array implementation. Konstanz: Hartung-Gorre, 2003.

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Wrixon, Adrian. D-A converter test optimisation. Dublin: University College Dublin, 1996.

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Motorola. Modular microcontroller family ADC analog-to-digital converter reference manual. Phoenix, AZ: Motorola, 1993.

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Xin, Jane Q. A high-precision digital-to-analog converter for tuning applications. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Santos, Mauro, Jorge Guilherme, and Nuno Horta. Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15978-8.

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An, Wei. An 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter. Ottawa: National Library of Canada, 2000.

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Naraghi, Samira. A 4-bit analog-to-digital converter for high-speed serial links. Ottawa: National Library of Canada, 2004.

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Hayashi, Takayuki. A 1 V floating-point analog-to-digital converter for portable communication devices. Ottawa: National Library of Canada, 1998.

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Book chapters on the topic "Digital-analog converter"

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Weik, Martin H. "analog-digital converter." In Computer Science and Communications Dictionary, 46. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_620.

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Havskov, Jens, and Gerardo Alguacil. "Analog to digital converter." In Instrumentation in Earthquake Seismology, 87–111. Dordrecht: Springer Netherlands, 2004. http://dx.doi.org/10.1007/978-1-4020-2969-1_4.

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Weik, Martin H. "digital-to-analog converter." In Computer Science and Communications Dictionary, 414. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_5067.

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Havskov, Jens, and Gerardo Alguacil. "Analog to Digital Converter." In Instrumentation in Earthquake Seismology, 113–48. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-21314-9_4.

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Weik, Martin H. "analog-to-digital converter." In Computer Science and Communications Dictionary, 48. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_642.

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Gadre, Dhananjay V., and Sarthak Gupta. "Analog to Digital Converter (ADC)." In Getting Started with Tiva ARM Cortex M4 Microcontrollers, 183–209. New Delhi: Springer India, 2017. http://dx.doi.org/10.1007/978-81-322-3766-2_14.

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Rossi, Mattia, Nicola Toscani, Marco Mauri, and Francesco Castelli Dezza. "Analog to Digital Converter Peripheral." In Introduction to Microcontroller Programming for Power Electronics Control Applications, 151–66. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003196938-12.

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Flurry, Greg. "An Analog-to-Digital Converter." In Java on the Raspberry Pi, 397–412. Berkeley, CA: Apress, 2021. http://dx.doi.org/10.1007/978-1-4842-7264-0_12.

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Plassche, Rudy. "The converter as a black box." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 1–36. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_1.

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Plassche, Rudy. "The converter as a black box." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 1–49. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_1.

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Conference papers on the topic "Digital-analog converter"

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de Emeri, Jair Lins, Saulo Finco, and Wilmar Bueno de Moraes. "Analog/Digital ΣΔ converter." In 2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro). IEEE, 2017. http://dx.doi.org/10.1109/sbmicro.2017.8113018.

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Zheng Yang and J. Van der Spiegel. "Extrapolating analog-to-digital converter." In 48th Midwest Symposium on Circuits and Systems, 2005. IEEE, 2005. http://dx.doi.org/10.1109/mwscas.2005.1594234.

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Danilaev, D. P. "Analog-to-Digital Converter Selection for Digital Receiver." In 2019 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO). IEEE, 2019. http://dx.doi.org/10.1109/synchroinfo.2019.8813931.

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Phong, Nguyen, Chung Joseph, Mariavanessa Pascua, Scott Tarkul, Eric Vasham, and David Parent. "Pixel Level Analog to Digital Converter." In 2006 16th Biennial University/Government/Industry Microelectronics Symposium. IEEE, 2006. http://dx.doi.org/10.1109/ugim.2006.4286389.

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Pavan, Shanthi, and Nagendra Krishnapura. "Oversampling Analog-to-Digital Converter Design." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.130.

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Ginetti, Vandemeulebroecke, and Jespers. "RSD cyclic analog-to-digital converter." In 1993 Symposium on VLSI Circuits. IEEE, 1988. http://dx.doi.org/10.1109/vlsic.1988.1037455.

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Whitehouse, Harper. "Implicit Sampling Analog-to-Digital Converter." In 2006 IEEE 12th Digital Signal Processing Workshop & 4th IEEE Signal Processing Education Workshop. IEEE, 2006. http://dx.doi.org/10.1109/dspws.2006.265444.

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Green, Paul E. "Low-power analog-to-digital converter." In San Dieg - DL Tentative, edited by John C. Carson. SPIE, 1990. http://dx.doi.org/10.1117/12.23013.

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Choe, Myung-Jun, Kang-Jin Lee, Munkyo Seo, and Mesfin Teshome. "DC - 10GHz RF Digital to Analog Converter." In 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, 2011. http://dx.doi.org/10.1109/csics.2011.6062442.

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Chia-Nan Yeh and Yen-Tai Lai. "A novel flash analog-to-digital converter." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541901.

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Reports on the topic "Digital-analog converter"

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, July 1989. http://dx.doi.org/10.21236/ada268538.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, July 1987. http://dx.doi.org/10.21236/ada268539.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, October 1987. http://dx.doi.org/10.21236/ada268540.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, January 1991. http://dx.doi.org/10.21236/ada268541.

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Morris, Frank. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, January 1992. http://dx.doi.org/10.21236/ada268545.

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Morris, Frank. Analog-To-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, January 1988. http://dx.doi.org/10.21236/ada269030.

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Morris, Frank. Analog-To-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, April 1989. http://dx.doi.org/10.21236/ada269032.

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8

Morris, Frank. Analog-To-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, January 1989. http://dx.doi.org/10.21236/ada269031.

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9

Morris, Frank, and W. R. Wisseman. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, May 1988. http://dx.doi.org/10.21236/ada268835.

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10

Morris, Frank, and W. R. Wisseman. Analog-to-Digital Converter. Fort Belvoir, VA: Defense Technical Information Center, October 1990. http://dx.doi.org/10.21236/ada268836.

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