To see the other types of publications on this topic, follow the link: Digital-analog converter.
Dissertations / Theses on the topic 'Digital-analog converter'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Digital-analog converter.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.
Full textAbstract:
This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.
The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.
In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.
2
Khilo, Anatol. "Integrated optical analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43035.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. [133]-137).
An optically-sampled frequency-demultiplexed wideband analog-to-digital converter (ADC) which has potential to exceed the performance of electronic ADCs by orders of magnitude is studied analytically and numerically. The accuracy of the ADC as a function of its parameters is analyzed and impact of various imperfections of ADC components on its operation is evaluated. A universal error compensation algorithm for improving the conversion accuracy is proposed. On the way to implementation of the integrated optical ADC, two of its critical components - ring resonator filter bank and fiber-to-chip coupler -are designed. A novel coupler from a standard single mode fiber to a strongly confining silicon waveguide is proposed. The results of characterization of the filter bank and fiber-to-chip coupler fabricated on the silicon-on-insulator platform are presented and analyzed.
by Anatol Khilo.
S.M.
3
Luschas, Susan 1975. "Radio frequency digital to analog converter." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28277.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 124-126).
Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (f), where k>l. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrow-band sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.
by Susan Luschas.
Ph.D.
4
Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.
Full textAbstract:
This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.
5
Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.
Full textAbstract:
This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics.
After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimizing the conversion time as well as keeping the precision of the floating point A/D converter (FP-ADC) by implementing the parallel architecture with Field Programmable Gate Arrays (FPGA).
The thesis presents the design and practical implementation of the parallel FP-ADC, based on a FPGA and other hybrid components-of-the-shelf. The correctness of the design was verified by computer simulation, while the functionality of the implemented FP-ADC was tested on a test bench controlled by a PC. (Abstract shortened by UMI.)
6
Wu, Yang 1974. "Monolithic nyquist rate analog to digital converter with digital calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29549.
Full textAbstract:
Nyquist rate analog to digital converter have always been an essential component in complex systems ranging from digital oscilloscope, radar, to modern telecommunication equipments. The fast-paced development in these complex systems has necessitated methods to improve resolution and power consumption of the analog to digital converters. The aim of this thesis is to offer one such method. The method involves the application of a digital DC reference source. The digital reference source will be proposed and used to remove mismatch, reduce comparator offset, thus improving the resolution of both flash and pipeline ADCs, while consuming no static power. The design of pipeline ADCs is also the emphasis of this work.The digital reference source consists of flip-flops and RC low-pass filters. By programming flip-flops with appropriate digital bit streams, accurate DC reference levels can be generated. The generated DC reference levels replace the need for reference ladder in Flash ADCs. Furthermore, with programmability provided by the digital reference source, the generated reference levels can be modified to reduce comparator offset. The comparator offset reduction algorithm is also applied to pipeline ADCs to reduce non-linear distortion.
The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented.
7
Breevoort, Cornelius Marius. "A 9-bit, pipelined GaAs analog-digital converter." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15036.
Full text
8
Orchanian, Shant. "Split Non-Linear Cyclic Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/324.
Full textAbstract:
Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively loaded differential pair to achieve this gain. The design reduces die size, power usage, and analog complexity. To correct for this inherent non- linearity, a Split ADC concept is employed to enable digital background calibration and a correction algorithm to account for this non- linearity. The Integrated circuit is designed, laid out, and simulated using the Cadence Integrated Circuit Front to Back design suite (ICFB) in the 0.18um Jazz CMOS process.
9
Gulati, Kush. "A low-power reconfigurable analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8701.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 197-200).
This thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design.
(cont.) At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0.82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power.
by Kush Gulati.
Ph.D.
10
Mangione, Paul Louis. "A high-speed, folding, analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35436.
Full text
11
Martins, Isadora Freire. "A novel wavelet-based analog-to-digital converter." reponame:Repositório Institucional da UnB, 2017. http://repositorio.unb.br/handle/10482/31874.
Full textAbstract:
Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Elétrica, 2017.Submitted by Raquel Almeida (raquel.df13@gmail.com) on 2018-05-10T19:59:26Z No. of bitstreams: 1 2017_IsadoraFreireMartins.pdf: 4901785 bytes, checksum: 6a4cdb2ba378eee8aea8b36501481209 (MD5)
Approved for entry into archive by Raquel Viana (raquelviana@bce.unb.br) on 2018-05-15T19:19:37Z (GMT) No. of bitstreams: 1 2017_IsadoraFreireMartins.pdf: 4901785 bytes, checksum: 6a4cdb2ba378eee8aea8b36501481209 (MD5)
Made available in DSpace on 2018-05-15T19:19:38Z (GMT). No. of bitstreams: 1 2017_IsadoraFreireMartins.pdf: 4901785 bytes, checksum: 6a4cdb2ba378eee8aea8b36501481209 (MD5) Previous issue date: 2018-05-15
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES).
Nesta dissertação, é proposto um conversor analógico-digital cujo processo de amostragem é baseado em propriedades da transformada wavelet. Tais propriedades permitem identificar características de interesse do sinal—especificamente, a localização de seus pontos críticos e a descrição da morfologia nos trechos entre esses pontos—, e assim representá-lo, em vez de aplicar a amostragem uniforme e limitada pelo critério de Nyquist. A primeira parte deste trabalho apresenta a implementação do conversor em nível de sistema para diferentes resoluções e bases e escalas da transformada wavelet. Para validar o algoritmo de amostragem, é proposto também um algoritmo de reconstrução polinomial do sinal. Os resultados mostram que a identificação de pontos críticos e a estimativa da morfologia do sinal são realizadas com sucesso, tendo sido possível recuperar o sinal de entrada com alta correlação e baixo erro RMS entre os sinais original e reconstruído. A segunda parte deste texto apresenta o desenvolvimento em nível de circuito. A transformada wavelet é implementada por filtros wavelet analógicos, que são testados utilizando-se duas aproximações diferentes para sua resposta em frequência. Os resultados de simulações para variadas escalas permitem identificar os pontos críticos do sinal.
This manuscript presents the project of an analog-to-digital converter with a wavelet-based sampling scheme. Instead of sampling a signal with uniformly spaced samples and in a frequency limited by Nyquist's criteria, the proposed ADC represents an input signal based on its characteristics speci cally, the critical points localization and the estimation of the signal's morphology around these points. The rst part of this work contains the system-level development, where the sampling algorithm is proposed as well as a polynomial reconstruction algorithm. Tests are run for di erent resolutions and wavelet bases and scales. The results show that the system successfully localizes the critical points and estimates the morphology of the signal, with high correlation and low RMS error values observed between the reconstructed signal and the input. The second part of this work contains the circuit-level development, where the wavelet transform is implemented with analog wavelet lters. The transfer functions of these lters are obtained by applying two di erent approximation methods. The results across scales show the critical points' localization.
12
Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.
Full textAbstract:
This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence.
As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes.
The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization.
Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.
13
Debski, Michal. "Self-calibrating floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/26884.
Full textAbstract:
The Floating-Point Analog-to-Digital Converter (FPADC) is an extended version of the Fixed-Point ADC. It is designed to deal with a broader dynamic range of signals while exhibiting a smaller relative quantization error. The traditional implementation of the FPADC is characterized by a high relative precision, but it requires high-precision high-speed components in order to achieve that. The high precision of the high-speed components comes at a greater cost. This constraint limits the availability of FPADCs to high-priced designs.
The thesis addresses a low-speed and a low-cost calibration approach for the FPADC. It presents the architecture, design and implementation platform of a self-calibrating differential predictive FPADC which is characterized by utilizing low-grade components. The precision is maintained at high values by additional hardware that periodically performs calibration cycles. Starting with a review of the field of FPADC the thesis develops the understanding of the Floating Point ADCs. The implementation is then extended to include a high precision low speed calibrating ADC. A complete implementation of the design is carried out and described. Finally, experimental measurements are performed to test the new FPADC and present the acquired results.
14
Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.
Full textAbstract:
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
15
Uster, Markus. "Current-mode analog-to-digital converter for array implementation /." [S.l.] : [s.n.], 2003. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=15252.
Full text
16
Syed, Arsalan Jawed. "Analog-to-Digital Converter Design for Non-Uniform Quantization." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2654.
Full textAbstract:
The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.
High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.
17
Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
Full text
18
Hou, Xiaobo Rosen Warren A. Daryoush Afshin S. "A leaky waveguide all-optical analog-to-digital converter /." Philadelphia, Pa. : Drexel University, 2004. http://dspace.library.drexel.edu/handle/1860/437.
Full text
19
Palakurthi, Praveen Kumar. "Design of a low voltage analog to digital converter." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
Full text
20
Calmese, Ife D. "The proteretic Hopfield neural network analog to digital converter /." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1674094131&sid=4&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full textAbstract:
Thesis (Ph. D.)--Southern Illinois University Carbondale, 2008."Department of Electrical and Computer Engineering." Keywords: Hopfield neural network, Analog to digital converter. Includes bibliographical references (p. 47-48). Also available online.
21
Yang, Heemin Yi 1976. "A time-based energy-efficient analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/35300.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 123-129).
Dual-slope converters use time to perform analog-to-digital conversion but require 2N+1 clock cycles to achieve N bits of precision. We describe a novel algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive sub-ranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating Voltage-to-Time and Time-to-Voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an effcient mechanism for amplification and error cancellation allow for energy-effcient operation: In a 0.35 [mu]m implementation, we were able to achieve 12 bits of DNL limited precision or 11 bits of thermal noise-limited precision at a sampling frequency of 31.25kHz with 75 [mu] W of total analog and digital power consumption. These numbers yield a thermal noise-limited energy-efficiency of 1.17pJ per quantization level making it one of the most energy-effcient converters to date in the 10 to 12 bit precision range.
(cont.) This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18 [mu] m process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.
by Heemin Yi Yang.
Ph.D.
22
Karanicolas, Andrew N. (Andrew Nicholas). "A switched-capacitor pipelined BiCMOS analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/13578.
Full textAbstract:
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.Includes bibliographical references (leaves 133-135).
by Andrew Nicholas Karanicolas.
M.S.
23
Calmese, Ife. "The Proteretic Hopfield Neural Network Analog to Digital Converter." OpenSIUC, 2008. https://opensiuc.lib.siu.edu/dissertations/255.
Full textAbstract:
The Hopfield neuron with predictive hysteresis is proposed and the efficiency of employing these neurons in analog to digital conversion, via the Hopfield Neural Network, will be demonstrated. Traditional hysteresis is defined, generally, as the occurrence of a delayed effect when forces acting on an object are varied. It will be shown that predictive hysteresis, a type of reverse hysteresis, improves upon the speed of hysteretic and non hysteretic systems without compromising the accuracy.
24
Tenten, Wilfried. "Improved analog to digital converter circuits using CMOS technology." Thesis, University of Bath, 1990. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329619.
Full text
25
Aust, Carrie Ellen. "A Low-Power, Variable-Resolution Analog-to-Digital Converter." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/33737.
Full textAbstract:
Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz.Master of Science
26
Perry, Jonathan. "Digital to Analog Converter Design using Single Electron Transistors." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/33871.
Full textAbstract:
CMOS Technology has advanced for decades under the rule of Moore's
law. But all good things must come to an end. Researchers estimate that
CMOS will reach a lower limit on feature size within the next 10 to 15 years.
In order to assure further progress in the field, new computing architectures
must be investigated. These nanoscale architectures are many and varied. It
remains to be seen if any will become a legitimate successor to CMOS.
Single electron tunneling is a process by which electrons can be trans-
ported (tunnel) across a thin insulating surface. A conducting island sepa-
rated by a pair of quantum tunnel junctions creates a Single Electron Tran-
sistor (SET). SETs exhibit higher functionality than traditional MOSFETs,
and function best at very small feature sizes, in the neighborhood of 1nm.
Many circuits must be developed before SETs can be considered a viable
contender to CMOS technology. One important circuit is the Digital to
Analog Converter (DAC). DACs are present on many microprocessors and
microcontrollers in use today and are necessary in many situations. While
other SET circuits have been proposed, including ADCs, no DAC design
exists in open literature.
We propose three possible SET DAC designs and characterize them with
an HSPICE SET simulation model. The first design is a charge scaling
architecture similar to what is frequently used in CMOS. The second two
designs are based on a current steering architecture, but are unique in their
implementation with SETs.Master of Science
27
"High speed floating analog to digital converter and interpolating digital to analog converter." 2001. http://library.cuhk.edu.hk/record=b6073306.
Full textAbstract:
Wang Hongwei."February 2001."
Thesis (Ph.D.)--Chinese University of Hong Kong, 2001.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Mode of access: World Wide Web.
Abstracts in English and Chinese.
28
DER, CHEN LONG, and 陳龍德. "MEMS Sensor Analog To Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/04884113723842269656.
Full textAbstract:
碩士中華大學
機械與航太工程研究所
90
The research is for Micro Electro Mechanical System；MEMS Analog To Digital Converter；MEMS_ADC，It is design function can be auto adjustment offset voltage、 Input Voltage range and MEMS Sensor’s interface Single end Voltage Input，This MEMS_ADC’s Design is Mix Mode Integrated Circuit 。 Micro Electronically Mechanical System (MEMS) technology can be reduce mechanical、optics， can be affected by voice、phot、electricity、magnetism、taste、cold、heat and motion systematic technology，Will be twenty one century major’s industry technology，is wisdom model high unit price industry technology。In to design Micro Electronically Mechanical System (MEMS) sensor component Analog to Digital Converter， To be application the most wide and important component。 MEMS Analog To Digital Converter；MEMS_ADC is basic design structure such as ：Flash、Two-Step、Interpolating、Folding、Pipelined，This component design is using Pipelined Analog To Digital Converter。 Keywords :Micro Electronically Mechanical System (MEMS),sensor component, Analog to Digital Converter.
29
Chuang, Bob, and 莊博智. "Sigma-Delta Analog to Digital Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/22995366967144993753.
Full textAbstract:
碩士國立中興大學
電機工程學系所
98
A signal output with natural variations in energy retrieved by sensors is the analog type, while the subsequent circuit processing belongs to the digital type. Hence, to enable a smooth transition between analog and digital circuits requires A/D converters. Types of A/D converters are available for different applications. Practitioners regard Sigma-Delta A/D converters, which have been developed and improved for several decades, among the best converters available with wide applications in devices such as sphygmomanometers, ear thermometers, body weight scales, and audio frequency circuits. For mid to low speed, high bit A/D converter circuits, the advantage is that quantizer and digital filter processes can be completed using digital circuits. Current research has developed the integrator and comparator of the analog part with OP AMP, followed by creating the quantizer and decimation filter with a Complex-programmable Logic Device (CPLD), thus, obtaining a complete Sigma-Delta A/D digital converter. Finally, measuring instruments have evaluated important characteristics, such as integral non-linearity/differential non-linearity (INL/DNL) and the effective number of bits (ENOB).The measurement result: DNL is -1 to +0.9 LSB avg0.005 LSB, INL is -4 to +2 LSB avg-1.7 LSB, , ENOBAvg 5.4 bit.
30
Lai, Chien-Hung, and 賴建宏. "Switched-Current Digital to Analog Converter." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/09696832865076703720.
Full textAbstract:
碩士國立臺北科技大學
電腦通訊與控制研究所
89
The switched-current digital to analog converter has the advantages of small chip size and low power dissipation compared with the other kinds of converters. Therefore, the proposed DAC in this thesis adopts this kind of architecture. Because usual switched-current D/A converters convert signals in serial-input way, their speeds are not pretty well. In order to improve this shortcoming our proposed DAC compromises between serial-input and parallel-input ways to speed up the conversion rate. In this thesis, we design and implement a 10-bit digital to analog converter with TSMC 0.35mm 1P4M CMOS process technology. Basically, the switched-current D/A converter is comprised of a 5-bit weighted current source and a current divider by 32. The major difference between our proposed DAC and other switched-current D/A converters is that we adopt a new algorithm named combined-input algorithm. The algorithm first deals with 5LSBs(b1~b5) and then 5MSBs(b6~b10) by adding the preceding result of 5LSBs. This architecture presents the reduction of the number of transistors, chip size and power consumption. With the loads of 200W and 5pF to our proposed D/A converter, the simulation results show that our proposed switched-current digital to analog converter occupies an area of 0.35mm2 and consumes a power of 26.1mW with the speed up to 31.25MS/s.
31
Chou, Chia-Hsin, and 鄒家信. "Two-Step analog-to-Digital Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/56699227824701570271.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
92
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric applications. In this thesis, a two-step ADC architecture is proposed to have 200 MHz samples rate with 8-bit resolution. We design the high speed architecture analog-to-digital converter by using averaging technology for comparator offset voltage. We implemented the ADC in TSMC 0.35 µm 2P4M technology. The chip occupied 1*1 mm2 with supply voltage of 3.3V. Through simulation, the chip can work up to 200 MHz as the input sample of 10 MHz sin-wave and has the differential nonlinearity of DNL<0.4 LSB, the integral nonlinearity INL<0.5 LSB, and the efficient number of 7.5 bits.
32
WEN, CHIU CHAO, and 邱超文. "Digital to Analog Converter for 802.11a." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/57104816704179260793.
Full textAbstract:
碩士中華大學
電機工程學系碩士班
91
ABSTRACT Digital to Analog Converter for 802.11a The purpose of this thesis is to describe a Digital to Analog Converter for 802.11a 10bits/100MS/s environment. Under the premise that meeting high-speed requirement, the Digital to Analog Converter adopts Segmented digital to analog converter configuration, which consists of 4 8x8 Current Cell Matrix. Each matrix has 63 current cells controlled by 6 MSB ranging from B9 to B4, and other 255 equal current cells respectively controlled by 8 bits ranging from B2 to B9. B0 and B1 will use binary-weighted configuration. The Bandgap reference circuit will also be included to provide the Digital to Analog Converter we design with an external resistance powered by a stable voltage from Bandgap reference, to which produce stable current.
33
Hsia, Jonathan, and 夏宇鵬. "Design and Implementation of an Array Digital-to-Analog Converter and the Pipelined Analog-to-Digital Converter." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/72gj5x.
Full textAbstract:
碩士國立臺北科技大學
電機工程研究所
105
This thesis presents an array digital-to-analog converter (DAC), including a sampling rate of 200Ms/s and a resolution of 12 bits. The whole structure is completed with segmented topology and switched-current mode, which is composed with 3-bit binary code and 9-bit thermometer code. Complementary transistor are used to reduce the glitch of current. Furthermore, the 9-bit thermometer code is composed with a 3-bit and a 6-bit thermometer-codes not only to reduce the layout area but also to relax the circuit complexity. A four-quadrant symmetric current source arrangement is used to eliminate the nonlinearity and parabolic gradients error in chip layout. Furthermore, this thesis also presents a pipelined analog-to-digital converter (ADC), including a sampling rate of 200Ms/s and a resolution of 10 bits. The pipelined ADC which consists of 8 stages in 1.5-bit/stage, and one stage in 2-bit/stage. Notify that a digital error correction circuit is used to correct the offset error of comparator in the pipelined ADC. Besides, not only the active feedback is used to decrease the input impedance and reduce the channel-length modulation effect, but also the dummy switch is adopted to decrease the signal-dependent charge-injection and clock feedthrough error. Those adopted techniques can decrease the transmission error effectively. This thesis had been fabricated with the TSMC 0.18μm 1P6M CMOS technology at the supply voltage of 1.8V. The DAC operates with a differential output current rage from -4.095 mA to +4.095 mA. The maximum DNL is 0.8 LSB and the minimum DNL is -0.8 LSB. The maximum INL is 0.786 LSB and the minimum INL is -0.217 LSB. The SNDR is 73.1 dB and the ENOB is 11.85 bits. Its power consumption is about 3.746mW. In view of ADC, its differential current range varies from -40µA to +40µA. The maximum DNL is 0.201 LSB and the minimum DNL is -0.199 LSB. The maximum INL is 0.24 LSB and the minimum INL is -0.413 LSB. The SNDR is 57.87 dB and the ENOB is 9.32 bits. The power consumption is about 60.6135mW.
34
Maleki, Mohammad. "Current-mode flash analog-to-digital converter." Thesis, 1992. http://hdl.handle.net/1957/37347.
Full textAbstract:
This thesis describes the development of a flash analog-to-digital converter based on
current-mode technique. The advantages of current -mode technique are higher speed,
smaller chip area, and simple division of reference current based on current mirror. A
current-mode comparator is designed consisting of a cascode current mirror and a
current sense amplifier used as a latch. The new method allows effective and simple
high-speed A/D conversion where the input is a current signal and the output of the
latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using
current sense amplifier comparator is designed and simulated in 1-micron CMOS
technology. Simulation results show that for ADC with resolution below six-bit, this
technique offers a comparable accuracy with the existing voltage-mode methods at
much higher speed.Graduation date: 1993
35
Lin, Kaih-Ping, and 林凱評. "High Speed Flash Analog to Digital Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/12280330170131356783.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
91
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. In this thesis, a flash ADC architecture is proposed to have 400 MHz samples rate with 6-bit resolution. We design the high speed architecture analog-to-digital converter by using two groups interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.80*1.10 mm2 with both powers of 3.3V and 2.5V. Experimentally, the chip can work up to 400 MHz as the input sample of 100 MHz sin-wave and has the differential nonlinearity is DNL<0.4 LSB, the integral nonlinearity is INL<1.0 LSB ,and the efficient number of 5.03 bits in practical applications. Moreover, we use two groups interleaved auto-zeroing technology for reducing the comparators capacitor value, so we can minimize the chip size and power consumption(152mA).
36
Lin, Jeff, and 林時毅. "Current-Cell Matrix Digital to Analog Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/27655992063157976458.
Full textAbstract:
碩士中華技術學院
電子工程研究所碩士班
96
This thesis proposes a new matrix digital to analog converter. All the results are simulated by TSMC 0.18m CMOS technology. The INL and DNL are 0.26 and 0.25 LSB for the 4 bit DAC, respectively. The INL and DNL are 0.23 and 0.25 LSB for the 8 bit DAC, respectively. The power consumption of 8-bit DAC is about 8.9mW. The proposed DAC also has advantages of simple encoder circuit to control current sources. It will decrease the size of circuit area. The DAC can also expand to more bit in the unit of 4 bits, for example, 8, 12 etc. It could be competitive with conventional matrix DAC.
37
Lin, Kai-Chie, and 林凱琪. "High Speed Flash Analog to Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56085018306124426889.
Full textAbstract:
碩士國立臺北科技大學
電腦通訊與控制研究所
90
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, colour, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. The designs of analog to digital converter are innovative and versatile to have higher speed, more accuracy and stability, along with low operating potential and low power consumption. Various types of circuits such as flash、folding、feedback、parallel and pipe-line, are constructed according to match their specific characteristics. In this thesis, a flash ADC architecture is proposed to have 400 Mega-sample per second with 6-bit sample length. We design the architecture by using group interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally affect its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.60*0.66 mm2 with both powers of 3V and 2.5V, 8461 MOS units, 449 resistors, and 147 capacitors. Experimentally, the chip can work up to 400 MHz as the input sample of 10 MHz sin-wave and has the efficient number of 5.76 bits in practical applications.
38
Sie, Ming-Jhou, and 謝明周. "4-Bit flash analog-to-digital converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60460902388790029068.
Full textAbstract:
碩士建國科技大學
電子工程系暨研究所
99
We use TSMC0.35μm2P 4M technology to design a positive feedback 3-bit 20MHz flash analog-to-digital converter and a 4-bit 1GHz flash analog-to-digital converter with hysteresis comparator. Reference potential was generated by resistor array, then compared with the input potential, and the resulting thermometer code pass through the pre-encoding circuit (1-out-of-N) and post-encoding circuit (Binary Code) after output. The 4-bit flash analog-to-digital-converter features working voltage range from 0.9 to 2.2 V, sampling rate of 1GHz, the power consumption is 5.158 mW and the chip layout area is 1.445×1.393mm . For 3-bit flash analog-to-digital converter, the working voltage ranges from 0 to 3.3 V, sampling rate of 20MHz, the power consumption is 2.2228mW and the chip layout area is 1.181 × 1.326 mm .
39
張雅惠. "Three Stages Pipelined Analog-to-Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/91927556524315407803.
Full textAbstract:
碩士國立海洋大學
電機工程學系
90
In this thesis, we design a 10-bit, 20Msamples/s, three stages pipelined analog-to-digital converter（ADC）. The converter consists of 3 stages with a resolution 4-b/stage with digital error correction. There are 48 comparators and 5 operational amplifiers. The main sub-circuits of the converter are sample-and-hold, 4-bit flash ADC, 4-bit digital-to-analog converter, subtractor, gain circuit, clock generator, encoder, register, digital error correction. The sample/hold circuit is implemented with switched-capacitor techniques. Switched-capacitor requires relative accurate capacitance not absolute accurate capacitance. It is therefore much easier to be fabricated for processing technology. The simulation results show that the overall circuit of ADC has 20MHz rate and 0.5LSB integral nonlinearity. The input range of ADC is from 0.85V to 2.45V. Power supply of 3.3V is used for this ADC chip. The power dissipation of the ADC is about 280mW. Total layout area is about 1800 1800μm2. The converter is fabricated with TSMC 0.25μm 1P5M CMOS technology.
40
Lin, Wu-Chun, and 林武駿. "BIST Design for Digital-to-Analog Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/20062653928383984705.
Full textAbstract:
碩士長庚大學
電子工程研究所
94
In the testing of DAC, BIST (built-in self test) is more suitable for SoC (system on chip) due to its easy observation and better controllability that ca reduce testing time and cost. In the present paper, we have designed a new DAC BIST; basing on the investigation of K. Arabi’s work, we used a RVG (reference voltage generator) to improve the issue of huge demand on external voltage references; and designed a subtract module circuits, to get the DAC close together two difference values of conversion voltageses. It can complete the offset error, gain error, differential nonlinearity error, integral nonlinearity error test.
41
Li, Wei-Chen, and 李葦宸. "Analog-to-Digital Converter for Biomedical System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27398469135986334835.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
103
Ageing population is a commonly observed phenomenon in most developed countries all over the world. Electrical engineers have turned their attention from consumer products to application in biomedical. We design ADCs that are suitable for biomedical application under this trend. In chapter 2, the fundamentals of analog-to-digital converters is introduced. In chapter 3 of this thesis, a low power successive approximation register analog-to-digital converter (SAR ADC) using monotonic switching procedure to decrease the power consumption is presented. In chapter 4 of this thesis, a biomedical system on chip (SoC) for smart oral appliance is introduced. These chips are fabricated in UMC 0.18 um CMOS process and the measurement results will be shown.
42
劉人佑. "Analog-to-Digital Converter Design and Implementation." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t74j8c.
Full textAbstract:
碩士國立高雄應用科技大學
電子工程系
106
In integrated circuit mixed signal applications, Analog to digital converter is an indispensable block in recent years ,The way to process signals is dominated by digital signals, But the signal of nature is analog signal ,Therefore, the bridge between analog and digital signals is an analog digital converter. This paper proposes a pipeline analog digital converter suitable for signal imaging and wireless communication and a sigma delta modulator suitable for use in voice systems. The pipelined analog-to-digital converter is designed using a 1.5-bit/stage architecture. Digital error correction circuit can correct the error digital code caused by 1.5-bit/stage architecture ,The number of target bits can be output correctly ,In a system of pipelined analog-to-digital converters ,Reduced the difficulty of designing the comparator .The circuit is simulated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-um 1P6M, In the case of a pipeline analog analog converter Input 18MHz sine wave and 100-MS/s sampling frequency, the pre-simulation result signal to noise and distortion ratio (SNDR) is 7.91dB. The sigma delta modulator uses a 2nd-order architecture OSR=128 times and noise shaping technology, Enter a sine wave of 1068.115 Hz and a sampling frequency of 2.5 MS/s , The post-simulation result signal to noise and distortion ratio (SNDR) is 13.79dB.
43
Huang, Wei-Fu, and 黃韋富. "Circuits study of digital-to-analog converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/23095591417871366760.
Full textAbstract:
碩士國立彰化師範大學
資訊工程學系
101
This thesis presents a four-bit digital-to-analog converter and an eight-bit digital-to-analog converter,we use the operational amplifier in the form of negative feedback to get the reference voltage, since the reference voltage is different variations, half of the circuit,current and output voltages are also followed different variations,to achieve the digital-to-analog converter functions. We use the TSMC 0.35um 2P4M CMOS technology to achieve its circuit, In the differential nonlinearity error of less than 0.5LSB and cumulative nonlinearity error of less than 0.5LSB,this circuit voltage is 3.3V, operational amplifier,four bits digital-to-analog converter and eitht bits digital-to-analog converter power consumption were 1.66mW, 1.25mW and 26mW. Keyword: Operational amplifier,Digital-to-Analog converter,Differential nonlinearity error,Cumulative nonlinear error.
44
Chen, Wei-Ting, and 陳韋廷. "Study on Pipelined Analog-to-Digital Converter." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51675791182035218460.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
98
In this thesis, we design a 10-bit 50MHz and a 10-bit 100MHz pipelined analog-to-digital converters with TSMC 0.35m 2P4M mixed signal process technology at 3.3V supply voltage and TSMC 0.18m 1P6M Mixed Signal process technology at 1.8V power supply voltage, respectively. The ADC architecture consists of nine stages in this design. Particularly, we adopt the 1.5-bit per stage tepology for the first eight stages and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of on resistance for the input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Besides, in order to decrease noise effect, the whole circuit is designed by fully differential structure. According to Hspice simulation results, the designed pipelined ADCs can operate at 50MHz and 100MHz, respectively. The Signal-to-Noise and Distortion Ratio are 60.49dB and 61.06dB when the input frequency is 1MHz, and the effective numbers of bit are 9.76-bit and 9.85-bit. The power dissipation are 246.09mW and 91.06mW.
45
Chai, Yun, and 翟芸. "Low-Power Pipelined Analog-to-Digital Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/96980090139238975829.
Full textAbstract:
博士國立交通大學
電子研究所
101
With recent application on higher speed and higher integration capability of circuits; the trend is that the channel length of MOS transistor is smaller and the thickness of gate oxide also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and the operation voltage is also reduced. By the demand of integrating analog-to-digital con- verter with digital signal-processing system on one chip (SOC), a low-power low-voltage analog-to-digital converter is an important key factor in mixed signal system nowadays. Pipelined analog-to-digital converter is one of the most popular products in mixed- mode signal devices and instruments. Mainly applied in achieving high linearity and high accuracy simultaneously, such as WLAN in mobile communication systems cell phone HDTV portable computer and so on. A novel pipelined ADC structure is developed in this thesis. This work demonstrates the power efficiency when achieving high speed and high accuracy potential of pipelined ADC at the same time. This novel scheme is iiidifferent from conventional works both in system and circuits. The improved Pipelined analog-to-digital converter adopts a dual-path structure. It utilizes two separated analog-to-digital converter paths with inaccurate specifications to generate an equivalent high accurate signal value. By a large reducing of the accuracy required in this novel structure will achieve a low-power and low-voltage implement what we explore. The power is optimized by using dual path amplification technique. The coarse amplifier covers large swing, and fine amplifier handles residue with high preci- sion. Also, time-interleaving capacitor sets are utilized to increase amplification time of MDAC operation for power reducing. Furthermore, a dual-path opamp circuit is also used in this design. By utilizing the methods of feedforward and current-ratio to well place the pole and zero can realize an opamp with high dc gain and eliminate the com- pensation capacitor results in a low power design. Then, we employ this dual-path opamp incorporating with switched opamp technique in the dual-path pipelined analog-to-digital converter what we mentioned above. To make matters even more exciting, by the particu- lar structure of dual-path pipelined analog-to-digital converter, we can design this opamp under unusual specifications to attain to an attractive lower power value. This complete circuit is designed with a 65nm CMOS technology. Power supply volt- age is 1 V, input signal amplitude is 1.3 V pp , resolution is 10-bit, the maximum sampling frequency is 200MS/s. At Nyquist rate, the maximum power consumption is 5.37mW.
46
林恪弘. "High Speed Pipelined analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/96122617172240633713.
Full text
47
林佳柏. "Analog to Digital Converter for 802.11a WLAN." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/44836273821888351501.
Full textAbstract:
碩士中華大學
電機工程學系碩士班
91
Since network is more and more popular, people go on internet not just searching for information, but demanding for more bandwidth. However, we do not prepare the wired line and plug-in sockets in advance for network in the most buildings. For the convenience in the family and the incorporation, there comes the wireless network, and for the faster transmission rate, in 1999, IEEE standardization group proposed the new wireless local area networks (WLAN) standard, 802.11a, whose transmission rate can reach 54Mbps, and 108Mbps for the turbo mode. We firmly believe that IEEE 802.11a can be the major network standard in the future. In this thesis, we use TSMC0.25μm CMOS process to perform the design and simulation of pipelined analog-to-digital converter. From the simulation results by HSPICE, we can operate the sampling rate at 40MHz for single voltage source 2.5V by this architecture. We utilize fully differential mode architecture for sampling circuits and comparators, which is helpful to suppress the common mode noise effect. In addition, this architecture suffers less power dissipation and has better resistance to the process deviation by using the dynamic comparator, which is less sensitive for mismatching effect.
48
Xu, Chao Hui, and 徐朝輝. "A 1.2V CMOS analog to digital converter." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/48567119086417934709.
Full text
49
HUANG, ZHONG-MING, and 黃鍾明. "High accuracy analog-to-digital converter design." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/70530088960562951959.
Full text
50
Χρίστου, Χρίστος, and Τιμόθεος Τιμοθέου. "Μελέτη και σχεδίαση γραμμικού digital to analog converter." Thesis, 2010. http://nemertes.lis.upatras.gr/jspui/handle/10889/3111.
Full textAbstract:
Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC.
Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση της θεωρίας των πιθανοτήτων τα χαρακτηριστικά του απλού Ladder και χρησιμοποιήθηκαν για την εξαγωγή συμπερασμάτων που αφορούν στη γραμμικότητα της νέας δομής Ladder. Τα θεωρητικά αποτελέσματα επιβεβαιώθηκαν με εξομοιώσεις.
Τέλος, μία σχεδίαση σε φυσικό επίπεδο με την χρήση μόνο MOSFETS και CMOS τεχνολογίας (χωρίς την χρήση αντιστάσεων) σχεδιάσθηκε και εξομοιώθηκε στο Cadence ένας Ladder της νέας δομής.This Diploma Thesis studies on a new Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the University of Patras. The new DAC structure is based on the simple R2R ladder combining several of them in a 2-dimentional grid. As result a high linearity DAC is derived after a simple calibration procedure. The Diploma Thesis presents results on probability of the simple R2R Ladder, employs these results so as to forecast the linearity of the 2-dimentional Ladder, whereas confirms theoretical results with simulations. Finally, a DAC based on the 2-dimentional topology has been designed and simulated using Cadence, in the framework of this Diploma Thesis.