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Journal articles on the topic 'Digital-analog converter'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

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1

Melikyan, V. Sh, V. D. Hovhannisyan, M. T. Grigoryan, A. A. Avetisyan, and H. T. Grigoryan. "Real Number Modeling Flow of Digital to Analog Converter." Proceedings of Universities. Electronics 26, no. 2 (April 2021): 144–53. http://dx.doi.org/10.24151/1561-5405-2021-26-2-144-153.

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This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output signal’s voltage difference between RNM and SPICE models is less than 2 mV.

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2

Pandya, Priyesh, and Vikas Gupta. "Enhancing Analog to Digital Converter Resolution Using Oversampling Technique." International Journal of Engineering Research 3, no. 4 (April 1, 2014): 245–48. http://dx.doi.org/10.17950/ijer/v3s4/413.

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3

Evtikhiev, N. N., S. S. Karinskiĭ, D. I. Mirovitskiĭ, and V. T. Popkov. "Optoelectronic interferometric analog–digital converter." Soviet Journal of Quantum Electronics 17, no. 2 (February 28, 1987): 140–46. http://dx.doi.org/10.1070/qe1987v017n02abeh006544.

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4

Ivanov, Yu I. "Pulse-time digital-analog converter." Measurement Techniques 30, no. 8 (August 1987): 739–41. http://dx.doi.org/10.1007/bf00865654.

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5

Borisyuk, L. A., and S. U. Klimovich. "Logarithmic analog-to-digital converter." Measurement Techniques 32, no. 5 (May 1989): 398–401. http://dx.doi.org/10.1007/bf00866209.

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6

Groshev, V. Ya. "Functional analog-to-digital converter." Measurement Techniques 31, no. 6 (June 1988): 533–36. http://dx.doi.org/10.1007/bf00867520.

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7

Yang Wang, Yang Wang, Hongming Zhang Hongming Zhang, Yujie Dou Yujie Dou, and Minyu Yao Minyu Yao. "Experimental evaluation of resolution enhancement of a phase-shifted all optical analog-to-digital converter using an electrical analog-to-digital converter array." Chinese Optics Letters 11, no. 8 (2013): 082301–82303. http://dx.doi.org/10.3788/col201311.082301.

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8

Grechishnikov, V. M., and E. G. Komarov. "Increasing the information capacity of a fiber-optic multi-sensor converter of binary mechanical signals into electrical signals." Izmeritel`naya Tekhnika, no. 9 (2020): 15–23. http://dx.doi.org/10.32446/0368-1025it.2020-9-15-23.

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The design and operation principle of a multi-sensor Converter of binary mechanical signals into electrical signals based on a partitioned fiber-optic digital-to-analog Converter with a parallel structure is considered. The digital-to-analog Converter is made from a set of simple and technological (three to five digit) fiber-optic digital-to-analog sections. The advantages of the optical scheme of the proposed. Converter in terms of metrological and energy characteristics in comparison with single multi-bit converters are justified. It is shown that by increasing the number of digital-analog sections, it is possible to repeatedly increase the information capacity of a multi-sensor Converter without tightening the requirements for its manufacturing technology and element base. A mathematical model of the proposed Converter is developed that reflects the features of its operation in the mode of sequential time conversion of the input code vectors of individual fiber-optic sections into electrical analogues and the formation of the resulting output code vector.

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9

Lukić, Jelena, and Dragan Denić. "A Novel Design Of An NTC Thermistor Linearization Circuit." Metrology and Measurement Systems 22, no. 3 (September 1, 2015): 351–62. http://dx.doi.org/10.1515/mms-2015-0035.

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Abstract A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.

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10

Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

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11

Teani, Carlos Roberto Negräo, and Alberto Martins Jorge. "Digital to analog converter nonlinear test." Nonlinear Analysis: Real World Applications 3, no. 1 (March 2002): 1–8. http://dx.doi.org/10.1016/s0362-546x(99)00107-8.

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12

Short, Robert Townsend. "Variable rate analog-to-digital converter." Journal of the Acoustical Society of America 126, no. 1 (2009): 517. http://dx.doi.org/10.1121/1.3182973.

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13

Sandell, R. D., B. J. Dalrymple, and A. D. Smith. "An SFQ digital to analog converter." IEEE Transactions on Appiled Superconductivity 7, no. 2 (June 1997): 2468–71. http://dx.doi.org/10.1109/77.621739.

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14

Luschas, S., R. Schreier, and Hae-Seung Lee. "Radio frequency digital-to-analog converter." IEEE Journal of Solid-State Circuits 39, no. 9 (September 2004): 1462–67. http://dx.doi.org/10.1109/jssc.2004.829377.

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15

Abdollahi, S. R., H. S. Al-Raweshidy, and T. J. Owens. "Pipelined photonic analog-to-digital converter." Journal of Optics 20, no. 9 (August 23, 2018): 095803. http://dx.doi.org/10.1088/2040-8986/aad922.

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16

Miller, D. L., J. X. Przybysz, J. Kang, C. A. Hamilton, and D. M. Burnell. "Josephson counting analog-to-digital converter." IEEE Transactions on Magnetics 27, no. 2 (March 1991): 2761–64. http://dx.doi.org/10.1109/20.133783.

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17

KALKUR, T. S., MIKE D'AMICO, and GREG PAULS. "POLARIZATION SWITCHING ANALOG TO DIGITAL CONVERTER." Integrated Ferroelectrics 81, no. 1 (August 17, 2006): 181–86. http://dx.doi.org/10.1080/10584580600660405.

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18

Groshev, V. Ya. "Analog-digital double integration converter (ADDIC)." Measurement Techniques 30, no. 3 (March 1987): 207–10. http://dx.doi.org/10.1007/bf00867055.

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19

Yu, Bo, Yi-Fei Pu, and Qiu-Yan He. "Fractional-Order Dual-Slope Integral Fast Analog-to-Digital Converter with High Sensitivity." Journal of Circuits, Systems and Computers 29, no. 05 (August 5, 2019): 2050083. http://dx.doi.org/10.1142/s0218126620500838.

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The dual-slope integral analog-to-digital converter is widely used in low-speed, high-precision measurement owing to its high precision and strong resistance on crosstalk interference. To meet the requirements of higher accuracy and faster measurement, the integral sensitivity and conversion speed of the dual-slope integral analog-to-digital converter must be improved. Therefore, based on fractional-order calculus, we propose a fractional-order dual-slope integral analog-to-digital converter. First, constant-current charging curves were provided to explain the source of the idea of the fractional-order dual-slope integral analog-to-digital converter. Then, the working principle of the fractional-order dual-slope integral analog-to-digital converter is described in detail. The calculation formula of analog-to-digital conversion is derived and analyzed. Moreover, the relationship of the voltage-measurement error with the operation-order error of the fractor and the reference voltage error is theoretically derived. Furthermore, we theoretically analyze the resistance of the proposed analog-to-digital converter to crosstalk interference, as well as the requirements for the first fractional integral time when crosstalk interference is suppressed. Specifically, we prove that the proposed analog-to-digital converter has a higher sensitivity and conversion speed than the classical converter, and we provide a quantitative calculation formula.

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20

Quenzer-Hohmuth, Samuel, Thoralf Rosahl, Steffen Ritzmann, and Bernhard Wicht. "Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications." Advances in Radio Science 14 (September 28, 2016): 85–90. http://dx.doi.org/10.5194/ars-14-85-2016.

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Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

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21

Kamaruzaman, Muhammad Syafiee, Nabihah Ahmad, Siti Hawa Ruslan, Hasmayadi Abdul Majid, C. Y. Chia, Nur Zazmera Mustafa Kamal, and Matthew Khoo Kah Wen. "Design of high-resolution digital-to-analog converter for 14-bit successive approximation analog-to-digital converter." Journal of Physics: Conference Series 1529 (May 2020): 052101. http://dx.doi.org/10.1088/1742-6596/1529/5/052101.

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22

Metodiev, Konstantin. "Data logging by AD7656 analog to digital converter." Aerospace Research in Bulgaria 30 (2018): 163–69. http://dx.doi.org/10.3897/arb.v30.e14.

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In the paper hereby, an exemplary algorithm of data logging by means of Analog Devices’ AD7656 analog to digital converter is presented. Converted data are transmitted further to ATmega644P microcontroller unit through Serial Peripheral Interface. The microcontroller, in turn, sends data to a PC through FTDI’s FT232 UART to USB chip. What motivates the current study is a source code development for the microcontroller unit. The source code is available for download at the quoted link. The main technique used in the code is external interrupt. The development environment used is MikroC Pro for AVR. The presented study is a part of software developed for project “Resonance”.

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23

Afonin, Sergey. "Characteristics of Nanopositioning Electroelastic Digital-to-Analog Converter for Communication Systems." Transactions on Networks and Communications 8, no. 6 (December 31, 2020): 35–44. http://dx.doi.org/10.14738/tnc.86.9699.

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The characteristics of the nanopositioning electroelastic digital-to-analog converter for communication systems are examined. In the static and dynamic regimes this characteristics are received. The static strain and control characteristics of the nanopositioning electroelastic digital-to-analog converter are obtained. The transfer function of the nanopositioning electroelastic digital-to-analog converter is received.

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24

Jalali, B., and Y. M. Xie. "Optical folding-flash analog-to-digital converter with analog encoding." Optics Letters 20, no. 18 (September 15, 1995): 1901. http://dx.doi.org/10.1364/ol.20.001901.

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25

Cruz Serra, A., F. Alegria, R. Martins, and M. Fonseca da Silva. "Analog-to-digital converter testing—new proposals." Computer Standards & Interfaces 26, no. 1 (January 2004): 3–13. http://dx.doi.org/10.1016/s0920-5489(03)00057-6.

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26

Sandell, R. D., D. J. Durand, B. J. Dalrymple, and T. Pham. "Counting SFQ analog to digital converter results." Computer Standards & Interfaces 21, no. 2 (June 1999): 114. http://dx.doi.org/10.1016/s0920-5489(99)91984-0.

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27

Sandell, R. D., D. J. Durand, B. J. Dalrymple, and T. Pham. "Counting SFQ analog to digital converter results." IEEE Transactions on Appiled Superconductivity 7, no. 2 (June 1997): 3298–300. http://dx.doi.org/10.1109/77.622060.

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28

Rathore, Tejmal S. "A Novel Ladder Digital to Analog Converter." IETE Journal of Education 40, no. 1-2 (January 1999): 21–22. http://dx.doi.org/10.1080/09747338.1999.11415691.

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29

Bruce, J. W. "Nyquist-rate digital-to-analog converter architectures." IEEE Potentials 20, no. 3 (2001): 24–28. http://dx.doi.org/10.1109/45.954534.

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30

Baccigalupi, A., and M. D'Apuzzo. "Analog-to-digital converter modeling: a survey." Measurement 19, no. 3-4 (November 1996): 139–46. http://dx.doi.org/10.1016/s0263-2241(97)00009-2.

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31

Nadeem, S., C. G. Sodini, and Hae-Seung Lee. "16-channel oversampled analog-to-digital converter." IEEE Journal of Solid-State Circuits 29, no. 9 (1994): 1077–85. http://dx.doi.org/10.1109/4.309903.

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32

Kang, J. U., M. Y. Frankel, and R. D. Esman. "Highly parallel pulsed optoelectronic analog-digital converter." IEEE Photonics Technology Letters 10, no. 11 (November 1998): 1626–28. http://dx.doi.org/10.1109/68.726771.

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33

Andreev, Mikhail, Aleksey Suvorov, and Aleksey Khlebov. "Mathematical simulation of analog-to-digital converter." MATEC Web of Conferences 141 (2017): 01040. http://dx.doi.org/10.1051/matecconf/201714101040.

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34

Jang, Ju-Seog, Sang-Yung Shin, and Soo-Young Lee. "Optical neural-net analog-to-digital converter." Optics Letters 14, no. 3 (January 15, 1989): 159. http://dx.doi.org/10.1364/ol.14.000159.

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35

Walden, R. H. "Analog-to-digital converter survey and analysis." IEEE Journal on Selected Areas in Communications 17, no. 4 (April 1999): 539–50. http://dx.doi.org/10.1109/49.761034.

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36

Al-Ali, A. R., M. T. Abuelma'atti, and A. Shabra. "An OTA-Based Digital-To-Analog Converter." Active and Passive Electronic Components 16, no. 3-4 (1994): 141–43. http://dx.doi.org/10.1155/1994/21258.

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A simple circuit for implementing a current-switching digital-to-analog converter is presented. The circuit uses operational transconductance amplifiers (OTAs) for switching a number of equal-value current sources. An R-2R ladder attenuator is used to scale the currents in a binary form. Experimental results show good performance.

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37

FURUTA, F., K. SAITOH, A. YOSHIDA, and H. SUZUKI. "Superconductor/Semiconductor Hybrid Analog-to-Digital Converter." IEICE Transactions on Electronics E91-C, no. 3 (March 1, 2008): 356–63. http://dx.doi.org/10.1093/ietele/e91-c.3.356.

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38

Anderson, C. J. "Josephson look-back analog to digital converter." IEEE Transactions on Applied Superconductivity 3, no. 1 (March 1993): 2769–73. http://dx.doi.org/10.1109/77.233507.

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39

Luong, H., D. Hebert, and T. Van Duzer. "Fully parallel superconducting analog-to-digital converter." IEEE Transactions on Applied Superconductivity 3, no. 1 (March 1993): 2633–36. http://dx.doi.org/10.1109/77.233968.

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40

Robertazzi, R. P., and S. V. Rylov. "Synchronous flux quantizing analog-to-digital-converter." IEEE Transactions on Appiled Superconductivity 3, no. 4 (1993): 3114–16. http://dx.doi.org/10.1109/77.251811.

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41

Rathore, T. S. "Generalized Inverted Ladder Digital-to-Analog Converter." Circuits, Systems, and Signal Processing 38, no. 3 (August 14, 2018): 1374–84. http://dx.doi.org/10.1007/s00034-018-0917-2.

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42

AL-Tamimi, Karama M., and Kamal El-Sankary. "Preweighted Linearized VCO Analog-to-Digital Converter." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 6 (June 2017): 1983–87. http://dx.doi.org/10.1109/tvlsi.2017.2661754.

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43

Liao, Xiao-jun, and Ya-pei Yang. "Optical-spectrum-encoded analog-to-digital converter." Optoelectronics Letters 3, no. 3 (May 2007): 227–30. http://dx.doi.org/10.1007/s11801-007-6157-5.

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44

Yang, Yu Jun, Wei Hu, Jun Liu, Zhou Yu, Dong Bing Fu, and Guang Bing Chen. "Design of a 10 Bit 2GHz Digital to Analog Converter Circuit." Applied Mechanics and Materials 713-715 (January 2015): 942–45. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.942.

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This paper presents the design of a 10 bit 2GHz digital to analog converter circuit. The digital to analog converter circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 4 GHz. The SFDR of the digital to analog converter circuit can reach 62dB (simulation work at 2 GHz), the SFDR can reach 45 dB (simulation work at 4 GHz). Early product parameters of the digital to analog converter circuit (working in 1 GHz sampling frequency) are as follows: the narrowband SFDR parameter can be achieved 81 dB, broadband SFDR parameters can reach 46 dB.

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45

Skup, Konrad, Paweł Grudziński, and Piotr Orleański. "Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters." International Journal of Electronics and Telecommunications 57, no. 1 (March 1, 2011): 77–83. http://dx.doi.org/10.2478/v10177-011-0011-1.

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Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

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46

Guang Yang, Guang Yang, Weiwen Zou Weiwen Zou, Ye Yuan Ye Yuan, and Jianping Chen Jianping Chen. "Wideband signal detection based on high-speed photonic analog-to-digital converter." Chinese Optics Letters 16, no. 3 (2018): 030601. http://dx.doi.org/10.3788/col201816.030601.

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47

Wang, Yanyi, Kaihui Wang, Wen Zhou, and Jianjun Yu. "Photonic aided vector millimeter-wave signal generation without digital-to-analog converter." Chinese Optics Letters 19, no. 1 (2021): 011101. http://dx.doi.org/10.3788/col202119.011101.

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48

Hayashi, Satoshi, Ryo Suzuki, Takamoto Watanabe, Shigenori Yamauchi, Nobuyuki Taguchi, Sumio Masuda, and Takehiko Adachi. "Proposal of a Method to Improve Linearity of Time Analog to Digital Converter." IEEJ Transactions on Electronics, Information and Systems 135, no. 1 (2015): 35–36. http://dx.doi.org/10.1541/ieejeiss.135.35.

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49

Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (August 12, 2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

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Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.

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50

Ye, Mao, Yumei Zhou, Bin Wu, and Jianhua Jiang. "An optimized analog to digital converter for WLAN analog front end." Journal of Semiconductors 33, no. 4 (April 2012): 045008. http://dx.doi.org/10.1088/1674-4926/33/4/045008.

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