Relevant bibliographies by topics / Digital clock

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Digital clock'

Author: Grafiati
Published: 11 December 2022
Last updated: 31 July 2025

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Journal articles on the topic "Digital clock"

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Yu, Xinguo, Wan Ding, Zhizhong Zeng, and Hon Wai Leong. "Reading Digital Video Clocks." International Journal of Pattern Recognition and Artificial Intelligence 29, no. 04 (2015): 1555006. http://dx.doi.org/10.1142/s021800141555006x.

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This paper presents an algorithm for reading digital video clocks reliably and quickly. Reading digital clocks from videos is difficult due to the challenges such as color variety, font diversity, noise, and low resolution. The proposed algorithm overcomes these challenges by using the novel methods derived from the domain knowledge. This algorithm first localizes the digits of a digital video clock and then recognizes the digits representing the time of digital video clock. It is a robust three-step algorithm. The first step is an efficient procedure that directly identifies the region of the
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ARORA, ANISH, SHLOMI DOLEV, and MOHAMED GOUDA. "MAINTAINING DIGITAL CLOCKS IN STEP." Parallel Processing Letters 01, no. 01 (1991): 11–18. http://dx.doi.org/10.1142/s0129626491000161.

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A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2 log N bits each and guarantees convergence to identical values within N2 "triggers".
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Korvorst, Marjolein, Ardi Roelofs, and Willem J. M. Levelt. "Telling Time from Analog and Digital Clocks." Experimental Psychology 54, no. 3 (2007): 187–91. http://dx.doi.org/10.1027/1618-3169.54.3.187.

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Abstract. Does the naming of clocks always require conceptual preparation? To examine this question, speakers were presented with analog and digital clocks that had to be named in Dutch using either a relative (e.g., “quarter to four”) or an absolute (e.g., “three forty-five”) clock time expression format. Naming latencies showed evidence of conceptual preparation when speakers produced relative time expressions to analog and digital clocks, but not when they used absolute time expressions. These findings indicate that conceptual mediation is not always mandatory for telling time, but instead
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Qiao, Shi Quan, Xiu Qing Zhang, Meng Yang, and Shu Wang Chen. "Design of Digital Clock Based on SCM." Applied Mechanics and Materials 668-669 (October 2014): 822–25. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.822.

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The digital clock is the timing device by using of the digital circuit to implement the digital display for hours, minutes and seconds. Due to the development of the digital integrated circuit and the wide application of the quartz crystal oscillator, the accuracy of the digital clock is far more than the old clocks’. The control part of the design is SCM AT89C51, and the compiler environment is Keil. The software is developed with C language, and the simulation debugging is used Proteus. The digital clock is convenient to people’s production and life, and it expands the original time function
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Li, Wangtingli, Shuhui Li, Qingyan Zeng, and Chengxi Zhou. "A Review of Design of Digital Clock Based on Verilog HDL." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 289–97. http://dx.doi.org/10.54097/hset.v46i.7716.

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With the development of electronic technology, digital clocks have added many functions that facilitate people's lives, Digital electronic clock is a device that uses digital circuits to realize the digital display of time, minutes, and seconds. This paper mainly discusses how to use Verilog HDL to design a simple digital clock and realize the basic functions such as timing and display in the clock, as well as the platform and tools used. The circuit of the digital clock is divided into three modules, namely the frequency division module, counting module, and decoding display module. And the t
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Wang, Yilin. "Verilog-based digital clock design methodology." Theoretical and Natural Science 14, no. 1 (2023): 102–7. http://dx.doi.org/10.54254/2753-8818/14/20240902.

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A digital electronic clock is a sophisticated instrument that employs digital circuits to render the timehours, minutes, and secondsin a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clocks essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate t
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Dattel, Andrew R., Andrew Henry, Godfrey D’Souza, et al. "Analog and Digital Clock Refresher Training for Improvement in Identifying Aviation Traffic." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 63, no. 1 (2019): 131–35. http://dx.doi.org/10.1177/1071181319631163.

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Air traffic controllers frequently point out other airplanes using a clock analogy (e.g., “Traffic 10 o’clock,”). This study explored the extent to which young pilots, who grew up in the digital age, understand an analog clock metaphor. Fourteen pilots were randomly assigned to either an analog clock or a digital clock refresher training group. Participants flew a 15-minute flight scenario pretest. During the pretest, participants heard prerecorded announcements of potential traffic factors. After the pretest, the analog group viewed 100 slides of analog clocks and the digital group viewed 100
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Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, et al. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 bo
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Yu, Xinguo, Wu Song, Xiaopan Lyu, Bin He, and Nan Ye. "Reading Both Single and Multiple Digital Video Clocks Using Context-Aware Pixel Periodicity and Deep Learning." International Journal of Digital Crime and Forensics 12, no. 2 (2020): 21–39. http://dx.doi.org/10.4018/ijdcf.2020040102.

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This article presents an algorithm for reading both single and multiple digital video clocks by using a context-aware pixel periodicity method and a deep learning technique. Reading digital video clocks in real time is a very challenging problem. The first challenge is the clock digit localization. The existing pixel periodicity is not applicable to localizing multiple second-digit places. This article proposes a context-aware pixel periodicity method to identify the second-pixels of each clock. The second challenge is clock-digit recognition. For this task, the algorithms based a domain knowl
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Anandaraj, Praveen Raaj, Nasrul Humaimi Mahmood, Mohd Azhar Abdul Razak, and Nor Aini Zakaria. "Digital Chess Clock for Visually Impaired Players." Journal of Human Centered Technology 3, no. 1 (2024): 46–52. http://dx.doi.org/10.11113/humentech.v3n1.68.

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Visually impaired chess players usually have difficulties using a normal traditional or digital chess clock during chess tournaments. This research aims to provide a solution which is a digital chess clock with an audio output indicating the remaining time of the chess players. These chess clocks are designed with Arduino Uno as the processing board with LCD keypad shield as display displaying and controlling and setting the hours, minutes, and seconds of the time. Besides that, the chess clock is equipped with a few mini pushbuttons to switch the time between the players together with two pus
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Dissertations / Theses on the topic "Digital clock"

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Figueroa, Álvarez Joaquín. "Clock gatting for latch based design." Tesis, Universidad de Chile, 2012. http://www.repositorio.uchile.cl/handle/2250/111407.

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Ingeniero Civil Electricista<br>Los circuitos digitales, que juegan un papel crucial en la vida cotidiana, consumen grandes cantidades de potencia lo que es considerado como una situación no deseada, lo que es particularmente cierto para equipos que dependen de baterías como celulares, es por esto que los diseñadores de circuitos así como las herramientas de síntesis utilizan diferentes técnicas con el fin de reducir su consumo de potencia. Una de las técnicas de reducción de potencia mas exitosas es clock-gating cuyo objetivo es reducir el consumo de potencia generado por las transiciones d
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Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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Smithson, Paul Michael. "Rapid clock recovery algorithms for digital magnetic recording and data communications." Thesis, University of Plymouth, 1999. http://hdl.handle.net/10026.1/2635.

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Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-98662.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm
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Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Technische Universität Dresden, 2006. https://tud.qucosa.de/id/qucosa%3A26194.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm
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Gong, Jianping. "Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/557.

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Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an accept
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Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Alimadadi, Mehdi. "Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/1447.

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Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy th
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Souillard-Mandar, William. "Learning classification models of cognitive conditions from subtle behaviors in the digital Clock Drawing Test." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100623.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 91-95).<br>The Clock Drawing Test -- a simple pencil and paper test -- has been used for more than 50 years as a screening tool to differentiate normal elderly individuals from those with cognitive impairment, and has proven
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Books on the topic "Digital clock"

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Shmaliy, Yuriy S. GPS-based optimal FIR filtering of clock models. Nova Science Publishers, 2009.

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Shmaliy, Yuriy S. GPS-based optimal FIR filtering of clock models. Nova Science Publishers, 2009.

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Calvert, John R. Design of a synchronous pipelined multiplier and analysis of clock skew in high-speed digital systems. Naval Postgraduate School, 2000.

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Sadayasu, Ono, and Eskelinen Pekka, eds. Digital clocks for synchronization and communications. Artech House, 2003.

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White, Ron. Click!: The no-nonsense guide to digital cameras. McGraw-Hill/Osborne, 2003.

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Keith, Anderson, ed. Click 2 save: The digital ministry bible. Morehouse Pub., 2012.

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Davis, Jack. Adobe Photoshop elements 2: One-click wow! Peachpit Press, 2004.

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ill, Halsey Megan, ed. Telling time: How to tell time on digital and analog clocks! Charlesbridge, 2000.

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Chen, Yuanming. Dui, dou shi shou ji pai de!: Cellphone photography whole world in a simple click. Guang xi shi fan da xue chu ban she, 2017.

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Zvavanjanja, Cade. Beyond a click: Regional assessment on state of digital rights : southern Africa. Media Institute of Southern Africa Zimbabwe Chapter, 2019.

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Book chapters on the topic "Digital clock"

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de Arruda Mello, Darli Augusto, and Fabio Aparecido Barbosa. "Clock Recovery." In Digital Coherent Optical Systems. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-66541-8_7.

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Taraate, Vaibbhav. "Multiple Clock Domain Design." In Digital Logic Design Using Verilog. Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2791-5_13.

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Goheer, Nabeel. "Clock, Cloud, and Contestation." In Digital Diplomacy and International Organisations. Routledge, 2020. http://dx.doi.org/10.4324/9781003032724-8.

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Taraate, Vaibbhav. "Multiple Clock Domain Design." In Digital Logic Design Using Verilog. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3199-3_22.

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Xu, Chong-wei. "Animation Programming: A Digital Clock and an Analog Clock." In Learning Java with Games. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-72886-5_11.

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Saxena, Amit, Kshitij Shinghal, Rajul Misra, and Alok Agarwal. "Clock System Architecture for Digital Circuits." In International Conference on Intelligent Computing and Smart Communication 2019. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0633-8_134.

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Hoch, Ezra N., Danny Dolev, and Ariel Daliot. "Self-stabilizing Byzantine Digital Clock Synchronization." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-49823-0_25.

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Gaj, Kris, Eby G. Friedman, and Marc J. Feldman. "Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits." In High Performance Clock Distribution Networks. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4684-8440-3_11.

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Hsieh, Hong-Yean, Wentai Liu, Paul Franzon, and Ralph Cavin. "Clocking Optimization and Distribution in Digital Systems with Scheduled Skews." In High Performance Clock Distribution Networks. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4684-8440-3_3.

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Bonanno, Alberto, Alberto Bocca, Alberto Macii, Enrico Macii, and Massimo Poncino. "Data-Driven Clock Gating for Digital Filters." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9_14.

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Conference papers on the topic "Digital clock"

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Pan, Wenhao, Haiyue Yan, Liqiong Dai, Nan Chen, and Libin Yao. "High-speed clock generator for digital readout circuit." In Infrared Technology and Applications, edited by Xue Li and Xin Tang. SPIE, 2024. https://doi.org/10.1117/12.3048203.

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gao, qiaoling, and LiJun Wei. "The designing and production of the multisim-based digital clock." In International Conference on Electronics. Electrical and Information Engineering, edited by Shengqing Li and Bin Hu. SPIE, 2024. https://doi.org/10.1117/12.3052145.

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Yin, MeiSu, Qun Yin, Ji Gu, and Rui Luo. "Intelligent digital alarm clock." In 2018 IEEE 4th Information Technology and Mechatronics Engineering Conference (ITOEC). IEEE, 2018. http://dx.doi.org/10.1109/itoec.2018.8740479.

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Yamanaka, Masashi. "Design and Manufacturing Education Utilized Digital Engineering." In ASME 2007 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/detc2007-35177.

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The most effective method in design and manufacturing education is to experience the series of processes, which are to be given a design subject, the design of the machine to qualify the specification, to manufacture or buy necessary parts, the assembly and the evaluation of performance, by oneself or few people. Firstly, the items to learn and improve in the course for the attending student were listed up and examined. These become the evaluation items of the program by the attending student. The program called ‘Clock Project’ was developed. The subject is to design the clock that displays ‘h
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Zeidler, Steffen, Oliver Schrape, Anselm Breitenreiter, and Milos Krstic. "A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks." In 2020 23rd Euromicro Conference on Digital System Design (DSD). IEEE, 2020. http://dx.doi.org/10.1109/dsd51259.2020.00013.

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Zhang, Chao, Yongkang Liu, Tao Jiang, Weiming Mao, and Jing Wang. "Multisim-Based Digital Clock Design." In 2020 IEEE 9th Joint International Information Technology and Artificial Intelligence Conference (ITAIC). IEEE, 2020. http://dx.doi.org/10.1109/itaic49862.2020.9338902.

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Win, Khant, Alexey N. Yakunin, Aung Myo San, and Nyan Linn Phyo. "Digital Clock with Myanmar Digits." In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2020. http://dx.doi.org/10.1109/eiconrus49466.2020.9039003.

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Na, Taesik, Jong Hwan Ko, and Saibal Mukhopadhyay. "Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927229.

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Hamalainen, J. "Clock Rate Conversion for Digital Video." In SMPTE Television Conference. IEEE, 1991. http://dx.doi.org/10.5594/m00911.

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Guohai, Xiong. "Digital Clock Design Based on Nios." In 2006 8th international Conference on Signal Processing. IEEE, 2006. http://dx.doi.org/10.1109/icosp.2006.344447.

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Reports on the topic "Digital clock"

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Geller, J. A DIGITAL VOLTAGE to FREQUENCY CONVERTER for the BOOSTER GAUSS CLOCK. Office of Scientific and Technical Information (OSTI), 1990. http://dx.doi.org/10.2172/1150553.

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Chien, Stanley, Yaobin Chen, Lauren Christopher, Mei Qiu, and Zhengming Ding. Road Condition Detection and Classification from Existing CCTV Feed. Purdue University, 2022. http://dx.doi.org/10.5703/1288284317364.

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The Indiana Department of Transportation (INDOT) has approximately 500 digital cameras along highways in populated areas of Indiana. These cameras are used to monitor traffic conditions around the clock, all year round. Currently, the videos from these cameras are observed one-by-one by human operators looking for traffic conditions and incidents. The main objective of this research was to develop an automatic, real-time system to monitor traffic conditions and detect incidents automatically. The Transportation and Autonomous Systems Institute (TASI) of the Purdue School of Engineering and Tec
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Krivoi, Kallmeyer, and Baranyak. L52199 Nopig Metal-Loss Detection System for Non-Piggable-Pipelines. Pipeline Research Council International, Inc. (PRCI), 2005. http://dx.doi.org/10.55274/r0011343.

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This project investigated and upgraded the digital filtering used to interpret NoPig displacement data. This upgrade should allow the system to be used on long seam welded pipes. Limited laboratory testing was performed to show the improvement on ERW pipe. The NoPig method is a non-destructive testing method for unpiggable pipelines which uses above ground measurements for detecting and sizing wall thickness anomalies like corrosion. The method uses an applied current containing several distinct frequencies between two points on a pipeline up to 1 km apart. The resultant magnetic field is meas
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Phillips, Paul. The Adoption of Digital Twins in Integrated Vehicle Health Management. SAE International, 2023. http://dx.doi.org/10.4271/epr2023024.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;To many, a digital twin offers “functionality,” or the ability to virtually rerun events that have happened on the real system and the ability to simulate future performance. However, this requires models based on the physics of the system to be built into the digital twin, links to data from sensors on the real live system, and sophisticated algorithms incorporating artificial intelligence (AI) and machine learning (ML). All of this can be used for integrated vehicle health management (IVHM) decisions, such as determini
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Ahmed, Qadeer, and Vishnu Renganathan. Cybersecurity and Digital Trust Issues in Connected and Automated Vehicles. SAE International, 2024. http://dx.doi.org/10.4271/epr2024009.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Given the rapid advancements in engineering and technology, it is anticipated that connected and automated vehicles (CAVs) will soon become prominent in our daily lives. This development has a vast potential to change the socio-technical perception of public, personal, and freight transportation. The potential benefits to society include reduced driving risks due to human errors, increased mobility, and overall productivity of autonomous vehicle consumers. On the other hand, the potential risks associated with CAV deploy
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Kemper, Bart. Developing the Role of the System Software Integrator to Mitigate Digital Infrastructure Vulnerabilities. SAE International, 2023. http://dx.doi.org/10.4271/epr2023028.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Traditional physical infrastructure increasingly relies upon software. Yet, 75% of software projects fail in budget by 46% and schedule by 82%. While other systems generally have a “responsible-in-charge” (RIC) professional, the implementation of a similar system of accountability in software is not settled. This is a major concern, as the consequences of software failure can be a matter of life-or-death. Further, there has been a 742% average annual increase in software supply chain attacks on increasingly used open-sou
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Wiseman, Jane. Innovations in Public Service Delivery: Issue No. 5: Improving Service Delivery through Information Integration: Building a Single View of the Citizen. Inter-American Development Bank, 2017. http://dx.doi.org/10.18235/0007030.

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So much of our daily business can be done with a swipe or a mouse click. Citizens have come to expect and rely on a certain amount of convenience in their daily lives as technology evolves to suit real-time individualized experiences of the marketplace. Those same expectations of ease of use and customized experience transfer to the citizen experience of government. In general, government is not moving as quickly as the private sector to embrace technology trends. Yet, there are promising examples of digital government where the citizen is at the center of the process. Embracing these emerging
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Abdul Hamid, Umar Zakir. User Experience for Digitalized and Smart Cockpits and Cabins of Next-gen Mobility. SAE International, 2025. https://doi.org/10.4271/epr2025006.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;This SAE Edge Research Report explores advancements in next-generation mobility, focusing on digitalized and smart cockpits and cabins. It offers literature review, examining current customer experiences with traditional vehicles and future mobility expectations. Key topics include integrating smart cockpit and cabin technologies, addressing challenges in customer and user experience (UX) in digital environments, and discussing strategies for transitioning from traditional vehicles to electric ones while educating custom
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Coyner, Kelley, and Jason Bittner. Automated Vehicles and Infrastructure Enablers: Cybersecurity. SAE International, 2024. http://dx.doi.org/10.4271/epr2024018.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;While weaponizing automated vehicles (AVs) seems unlikely, cybersecurity breaches may disrupt automated driving systems’ navigation, operation, and safety—especially with the proliferation of vehicle-to-everything (V2X) technologies. The design, maintenance, and management of digital infrastructure, including cloud computing, V2X, and communications, can make the difference in whether AVs can operate and gain consumer and regulator confidence more broadly. Effective cybersecurity standards, physical and digital security
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10

Coyner, Kelley, and Jason Bittner. Automated Vehicles and Infrastructure Enablers: Connectivity. SAE International, 2023. http://dx.doi.org/10.4271/epr2023013.

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&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Do connected vehicle (CV) technologies encourage or dampen progress toward widespread deployment of automated vehicles? Would digital infrastructure components be a better investment for safety, mobility, and the environment? Can CVs, coupled with smart infrastructure, provide an effective pathway to further automation? Highly automated vehicles are being developed (albeit slower than predicted) alongside varied, disruptive connected vehicle technology. &lt;/div&gt;&lt;div class="htmlview paragraph"&gt;&lt;b&gt;Automated
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