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Dissertations / Theses on the topic 'Digital clock'

Author: Grafiati

Published: 11 December 2022

Last updated: 31 July 2025

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1

Figueroa, Álvarez Joaquín. "Clock gatting for latch based design." Tesis, Universidad de Chile, 2012. http://www.repositorio.uchile.cl/handle/2250/111407.

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Ingeniero Civil Electricista<br>Los circuitos digitales, que juegan un papel crucial en la vida cotidiana, consumen grandes cantidades de potencia lo que es considerado como una situación no deseada, lo que es particularmente cierto para equipos que dependen de baterías como celulares, es por esto que los diseñadores de circuitos así como las herramientas de síntesis utilizan diferentes técnicas con el fin de reducir su consumo de potencia. Una de las técnicas de reducción de potencia mas exitosas es clock-gating cuyo objetivo es reducir el consumo de potencia generado por las transiciones d

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2

Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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3

Smithson, Paul Michael. "Rapid clock recovery algorithms for digital magnetic recording and data communications." Thesis, University of Plymouth, 1999. http://hdl.handle.net/10026.1/2635.

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4

Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-98662.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm

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5

Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Technische Universität Dresden, 2006. https://tud.qucosa.de/id/qucosa%3A26194.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm

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6

Gong, Jianping. "Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/557.

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Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an accept

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7

Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.

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8

Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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9

Alimadadi, Mehdi. "Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/1447.

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Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy th

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10

Souillard-Mandar, William. "Learning classification models of cognitive conditions from subtle behaviors in the digital Clock Drawing Test." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100623.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 91-95).<br>The Clock Drawing Test -- a simple pencil and paper test -- has been used for more than 50 years as a screening tool to differentiate normal elderly individuals from those with cognitive impairment, and has proven

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11

Ren, Saiyu Dr. "BROAD BANDWIDTH HIGH RESOLUTION ANALOG TO DIGITAL CONVERTERS: THEORY, ARCHITECTURE AND IMPLEMENTATION." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1205948819.

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12

Clauscen, Heidi M. "Exploring fraction knowledge with telling time : a case study of students who have learning difficulties." Thesis, Queensland University of Technology, 2016. https://eprints.qut.edu.au/102439/1/Heidi_Clauscen_Thesis.pdf.

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This research employed an intrinsic case study method to explore the mathematics knowledge, procedures, and strategies used by nine Year Four children who have learning difficulties (LD) to tell twelve-hour time on analogue and digital clocks. A specific focus was to examine the fraction knowledge as a factor contributing to the mastery of telling twelve-hour time on analogue and digital clocks. The research highlighted the children’s predominant use of mathematics knowledge linked to number and arithmetic only and argued that fraction knowledge is vital to telling twelve-hour time.

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13

Calvert, John R. "Design of a synchronous pipelined multiplier and analysis of clock skew in high-speed digital systems." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2000. http://edocs.nps.edu/npspubs/scholarly/theses/2000/Dec/00Dec_Calvert.pdf.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 2000.<br>Thesis advisors, Douglas J. Fouts, Herschel H. Loomis, Jr. Includes bibliographical references (p. 131). Also Available online.

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14

Panchangam, Ranganath. "MINIMIZATION OF POWER DISSIPATION IN DIGITAL CIRCUITS USING PIPELINING AND A STUDY OF CLOCK GATING TECHNIQUE." Master's thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4446.

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Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount

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Jung, Seok Min, and Seok Min Jung. "Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/621292.

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The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generat

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16

Elangovan, Vivek. "Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71029.

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The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital P

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17

Angeli, Nico [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Chihao [Akademischer Betreuer] Xu. "All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion / Nico Angeli ; Klaus Hofmann, Chihao Xu." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2020. http://d-nb.info/1216627509/34.

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18

Prasad, Rohit. "Characterization, Clock Tree Synthesis and Power Grid Dimensioning in SiLago Framework." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-247794.

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A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. First, power characterization of the flat design which was designed using the SiLago methodology. Second, designing a hierarchical clock tree and harden it inside the SiLago logic. Third, dimensioning hierarchical power grids. Out of these, clock

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19

Zhao, Xin. "Reliable clock and power delivery network design for three-dimensional integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45881.

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The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-

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20

Ostrander, Charles Nicholas. "Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit." Thesis, Montana State University, 2009. http://etd.lib.montana.edu/etd/2009/ostrander/OstranderC0509.pdf.

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The Periodic Event Synchronization Unit aligns devices without the ability to be triggered by an external source. The primary function of the unit is to align the pattern trigger pulses of two pulse pattern generators which supply four inputs of a multiplexer. The pulse pattern generators lack the ability to start their code according to an external signal. When operating, the designed unit maintains a specific pattern alignment of two binary data streams of 5 gigabits per second as a multiplexer combines them into a data stream of four times the bit rate. In addition to alignment, the uni

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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA-2019, 2019. https://doi.org/10.35598/mcfpga.2019.003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.

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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.

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23

Walter, Fábio Leandro. "Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/67848.

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Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperform

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24

Zhou, Dong. "Clock synchronization and dominating set construction in ad hoc wireless networks." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1131725177.

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25

Hordeski, Theodore J. Jr. "TUNABLE FSK/AM SIGNAL DETECTOR ON A 6U-VME CARD." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609677.

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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California<br>The telemetry and aerospace communities require communications equipment providing various modulation and demodulation formats. One format, with application in Space Ground Link Subsystems (SGLS), utilizes a Ternary (tri-tone) Frequency Shift-Keyed (FSK) signal Amplitude Modulated (AM) by a triangle waveform. Historically, SGLS equipment has operated with a fixed tri-tone frequency set (e.g., 65 kHz, 76 kHz and 95 kHz). The need for additional tr

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Neuberger, Gustavo. "Protecting digital circuits against hold time violations due to process variations." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12924.

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Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida d

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27

Shrestha, Amit [Verfasser], Viktor [Akademischer Betreuer] Krozer, Viktor [Gutachter] Krozer, and Lars [Gutachter] Hedrich. "SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization / Amit Shrestha ; Gutachter: Viktor Krozer, Lars Hedrich ; Betreuer: Viktor Krozer." Frankfurt am Main : Universitätsbibliothek Johann Christian Senckenberg, 2021. http://d-nb.info/1239729847/34.

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28

Bousselham, Abdel Kader. "FPGA based data acquistion and digital pulse processing for PET and SPECT." Doctoral thesis, Stockholm University, Department of Physics, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:su:diva-6618.

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<p>The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sam

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29

Chang, Zi-Feng, and 張誌峰. "Digital Clock and Data Recovery." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/61742183009078495426.

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碩士<br>國立高雄師範大學<br>電子工程學系<br>102<br>In recent years, with the advancement of VLSI technology as well as communication transmission technology and its services and applications, the high-speed digital technology is applied into various products, such as multimedia and wireless network. On the high-speed digital transmission systems, clock and data recovery technology in the receiver plays an important role to accurately recovery the data and clock. In this thesis, two clock data recovery approaches are proposed and implemented in FPGA system. The first one is three phase digital clock data recov

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30

Li, Chuang, and 莊立. "All Digital Spread Spectrum Clock Generator for Serial ATA Application & Digital Programmable Gaussian Clock Generator." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/88626364210484112620.

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碩士<br>國立交通大學<br>電子研究所<br>98<br>In the thesis, we focus on the AD-SSCG (All Digital Spread Spectrum Clock Generator) modulation method with input reference. In order to achieve higher frequency and less frequency deviation, we propose a new Domino modulation method. We can improve the modulated clock to 100MHz and 5000ppm of frequency deviation as compared to 23MHz modulated clock and 3% of frequency deviation is published before. In the architecture design, we propose a novel Coarse-Fine DDLi (Digital Delay Line) structure, it improve the power and area by 330% and 383% than traditional struct

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Lin, Sheng-You, and 林聖祐. "All-Digital Spread Spectrum Clock Generators." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/47483356873880492085.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>In a PC system, the speed of the center process unit (CPU) improves continuously. If the I/O interface is not able to improve simultaneously, the performance of the PC system will be limited. Therefore, high-speed I/O interface are becoming popular. As operating in high data rate, the high-frequency clock causes electromagnetic interference (EMI) which may affect the wireless communication system. Therefore, reduction of unnecessary EMI is a very important issue. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up

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32

Wang, Chih-Yong, and 王志傭. "Clock Synchronizer for High Speed Digital Systems." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/71191213067590937880.

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碩士<br>國立臺灣大學<br>電機工程學系<br>86<br>In this thesis, two architectures of the clock synchronizer that delivers synchronous clock to multiple targets in high-speed digital systems are realized. Based on the consept of delay locked loop, a digital controlled delay line is used to compensate for the various clock propagation delay caused by various environmental conditions.

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Chen, Wei-chieh, and 陳韋潔. "An All-Digital DLL-Based Clock Generator." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/97797653941694040274.

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碩士<br>大同大學<br>通訊工程研究所<br>99<br>In digital processing ICs, on-chip clock is an important signal for operation. Clock performance is relative to the speed and the performance of data process. Multiphase clocks are effective to speed the clock frequency. And multiphase clocks also have low jitter and low skew performance, because multiphase clock generator employs delay-locked loop as based architecture. This thesis present an all-digital DLL-based clock generator. The all-digital multiphase clock generator inculds a time-to-digital converter and a fixed step scheme of phase lock operation to imp

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34

Chang, Yijung, and 張益榮. "All Digital Programmable Spread Spectrum Clock Generator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/97107829115547828841.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>100<br>Continuing advance of the semiconductor process technology enable the successful realization of the System-on-a-Chip (SoC). The performance and the complexity of SOCs keep grow steadily. However, the signal routing complexity inside the chip itself as well as the level of electronic noise will also increase. To the best of our knowledge, the Electro Magnetic Interference (EMI) will gradually become an issue, since it will decrease the stability and reliability of a system. In order to alleviate this problem, shielding method has been adopted, but it has much

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Wu, Chia-Lin, and 吳佳霖. "All-Digital Reference Clock Generator for WBAN Applications." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/54331761591740126399.

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碩士<br>輔仁大學<br>電機工程學系碩士班<br>102<br>In this thesis, a wide range and a low power digitally controlled oscillator with low output frequency for wireless body area network (WBAN) are presented. The proposed digitally controlled oscillator not only can provide high resolution, but also can generate low frequency clock signal with low power consumption and low circuit complexity as compared with conventional approaches. 　　This thesis presents two different low-frequency digitally controlled oscillator architectures; the first proposed architecture employs a cascade-stage structure to achieve high re

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Shih, Po-Yuan, and 施博元. "An All-Digital Clock Synthesizer Based on MDLL." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85200613739280024861.

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碩士<br>國立雲林科技大學<br>電機工程系碩士班<br>101<br>Acquisition range of phase detector in the architecture of a conventional multiplying delay-locked loop (MDLL) is limited. In order to guarantee the correct lock-in process, the delay line must be initially reset to its minimal delay with an external signal. Therefore, it is difficult to change output frequency from low to high. This problem also restricts the application of the MDLL. In this thesis, we propose a clock synthesizer based on all-digital multiplying delay-locked loop architecture to solve the constraint of the conventional architecture. The p

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Chen, I.-Fong, and 陳易楓. "All-digital Clock and Data Recovery and All-digital Phase-locked Loop." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/72656359516188540808.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>In recent years, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery. In this thesis, a 1.25 Gbps all-digital clock and data recovery is proposed. The clock frequency of t

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Ku, Shih-Han, and 古識涵. "All-Digital Spread Spectrum Clock Generator with Self-Calibrated Bandwidth and De-Spreading Clock Generator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/60579481811890740069.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>This thesis focuses on the research of a spread-spectrum method as well as a de-spreading method. Two topics of these chips are named as an all-digital spread-spectrum clock generator with self-calibrated bandwidth and an all-digital de-spreading clock generator for DisplayPort. They are both fabricated in a 0.18um CMOS process and implemented in an all-digital manner. In contrast to those area-consuming analog filter implementation, these proposed circuits implement the necessary filtering function in a digital way, which achieve a low-cost solution owing to

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Yi-Pei, Su. "An Analog-to-Digital Converter with DLL Clock Generator." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2607200618454500.

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40

"A 1.0 [mu]m CMOS all-digital clock multiplier." 1997. http://library.cuhk.edu.hk/record=b5889119.

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by Cheng King Sum Frankie.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references (leaf 53).<br>Acknowledgments --- p.iv<br>List of Figures --- p.vii<br>List of Tables --- p.ix<br>Abstract --- p.x<br>Chapter Chapter1 --- Introduction --- p.1<br>Chapter 1.1 --- Multiple Clock System --- p.1<br>Chapter 1.2 --- Clock Multiplier --- p.2<br>Phase-Locked Loop --- p.2<br>Delay Locked Loop --- p.3<br>Chapter 1.3 --- Objective --- p.5<br>Chapter Chapter2 --- All-Digital Clock Multiplier --- p.6<br>Chapter 2.1 --- Architecture --- p.6<br>Chapter 2.

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Chen, Wei-Hao, and 陳威豪. "Design of Clock Generator Based on All-Digital MDLL." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/trgda3.

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碩士<br>國立雲林科技大學<br>電機工程系<br>103<br>With the advances of the technology, the integrated circuits are widely applied in our daily life. Due to the continual progress of process technologies, the high-speed clock generators and synthesizers demand more the products of the market. With the aid of the merits of delay-locked loop (DLL), this thesis proposes a clock generator based on all-digital multiplying delay-locked loop (AD-MDLL). The detection range problem in AD-MDLL is resolved by a new digital phase detector. The edge-selecting function is also achieved with the aid of the improved select lo

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Su, Cheng-Dow, and 蘇承道. "An All Digital PLL for Spread Spectrum Clock Generator." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/11880378867304784395.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>Recent advances in integrated circuit (IC) technology make fabrication processes very suitable for digital design. In order to satisfy the market requirement, small area and low voltage designs are mandated nowadays. It is easy to redesign with process changes for digital designs. The all-digital phase-locked loop (ADPLL), one of the most recent and significant advancements in the integrated circuits, offers the remarkable advantage of replacing the charge pump and the loop filter with digital loop filter. The spread spectrum clock generator (SSCG) can be appl

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Su, Yi-Pei, and 蘇逸霈. "An Analog-to-Digital Converter with DLL Clock Generator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/85002929584774695167.

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Su, Ming-Chiuan, and 蘇明銓. "Burst Mode Clock/Data Recovery and All-Digital Spread-Spectrum Clock Generator for Serial Link System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/37535487725559157454.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>In modern times, the process technology node has advanced toward small feature size with low power consumption and high operation speed to per the demand on the enormous amount of data computation and communication among individual system-on-chip (SoC). The high-speed interface specifications have evolved toward multi-Gbps data rate as well as low-jitter and energy-efficient (~1pJ/bit) concerns. The transmitter (TX) utilizes spread-spectrum clock generator for the purpose of suppressing the electro-magnetic interference (EMI). The digitally-controlled osc

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Guo, Li-Wei, and 郭力瑋. "An All-Digital Burst-Mode Clock and Data Recovery Circuit." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/10191076709367380635.

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碩士<br>國立雲林科技大學<br>電機工程系碩士班<br>102<br>This thesis presents the work of an all-digital half-rate burst-mode clock and data recovery circuit (CDR). Since it possesses the capability of realigning the recovered clock from the input data, this clock and data recovery circuit can be used to retiming the data which transmit under burst-mode. It can operate at the half-rate mode, so the frequency of recovered clock can be only half of the bit rate of data. With the aid of the all-digital mechanism, the frequency of the oscillator is controlled by a set of binary codes. The MSB of this binary code is d

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Fan, Chi-Wei, and 范啟威. "Clock Jitter Measurement and Compensation for Analog-to-Digital Converters." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/59549665262682053701.

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博士<br>國立交通大學<br>電子研究所<br>99<br>In a modern communication receiver, the received continuous-time analog signal is quantized into a discrete-time digital sequence by an analog-to-digital converter (ADC) so that the complex signal processing can be performed in the digital domain. The ADC requires a periodic clock as a timing reference for input sampling. If the sampling clock exhibits jitter, the ADC suers from sampling errors and its signal-to-noise ratio (SNR) performance is degraded. For a low-speed low-resolution ADC, the sampling error due to clock jitter is not crucial. As the progress of

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Fan, Wen-Teng, and 范文騰. "A PLL-Based Clock Generator with Digital Frequency Tracking Scheme." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/20864549583446749662.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>The goal of this thesis is to design and improve a PLL-based clock generator, a clock generator for DVD/Audio system. The system master clock(MCLK) is the input reference signal of the clock generator and its frequency range is from 4.096MHz to 73.728MHz. Besides, the clock generator has corresponding frequency multiplication such as four, two and one, according to the different input frequency band. The output frequency range is from 16.384MHz to 73.728MHz. In this thesis, two PLL-based clock generators are designed. 　　According to PLL design technique, we

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Xue, Jing-Wen, and 薛景文. "A PLDCO-based FLL for All Digital Clock Recovery Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/06065086292931122381.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>This thesis is based on a new frequency locked loop(FLL) circuit for all digital clock recovery circuit called the PLDCO- based FLL circuit . The piecewise linear digital controlled oscillator(PLDCO) which is a modified version of the digital control oscillator(DCO) is the heart of this proposed circuit. The PLDCO has features of small mode transistion jitter,simple control algorithm and has the same jitter of each nearby contrl wordtransition. A propotype

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Su, Ming-Chiuan, and 蘇明銓. "All Digital Phase-Locked Loop for Spread-Spectrum Clock Generator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/43743861319797682304.

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碩士<br>國立交通大學<br>電子工程系所<br>98<br>Abstract As SOC(System On Chip) works with increasing internal reference clocks, the spread-spectrum clocking technique is used to mitigate EMI(Electro-Magnetic Interference) effect. Conventional analog PLLs are likely to be affected by PVT (process/voltage/temperature) variations. Hence, when using deep-submicron CMOS process, PLLs are prone to all-digital design. All-digital PLL consists of bang-bang PFD, accumulator-based digital loop filter, differential DCO and divider. Bang-bang PFD generates phase compare signals to control accumulator-based digital loop

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Jeng, Wei-Young, and 鄭惟陽. "The Design of All-Digital Cyclic Clock De-skew Buffer." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/89492893972447883390.

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碩士<br>雲林科技大學<br>電機工程系碩士班<br>97<br>This thesis presents an all-digital Cyclic Delay-Locked Loop. Generally Delay-Locked Loop can be divided into two kinds of digital and analog. For Digital model, the advantages are: high speed in operation, larger delay range and much better noise suppression. For Analog model, the advantages are: high resolution for delay time, low-jitter and small power consumption, the disadvantages are: larger locking time and easily sensitive to the process, voltage, and temperature variations. Generally Digital Delay-Locked Loop’s operation range is limited by the delay

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