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Journal articles on the topic 'Digital clock'

Author: Grafiati

Published: 11 December 2022

Last updated: 31 July 2025

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1

Yu, Xinguo, Wan Ding, Zhizhong Zeng, and Hon Wai Leong. "Reading Digital Video Clocks." International Journal of Pattern Recognition and Artificial Intelligence 29, no. 04 (2015): 1555006. http://dx.doi.org/10.1142/s021800141555006x.

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This paper presents an algorithm for reading digital video clocks reliably and quickly. Reading digital clocks from videos is difficult due to the challenges such as color variety, font diversity, noise, and low resolution. The proposed algorithm overcomes these challenges by using the novel methods derived from the domain knowledge. This algorithm first localizes the digits of a digital video clock and then recognizes the digits representing the time of digital video clock. It is a robust three-step algorithm. The first step is an efficient procedure that directly identifies the region of the

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ARORA, ANISH, SHLOMI DOLEV, and MOHAMED GOUDA. "MAINTAINING DIGITAL CLOCKS IN STEP." Parallel Processing Letters 01, no. 01 (1991): 11–18. http://dx.doi.org/10.1142/s0129626491000161.

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A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2 log N bits each and guarantees convergence to identical values within N2 "triggers".

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Korvorst, Marjolein, Ardi Roelofs, and Willem J. M. Levelt. "Telling Time from Analog and Digital Clocks." Experimental Psychology 54, no. 3 (2007): 187–91. http://dx.doi.org/10.1027/1618-3169.54.3.187.

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Abstract. Does the naming of clocks always require conceptual preparation? To examine this question, speakers were presented with analog and digital clocks that had to be named in Dutch using either a relative (e.g., “quarter to four”) or an absolute (e.g., “three forty-five”) clock time expression format. Naming latencies showed evidence of conceptual preparation when speakers produced relative time expressions to analog and digital clocks, but not when they used absolute time expressions. These findings indicate that conceptual mediation is not always mandatory for telling time, but instead

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Qiao, Shi Quan, Xiu Qing Zhang, Meng Yang, and Shu Wang Chen. "Design of Digital Clock Based on SCM." Applied Mechanics and Materials 668-669 (October 2014): 822–25. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.822.

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The digital clock is the timing device by using of the digital circuit to implement the digital display for hours, minutes and seconds. Due to the development of the digital integrated circuit and the wide application of the quartz crystal oscillator, the accuracy of the digital clock is far more than the old clocks’. The control part of the design is SCM AT89C51, and the compiler environment is Keil. The software is developed with C language, and the simulation debugging is used Proteus. The digital clock is convenient to people’s production and life, and it expands the original time function

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Li, Wangtingli, Shuhui Li, Qingyan Zeng, and Chengxi Zhou. "A Review of Design of Digital Clock Based on Verilog HDL." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 289–97. http://dx.doi.org/10.54097/hset.v46i.7716.

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With the development of electronic technology, digital clocks have added many functions that facilitate people's lives, Digital electronic clock is a device that uses digital circuits to realize the digital display of time, minutes, and seconds. This paper mainly discusses how to use Verilog HDL to design a simple digital clock and realize the basic functions such as timing and display in the clock, as well as the platform and tools used. The circuit of the digital clock is divided into three modules, namely the frequency division module, counting module, and decoding display module. And the t

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Wang, Yilin. "Verilog-based digital clock design methodology." Theoretical and Natural Science 14, no. 1 (2023): 102–7. http://dx.doi.org/10.54254/2753-8818/14/20240902.

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A digital electronic clock is a sophisticated instrument that employs digital circuits to render the timehours, minutes, and secondsin a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clocks essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate t

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Dattel, Andrew R., Andrew Henry, Godfrey D’Souza, et al. "Analog and Digital Clock Refresher Training for Improvement in Identifying Aviation Traffic." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 63, no. 1 (2019): 131–35. http://dx.doi.org/10.1177/1071181319631163.

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Air traffic controllers frequently point out other airplanes using a clock analogy (e.g., “Traffic 10 o’clock,”). This study explored the extent to which young pilots, who grew up in the digital age, understand an analog clock metaphor. Fourteen pilots were randomly assigned to either an analog clock or a digital clock refresher training group. Participants flew a 15-minute flight scenario pretest. During the pretest, participants heard prerecorded announcements of potential traffic factors. After the pretest, the analog group viewed 100 slides of analog clocks and the digital group viewed 100

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Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, et al. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 bo

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Yu, Xinguo, Wu Song, Xiaopan Lyu, Bin He, and Nan Ye. "Reading Both Single and Multiple Digital Video Clocks Using Context-Aware Pixel Periodicity and Deep Learning." International Journal of Digital Crime and Forensics 12, no. 2 (2020): 21–39. http://dx.doi.org/10.4018/ijdcf.2020040102.

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This article presents an algorithm for reading both single and multiple digital video clocks by using a context-aware pixel periodicity method and a deep learning technique. Reading digital video clocks in real time is a very challenging problem. The first challenge is the clock digit localization. The existing pixel periodicity is not applicable to localizing multiple second-digit places. This article proposes a context-aware pixel periodicity method to identify the second-pixels of each clock. The second challenge is clock-digit recognition. For this task, the algorithms based a domain knowl

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Anandaraj, Praveen Raaj, Nasrul Humaimi Mahmood, Mohd Azhar Abdul Razak, and Nor Aini Zakaria. "Digital Chess Clock for Visually Impaired Players." Journal of Human Centered Technology 3, no. 1 (2024): 46–52. http://dx.doi.org/10.11113/humentech.v3n1.68.

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Visually impaired chess players usually have difficulties using a normal traditional or digital chess clock during chess tournaments. This research aims to provide a solution which is a digital chess clock with an audio output indicating the remaining time of the chess players. These chess clocks are designed with Arduino Uno as the processing board with LCD keypad shield as display displaying and controlling and setting the hours, minutes, and seconds of the time. Besides that, the chess clock is equipped with a few mini pushbuttons to switch the time between the players together with two pus

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Jiang, Li, Xu Yan, Wei Xu, and Hancheng Zhao. "Design of Light, Small, and High-precision Digital Servo Clock for LEO Constellation." Journal of Physics: Conference Series 2638, no. 1 (2023): 012004. http://dx.doi.org/10.1088/1742-6596/2638/1/012004.

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Abstract Modern low earth orbit (LEO) satellite systems have placed increasingly stringent requirements on spaceborne time-frequency systems in the fields of constellation autonomous management, distributed synthetic aperture radar (SAR) imaging, and navigation time service. Admittedly, the original high-stability constant-temperature crystal oscillator and high-stability temperature-compensated crystal oscillator can no longer comply with the indicator requirements of clock source frequency characteristics and clock synchronization accuracy. Likewise, traditional satellites use atomic clocks

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Patil, Archana. "Design and Simulation of Clock Divider using VHDL." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem33837.

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This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

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Saradhy, Rohith, Erich Frahm, Eduardo B. S. Mendes, and Roger Rusack. "A sub-picosecond digital clock monitoring system." Journal of Instrumentation 18, no. 01 (2023): T01003. http://dx.doi.org/10.1088/1748-0221/18/01/t01003.

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Abstract We describe a low-cost system designed to monitor wander in digital clocks with a precision of ≤ 1 ps. With this system we have shown that it is possible to track phase variations at the sub-picosecond level by adding noise to a reference clock. As in many cases where a clock is part of a complex distribution network small changes in temperature and other effects can lead to small changes in the clock's phase. As a further demonstration of the system, we have used it to measure the phase changes induced in optical signals in fibers.

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Meng, Chaoyong, Chuanpei Xu, and Jiafeng Liao. "Research on Clock Synchronization of Data Acquisition Based on NoC." Applied Sciences 14, no. 11 (2024): 4838. http://dx.doi.org/10.3390/app14114838.

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Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affec

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Al-Asy’ari, Adhira Firza Fauzi Syam, Berocca Ahmada Kamelia, Dewi Atikah Mumtaz, Rafli Syahrul Yulian, and Siti Tatmainul Qulub. "Akurasi Jam Bencet Pada Waktu Salat Zuhur di Masjid Jami’ Azharul A’wan Desa Pagelaran Malang Jawa Timur." Azimuth: Journal of Islamic Astronomy 4, no. 1 (2023): 64–77. https://doi.org/10.15642/azimuth.v4i1.2210.

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Abstrak: Di era modern yang serba praktis ini, jam bencet / jam istiwa’ hampir jarang kita temui keberadaannya. Karena keberadaannya sudah tergantikan oleh jam digital. Seperti pada Masjid Azharul A’wan Desa Pagelaran, Kab. Malang, Jawa Timur ini, jam bencet ini dahulunya masih sering digunakan. Menurut wawancara takmir masjid dahulu jam bencet biasanya digunakan untuk menentukan awal waktu salat jum'at saja, untuk waktu salat selain zuhur menggunakan perhitungan hisab kontemporer. Penggunaan jam bencet yang harus membutuhkann cahaya sinar matahari membuat jam bencet hanya dapat digunakan pada

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Sarifudin, Sarifudin, Manshur Manshur, and Angga Tirtana. "Penggunaan Komunikasi Bluetooth Pada Smartphone Android Untuk Pengiriman Data Pada Jam Digital Berbasis Arduino." Jurnal ELTIKOM 1, no. 2 (2018): 102–12. http://dx.doi.org/10.31961/eltikom.v1i2.22.

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The schedule of prayer is very important akan ada.Masa Today many in the mosque as well as in homes that usually have a calendar and the viewer time of eternal prayer, but it looks so small that it can not be seen from a great distance. This prayer timepiece uses a display display dot matrix P4, displaying the date, digital clock as well as the 5th time of the prayer. So that prayer times can be changed in real time according to time and day changes, and can be seen from a great distance and can be used to maximize the time available. This research produces a digital clock time system that use

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Al-Hamoud, Yosif Marwan, and Ivaylo Ivanov. "Development and Programing of LCD Digital Clock with “RTC - Real Time Clock Module”." Science, Engineering and Education 9, no. 1 (2024): 49–58. http://dx.doi.org/10.59957/see.v9.i1.2024.7.

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In the digital era, precise timekeeping is critical across a large variety of applications, from personal devices and hobby electronics to industrial systems. This article presents the development and programming of a digital clock using a Real-Time Clock (RTC) module, a core component that ensures accurate time maintenance even if the device in which it is used is not connected to the power source.My research focuses on the integration of the RTC module using a microcontroller, emphasizing on the reliability of timekeeping provided by this hardware. My article can serve as a guide for hobbyis

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Zhang, Jingyan, and Xiaoyu Zheng. "Exploring the implementation and applications of 7-segment clocks on FPGA." Theoretical and Natural Science 26, no. 1 (2023): 37–43. http://dx.doi.org/10.54254/2753-8818/26/20241009.

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The core objective of this undertaking revolves around digital circuits and Field-programmable gate arrays (FPGAs), focusing on the design and implementation of a digital clock capable of showcasing real-time hours, minutes, and seconds. To ensure accurate time tracking, the project ingeniously employs a MOD 60 counter, dedicated specifically for counting both minutes and seconds, while a separate MOD 24 counter is harnessed to track hours. These counters serve as the backbone of the clocks accurate time-keeping capability. To translate this raw digital data into an easily interpretable format

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Yang, Jun, Hong Ye Li, and Long Liu. "Design and Implementation of the Infrared Remote-Controlled Digital Clock Based on FPGA." Applied Mechanics and Materials 738-739 (March 2015): 1266–69. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.1266.

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The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, a

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Huang, Wan Fu. "Incorporating a 4x4 Keypad in a Simple Digital Clock." Applied Mechanics and Materials 433-435 (October 2013): 1438–47. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1438.

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Most simple digital clocks use a push button to increment time reading for time adjustment. It is often time consuming. This paper suggests adding a four-by-four keypad to adjust each single time digit. The required valid 4x4 keypad key set for each time digit is predefined in the circuit design. Pressing a prohibited key would neither generate any function nor affect the operation of the digital clock. The system prototype circuit design was based on Verilog hardware description language and implemented on an EVS6 Boardan FPGA lab board. With the proposed design, adjusting time on a digital c

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Dion, Catherine, Brandon E. Frank, Samuel J. Crowley, et al. "Parkinson’s Disease Cognitive Phenotypes Show Unique Clock Drawing Features when Measured with Digital Technology." Journal of Parkinson's Disease 11, no. 2 (2021): 779–91. http://dx.doi.org/10.3233/jpd-202399.

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Background: A companion paper (Crowley et al., 2020) reports on the neuroimaging and neuropsychological profiles of statistically determined idiopathic non-dementia Parkinson’s disease (PD). Objective: The current investigation sought to further examine subtle behavioral clock drawing differences within the same PD cohort by comparing 1) PD to non-PD peers on digitally acquired clock drawing latency and graphomotor metrics, and 2) PD memory, executive, and cognitively well phenotypes on the same variables. Methods: 230 matched participants (115 PD, 115 non-PD) completed neuropsychological test

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Zhou, Yixuan. "The Application Analysis of Sequential Circuit in the Design of Multifunctional Clock." Applied and Computational Engineering 130, no. 1 (2025): 216–25. https://doi.org/10.54254/2755-2721/2025.20486.

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As time management is getting harder in this fast pace of life, traditional clocks have encountered many problems for its complexity and simple functions because it can also be a problem to integrate multiple capabilities into one device based on mechanical inner structure. Therefore, digital clocks can be a better choice and this experiment intended to provide a way of designing the circuit of a multifunctional digital clock based on components used in sequential circuits. Within the circuit, counter, reversible counter and comparator were applied to realize counting, time-setting, countdown,

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Qi, Yanfeng, and Liangfu Peng. "Design and Implementation of Precision Phase Measurement Module Base on Digital Dual Mixer Time Difference." Academic Journal of Science and Technology 5, no. 3 (2023): 152–57. http://dx.doi.org/10.54097/ajst.v5i3.7903.

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Precise phase difference measurement is critical for distributed time synchronization systems. Aiming at the problem of how to realize the sub-nanosecond phase difference measurement of the time signal, the digital dual mixer time difference (DDMTD) measurement technology is used to measure the fine transmission delay and the two digital clock phase difference. Given the problem that it is difficult to generate a common clock source with fine frequency changes inside the FPGA chip, the Si5338 chip is used to generate 4 differential clocks, and the communication with the FPGA is completed throu

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Cheng, Leqian. "Digital and analysis of alarm clock design based on Multisim." Applied and Computational Engineering 9, no. 1 (2023): 288–94. http://dx.doi.org/10.54254/2755-2721/9/20230113.

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With the development of technology and the times, virtual simulation technology represented by Multisim has been widely used, and simulation technology is also an indispensable part of industrial design. This article uses Multisim simulation technology to design and complete a digital electronic clock based on a 74ls160 counter, composed of a decoder, a display, a numerical comparator, and an alarm clock. In this design, digital circuits are used to display and adjust "time", "minute", and "second". By using various integrated digital chips to build circuits to achieve corresponding functions.

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Feng, Ziwei. "Analysis and design research of digital electronic clocks." Theoretical and Natural Science 25, no. 1 (2023): 66–72. http://dx.doi.org/10.54254/2753-8818/25/20240905.

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A digital electronic clock stands as a pinnacle of modern timing technology, built on digital circuits that offer precise hour, minute, and second tracking and display capabilities. The evolution of integrated circuits, combined with the ubiquitous application of quartz crystal oscillators, has propelled the digital electronic clock into myriad sectors including science, transportation, and finance. These clocks, appreciated for their precision, clarity, stability, and other attributes, vastly differ from their mechanical predecessors. Absent of mechanical transmission devices, they promise lo

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Lyu, Fangxing, Zekang Xiong, Fei Li, and Xin Fang. "A Photonic Time-Interleaved ADC Architecture Based on Optical Clock Distribution and Elector-Optical Modulation Technology." Journal of Nanoelectronics and Optoelectronics 18, no. 4 (2023): 435–40. http://dx.doi.org/10.1166/jno.2023.3409.

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A photonic time-interleaved analog-to-digital conversion (PTIADC) scheme by exploring optical clock distribution technology and elector-optical modulation technology is presented in this work. In the proposed PTIADC system, the interleaved sampling clocks for several channel analog-to-digital converters (ADCs) are implemented by optical clocks. A proof-of-concept experiment with a four-channel 400 MS/s PTIADC system has been achieved, and the performance has been experimentally demonstrated. Experimental results show that the proposed method can offer four-channel clock signals with low-timing

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Li, Tie Hu, Rui Tao Zhang, Wei Dong Yang, and Guang Bing Chen. "An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter." Applied Mechanics and Materials 716-717 (December 2014): 1293–97. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1293.

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An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) ca

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Andersen, Stacy, Mengtian Du, Nicole Roth, et al. "Early Differences in Cognition Associated With Familial Longevity and ApoE Genotype Using Digital Technology." Innovation in Aging 4, Supplement_1 (2020): 656–57. http://dx.doi.org/10.1093/geroni/igaa057.2264.

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Abstract Merging digital technologies with neuropsychological testing allows for collection of novel metrics that may reveal early, subtle differences in cognitive functioning. We examined whether digital pen metrics from the Clock Drawing Test (CDT) differentiate healthy agers (i.e., individuals with familial longevity) from spouses and individuals by APOE genotype. We used generalized estimating equations adjusted for sociodemographics, familial longevity, and APOE genotype. Among 1974 participants with correct clocks (mean age 71±10 years), familial longevity was associated with better cogn

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Jung, Gunok, Gi-Ho Park, Ukrae Cho, and Jae Cheol Son. "Fully digital clock frequency doubler." IEICE Electronics Express 7, no. 6 (2010): 416–20. http://dx.doi.org/10.1587/elex.7.416.

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Balasubramanian, K. "Multi-time zoned digital clock." IEEE Transactions on Consumer Electronics 37, no. 4 (1991): 867–72. http://dx.doi.org/10.1109/30.106951.

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Fenghao Mu, A. Edman, and C. Svensson. "Digital multiphase clock/pattern generator." IEEE Journal of Solid-State Circuits 34, no. 2 (1999): 182–91. http://dx.doi.org/10.1109/4.743769.

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Jovanovic, Goran, and Mile Stojcev. "Pulse width control loop as a duty cycle corrector." Serbian Journal of Electrical Engineering 1, no. 2 (2004): 215–26. http://dx.doi.org/10.2298/sjee0402215j.

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The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system?s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as

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Viraktamath, Dr S. V. "Arduino Digital Clock without RTC Module." International Journal for Research in Applied Science and Engineering Technology 9, no. 8 (2021): 967–71. http://dx.doi.org/10.22214/ijraset.2021.37546.

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Abstract: This paper analyzes a clock using Arduino without Real time clock (RTC). The development of the digital clock in Arduino is to provide its own time without RTC. Generally, electronic circuit designers use RTC to construct a clock. Such a circuit requires an extra circuit and power. The CMOS battery supplies power to the RTC, once the CMOS battery power is discharged. It automatically erases the date and time and requires an update from an external device. Considering these facts, RTC is avoided and code with nested looping is used to maintain timing in Arduino. It enables us to modif

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Kim, Seungjun, Junghoon Jin, and Jongsun Kim. "A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications." Electronics 11, no. 21 (2022): 3630. http://dx.doi.org/10.3390/electronics11213630.

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A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated

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He, Juan, and Song Yue Yuan. "Liquid Crystal Display Digital Clock Based on SCM." Advanced Materials Research 711 (June 2013): 598–601. http://dx.doi.org/10.4028/www.scientific.net/amr.711.598.

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The single chip microcomputer with digital clock has been designed based on AT89C52, through the design ideas of multi-function digital clock, we have described the system hardware, software and the realization process.The display design and implementation of a year, month, day, time and second is achieved using C language. And the simulation is used by Proteus software. By comparing the actual clock, we have found out the source of the error and have determined the method of adjusting error, and we reduce the error as much as possible, so we can achieve the allowable error range for a practic

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Cheng, Zilu. "Design and implementation of a digital clock using a seven-segment display." Theoretical and Natural Science 14, no. 1 (2023): 224–32. http://dx.doi.org/10.54254/2753-8818/14/20241013.

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A digital electronic clock is a sophisticated timing instrument that employs digital technology to showcase the hours, minutes, and seconds. Distinct from traditional timekeeping devices, these clocks offer unparalleled precision, eliminating the need for mechanical transmission components. Their displays are not only clear and easy to read but also streamlined, which enhances their appeal. In the ever-evolving urban landscape, where aesthetics and functionality are paramount, digital electronic clocks have carved out a significant niche. These modern marvels can now be found gracing numerous

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Davoudi, Anis, Catherine Dion, Erin Formanski, et al. "Normative References for Graphomotor and Latency Digital Clock Drawing Metrics for Adults Age 55 and Older: Operationalizing the Production of a Normal Appearing Clock." Journal of Alzheimer's Disease 82, no. 1 (2021): 59–70. http://dx.doi.org/10.3233/jad-201249.

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Background: Relative to the abundance of publications on dementia and clock drawing, there is limited literature operationalizing ‘normal’ clock production. Objective: To operationalize subtle behavioral patterns seen in normal digital clock drawing to command and copy conditions. Methods: From two research cohorts of cognitively-well participants age 55 plus who completed digital clock drawing to command and copy conditions (n = 430), we examined variables operationalizing clock face construction, digit placement, clock hand construction, and a variety of time-based, latency measures. Data ar

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Yih-Chyun Jenq. "Direct digital synthesizer with jittered clock." IEEE Transactions on Instrumentation and Measurement 46, no. 3 (1997): 653–55. http://dx.doi.org/10.1109/19.585421.

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Friedman, William J., and Frank Laycock. "Children's Analog and Digital Clock Knowledge." Child Development 60, no. 2 (1989): 357. http://dx.doi.org/10.2307/1130982.

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Lee, I.-Ting, Shih-Han Ku, and Shen-Iuan Liu. "An All-Digital Despreading Clock Generator." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 1 (2014): 16–20. http://dx.doi.org/10.1109/tcsii.2013.2290913.

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Hamalainen, Jukka. "Clock Rate Conversion for Digital Video." SMPTE Journal 101, no. 6 (1992): 394–98. http://dx.doi.org/10.5594/j02260.

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Jovanovic, Goran, and Mile Stojcev. "Voltage controlled delay line for digital signal." Facta universitatis - series: Electronics and Energetics 16, no. 2 (2003): 215–32. http://dx.doi.org/10.2298/fuee0302215j.

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This paper describes dual delay locked loop architecture with a mixed mode phase tuning method. The circuit accomplishes low jitter, unlimited phase shift in a large operating range, and accurate phase alignment with high resolution for relatively low input clock frequency. The architecture employs two DLL loops. The first one is digital and is used for generating coarsely spaced clock pulses, while the second is analog and is intended for accurate and precise fine phase shifting. Simulations show that this circuit has 2?r radians phase shift capability, and can resolve 25ps phase error at inp

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Olsson, T., and P. Nilsson. "Portable digital clock generator for digital signal processing applications." Electronics Letters 39, no. 19 (2003): 1372. http://dx.doi.org/10.1049/el:20030910.

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Dr., Mohan Kumar. "Digital Locker - A Step towards Digital India: Uses and Challenges." Journal of Management Engineering and Information Technology (JMEIT) 3, no. 6 (2017): 3. https://doi.org/10.5281/zenodo.250627.

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Abstract The official website of Govt. of India i.e. www.digitallocker.gov.in defines digital locker as “Digi locker is a secure cloud based platform for storage, sharing and verification of documents and certificates”. The digilocker is a facility provided to the citizens of India to help them to digitally store their documents. Now one need not to take his/ her documents , mark sheets, pan card, etc. in his briefcase or folder and be vigilant round the clock for their security due to misplace or theft. You may just click to your Digital Locker if you want to use these documents anywhere in t

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Zhu, Juan Hua, Ang Wu, and Juan Fang Zhu. "Research and Design of Digital Clock Based on FPGA." Advanced Materials Research 187 (February 2011): 741–45. http://dx.doi.org/10.4028/www.scientific.net/amr.187.741.

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A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified exp

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HamaRaouf, Karwan M., and Ayub Othman Abdulrahman. "Microcontroller-Based Kurdish Understandable and Readable Digital Smart Clock." Science Journal of University of Zakho 10, no. 1 (2022): 1–4. http://dx.doi.org/10.25271/sjuoz.2022.10.1.870.

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A smart clock is any digital clock that has at least one intelligent feature. Moreover, it provides time with synchronizing automatically base on the standard measurement, which is determined during the implementation software on the hardware architecture design. This study presents an efficient cost-effective smartwatch for disable people based on the Atmega328p microcontroller (Arduino Uno) that is programmed in “Arduino” (C based) programming language. Moreover, the system uses DS1302 real time clock, SD card memory, push button, voice recognition module, liquid crystal display (LCD), and s

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LUO, ZHIHONG, YEUNG ON AU, BENJAMIN LAU, and HENRY LAW. "A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS." Journal of Circuits, Systems and Computers 21, no. 08 (2012): 1240026. http://dx.doi.org/10.1142/s0218126612400269.

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A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND

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Chen, Hsin Chuan. "Design of DDS-Like Clock Generator Using Bidirectional Integration." Applied Mechanics and Materials 284-287 (January 2013): 2627–31. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2627.

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In many applications such as digital communication systems, a reconfigurable clock is required to switch the desired frequency at necessary time. However, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems, therefore phase-interpolation approaches are used to generate a pulse or clock with correct time intervals. Focusing on design methodology, a high-precision DDS-like clock generator without phase accumulator and phase interpolation is proposed in this paper, which only uses the bidirectional integration on a single capac

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Lu, Shi Bin, Tai Long Xu, Chang Yong Zheng, Hao Pan, and Jun Ning Chen. "An Improved Phase Comparator for the Fast-Locking All Digital SARDLL." Applied Mechanics and Materials 303-306 (February 2013): 1849–53. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1849.

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An improved phase comparator solution for the fast-locking all digital SARDLL, which can deal with the irregular clock signal and give the signal Comp reflecting the phase relations between input clock and output clock, and the signal LD indicating whether the DLL is locked or not, is presented. The improved solution is justified by the transistor- level post-layout SPICE simulation results.

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Heo, Yoon, and Won-Young Lee. "An All-Digital Dual-Mode Clock and Data Recovery Circuit for Human Body Communication Systems." Electronics 13, no. 23 (2024): 4832. https://doi.org/10.3390/electronics13234832.

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This paper describes an all-digital clock and data recovery (CDR) circuit for implementing edge processing with a wireless body area network (WBAN). The CDR circuit performs delay-locked loop (DLL)-based and phase-locked loop (PLL)-based operations depending on the use of an external reference clock and is implemented using a digital method that is robust against external noise. The clock generator circuit shared by the two operation methods is described in detail, and the CDR circuit recovers 42 Mb/s input data and a 42 MHz clock, which are the specifications of human body communication (HBC)

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