Academic literature on the topic 'Digital CMOS integrated circuits'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Digital CMOS integrated circuits.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Digital CMOS integrated circuits"

1

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

Full text
Abstract:
In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
APA, Harvard, Vancouver, ISO, and other styles
2

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

Full text
Abstract:
Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.
APA, Harvard, Vancouver, ISO, and other styles
3

de Sousa, J. J. H. T., F. M. Goncalves, and J. P. Teixeira. "Physical design of testable CMOS digital integrated circuits." IEEE Journal of Solid-State Circuits 26, no. 7 (1991): 1064–72. http://dx.doi.org/10.1109/4.92027.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

Full text
Abstract:
Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
APA, Harvard, Vancouver, ISO, and other styles
5

Mark, Andrew G., Emmanuel Suraniti, Jérôme Roche, et al. "On-chip enzymatic microbiofuel cell-powered integrated circuits." Lab on a Chip 17, no. 10 (2017): 1761–68. http://dx.doi.org/10.1039/c7lc00178a.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

Full text
Abstract:
Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.
APA, Harvard, Vancouver, ISO, and other styles
7

Daoming, Ke, Feng Yaolan, Tong Qinyi, and Ke Xiaoli. "Transient characteristic analysis of high temperature CMOS digital integrated circuits." Journal of Electronics (China) 11, no. 2 (1994): 104–15. http://dx.doi.org/10.1007/bf02778359.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Song, Hang, Afreen Azhari, Xia Xiao, Eiji Suematsu, Hiromasa Watanabe, and Takamaro Kikkawa. "Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom." International Journal of Antennas and Propagation 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/6757048.

Full text
Abstract:
A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS) integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T) switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.
APA, Harvard, Vancouver, ISO, and other styles
9

Liu, Lun Cai, Xiao Zong Huang та Wen Gang Huang. "An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process". Applied Mechanics and Materials 251 (грудень 2012): 206–9. http://dx.doi.org/10.4028/www.scientific.net/amm.251.206.

Full text
Abstract:
A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in a low-cost standard CMOS process with 0.6μm featured size, taking area of 600μm×150μm excluding the bonding pads.
APA, Harvard, Vancouver, ISO, and other styles
10

FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

Full text
Abstract:
Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Digital CMOS integrated circuits"

1

Jiang, Wenjie 1963. "Hot-carrier reliability assessment in CMOS digital integrated circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47514.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Miranda, Fernando Pedro Henriques de. "Estudo e projeto de circuitos dual-modulus prescalers em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-154818/.

Full text
Abstract:
Este trabalho consiste no estudo e projeto de circuitos Dual-Modulus Prescaler utilizados em sistemas de comunicação RF (radio frequency). Sistemas de comunicação RF trabalham em bandas de freqüência pré-definidas e dentro destas há, normalmente, vários canais para transmissão. Neste caso, decidido o canal onde se vai trabalhar, o receptor e o transmissor geram, através de um circuito chamado Sintetizador de Freqüências, sinais que têm a freqüência igual a freqüência central do canal utilizado. Esses sinais ou tons são empregados na modulação e demodulação das informações transmitidas ou recebidas. O Sintetizador de Freqüências possui como componentes um oscilador controlável, contadores programáveis, comparadores de fase e um divisor de freqüências chamado Dual-Modulus Prescaler. O funcionamento do Sintetizador é descrito a seguir: o Prescaler recebe um sinal proveniente da saída do oscilador controlável e gera um sinal que tem a freqüência igual a aquela do sinal de entrada dividida por N ou N+1, dependendo do valor lógico de um sinal de controle. O sinal gerado por esse circuito divisor será ainda dividido por contadores e comparado a um sinal de referência externo no comparador de fase. O comparador, por sua vez, gera o sinal de controle do oscilador controlável, aumentando ou reduzindo sua velocidade. Pelo ajuste do número de vezes que o circuito Prescaler divide por N ou N+1, se controla a freqüência da saída do Sintetizador. De todos os circuitos que compõe o Sintetizador de Freqüência, apenas o oscilador controlável e o Prescaler trabalham em altas freqüências (freqüência máxima do sistema) e por conseqüência, a velocidade máxima de trabalho e o consumo de potência do Sintetizador dependerão da performance destes. Neste trabalho se utilizou a técnica Extended True Single Clock Phase para se projetar o Prescaler. O projeto do circuito Prescaler foi realizado na tecnologia CMOS (Complementary Metal Oxide Silicon) 0,35 ?m da AMS [Au03a], que satisfaz as necessidades visadas (banda de trabalho centrada em 2,4 GHz) e tem um custo para prototipagem satisfatório. Vários circuitos foram implementados nesta tecnologia e testados, se obtendo um Prescaler que atinge velocidade de 3,6 GHz, consumo de 1,6 mW para tensão de alimentação de 3,3 V.<br>This work consists of the study and project of circuits Dual-Modulus Prescaler used in communication systems RF (radio frequency). RF Communication Systems work in predefined frequency bands and inside of them, there are several transmission channels. In this case, once decided the channel where we will work, the receiver and the transmitter generate, through a circuit called Frequency Synthesizer, signs that have the same frequency of the central frequency of the used channel. Those signs or tones are used in the modulation and demodulation of the transmitted or received information. The Frequency Synthesizer possesses as components a controllable oscillator, programmable counters, phase comparator and a frequency divider called Dual-Modulus Prescaler. The Synthesizer operation is described: the Prescaler receives a sign from the oscillator and generates an output signal with frequency equal to the frequency of the input signal divided by N or N+1, depending on the logical value of a control sign. The output of the Prescaler will be divided by other counters and compared with an external reference sign in the phase comparator. That comparator, for its turn, generates a control signal for the oscillator, increasing or reducing its speed. By the adjustment of the number of times that the circuit Prescaler divides for N or N+1, the frequency of Synthesizer output is controlled. From all the blocks that compose the Frequency Synthesizer, only the controllable oscillator and the Prescaler work in high frequencies (the maximum frequency of the system), and, in consequence, the maximum speed and the power consumption of the full Synthesizer will depend on the performance of these two blocks. In this work we applied the technique called Extended True Single Clock Phase to design the Prescaler. The project of the circuit Prescaler used the technology CMOS (Complementary Metal Oxide Silicon) 0.35 ?m of AMS [Au03a]. This technology was used because it satisfies the sought needs (work band centered in 2.4 GHz) and has a satisfactory cost. Several circuits were implemented in this technology and tested and it was obtained a Prescaler which reaches 3.6 GHz, 1.6 mW power consumption with power supply of 3.3 V.
APA, Harvard, Vancouver, ISO, and other styles
3

Maiuri, Ovidio V. "Testing of digital CMOS integrated circuits : the multidimensional testing paradigm." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299132.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Iyer, Gopal Balakrishnan. "Digital communication and control circuits for 60ghz fully integrated CMOS digital radio." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39589.

Full text
Abstract:
Emerging "bandwidth hungry" applications such as high definition video distribution and ultra fast multimedia side-loading have extended the need for multi-gigabit wireless solutions beyond the reach of conventional WLAN technology or even more recently emerging UWB and MIMO systems. The availability of 7GHz of unlicensed bandwidth in the 60GHz spectrum, represents a unique opportunity to address such data-throughput requirements. The 60GHz Integrated CMOS digital radio chipset comprises of PHY and MAC layers, RF transceiver, High-Speed Digital Interface and an underlying Serial Communication Fabric. To have a complete communication solution compliant with the latest ECMA-369, ISO/DIS 13156 and IEEE 802.15.3c standards, we build a million gate digital implementation of MAC and PHY. The Serial Peripheral Interface (SPI) serves as the bridge between the higher layers in the communication stack (PAL-MAC) and the lower layers like PHY-RF Front End. The MAC module can setup the communication link on the fly by tuning parameters such as operating channel, channel bonding and bandwidth, data rates, error correction mechanisms, handshaking mechanisms, etc, by using the SPI to communicate with internal components. The SPI interface plays a crucial rule in not only this, but also during the testing and debug phase. Operation of each of the RF modules is monitored through the serial interface using local SPI slaves which are hooked up to the 4-wire serial bus running all through the chip. The SPI host controller emulates an embedded protocol analyzer. For calibration and fine tuning purposes, digital settings can also be loaded onto these modules through the SPI interface. R-2R DACs are used to convert these commands into analog voltages which then provide a tunable bias to the RF and mixed-signal modules. Other key functions of this serial communication and control interface are: Initialization of all of the RF and mixed signal modules, DC calibration of data converter, PLL and other mixed-signal modules, data acquisition, parametric tuning for digital modules such as linear equalizer, Gain Control loops (AGC, VGA), etc. Ultra high speed digital Input-Output buffers are used to provide an external data interface to the radio chipset. These high speed I/Os are also used in the gbps (gigabit-per-second) link for data transfer between the RF transceiver chip and the PHY-MAC baseband chip. The IOs are expected to comply with different signaling standards such as LVDS, SLVS200, SLVS400, etc. A robust system involves a meticulous pad ring design with proper power domains and power cuts. Full-chip integration of the digital PHY, MAC, peripheral logic and IO ring is done in a semi-custom fashion.
APA, Harvard, Vancouver, ISO, and other styles
5

Kasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /." View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Johnstone, Kevin Kennedy. "On the nature and effect of power distribution noise in CMOS digital integrated circuits." Thesis, Middlesex University, 1991. http://eprints.mdx.ac.uk/13368/.

Full text
Abstract:
The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing.
APA, Harvard, Vancouver, ISO, and other styles
8

Lee, Myunghee. "A quasi-monolithic optical receiver using a standard digital CMOS technology." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14720.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

Full text
Abstract:
Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas.<br>This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Digital CMOS integrated circuits"

1

Yusuf, Leblebici, ed. CMOS digital integrated circuits: Analysis and design. 2nd ed. McGraw-Hill, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kang, Sung-Mo. CMOS digital integrated circuits: Analysis and design. 2nd ed. McGraw-Hill, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Yusuf, Leblebici, ed. CMOS digital integrated circuits: Analysis and design. 3rd ed. McGraw-Hill, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kang, Sung-Mo. CMOS digital integrated circuits: Analysis and design. McGraw-Hill, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Digital CMOS circuit design. Kluwer Academic Publishers, 1986.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Kuo, James B. CMOS digital IC. McGraw-Hill, Inc., 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton University Press, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton University Press, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Shoji, Masakazu. CMOS digital circuit technology. Prentice-Hall International, 1988.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

CMOS digital circuit technology. Prentice Hall, 1987.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Digital CMOS integrated circuits"

1

Larsson, Patrik. "di/dt Noise in CMOS Integrated Circuits." In Analog Design Issues in Digital VLSI Circuits and Systems. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6101-9_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Leblebici, Duran, and Yusuf Leblebici. "Analog-Digital Interfaces." In Fundamentals of High Frequency CMOS Analog Integrated Circuits. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-63658-6_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Unbehauen, Rolf, and Andrzej Cichocki. "CMOS Analog-to-Digital and Digital-to-Analog Conversion Systems." In MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-83677-0_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Van Rethy, Jelle, Valentijn De Smedt, Wim Dehaene, and Georges Gielen. "Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits." In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07938-7_17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Strukov, Dmitri B. "Hybrid Semiconductor-Molecular Integrated Circuits for Digital Electronics: CMOL Approach." In Nanoelectronics and Photonics. Springer New York, 2008. http://dx.doi.org/10.1007/978-0-387-76499-3_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Di Pendina, Gregory, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, and Lionel Torres. "Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Likhareu, Konstantin K. "Integrated Circuits Beyond CMOS." In Nanoelectronics and Photonics. Springer New York, 2008. http://dx.doi.org/10.1007/978-0-387-76499-3_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Chan, Mansun. "Stacked CMOS Technologies." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Ingels, Mark, and Michiel Steyaert. "Integrated CMOS Optical Receivers." In Integrated CMOS Circuits for Optical Communications. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-662-07926-3_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Stan, M. R., G. S. Rose, and M. M. Ziegler. "Hybrid CMOS/Molecular Integrated Circuits." In Into the Nano Era. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-74559-4_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Digital CMOS integrated circuits"

1

Wang, Hua, and Ali Hajimiri. "A Wideband CMOS Linear Digital Phase Rotator." In 2007 IEEE Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405821.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Lou, Liheng, Bo Chen, Kai Tang, and Yuanjin Zheng. "A CMOS digital-controlled oscillator for All-digital PLL frequency synthesizer." In 2016 International Symposium on Integrated Circuits (ISIC). IEEE, 2016. http://dx.doi.org/10.1109/isicir.2016.7829720.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Natarajan, Saravana P., Shawn J. Cunningham, Arthur S. Morris, and Dana R. Dereus. "CMOS integrated digital RF MEMS capacitors." In 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2011). IEEE, 2011. http://dx.doi.org/10.1109/sirf.2011.5719327.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Komatsu, T., K. Watanabe, E. Minamimura, et al. "CMOS high speed digital datastrobe processor." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56731.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Borremans, J., K. Vengattarmane, and J. Craninckx. "A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS." In 2010 IEEE Radio Frequency Integrated Circuits Symposium. IEEE, 2010. http://dx.doi.org/10.1109/rfic.2010.5477312.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Boers, Michael. "A 60GHz transformer coupled amplifier in 65nm digital CMOS." In 2010 IEEE Radio Frequency Integrated Circuits Symposium. IEEE, 2010. http://dx.doi.org/10.1109/rfic.2010.5477356.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Borremans, J., P. Wambacq, G. van der Plas, Y. Rolian, and M. Kuijk. "A Bondpad-Size Narrowband LNA for Digital CMOS." In 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. IEEE, 2007. http://dx.doi.org/10.1109/rfic.2007.380973.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Staszewski, Robert, Khurram Muhammad, and Dirk Leipold. "Digital Signal Processing for RF at 45-nm CMOS and Beyond." In IEEE Custom Integrated Circuits Conference 2006. IEEE, 2006. http://dx.doi.org/10.1109/cicc.2006.320904.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Kwon, Dae Hyun, Hao Li, Yuchun Chang, Richard Tseng, and Yun Chiu. "CMOS RF transmitter with integrated power amplifier utilizing digital equalization." In 2009 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2009. http://dx.doi.org/10.1109/cicc.2009.5280808.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Huang, Chi-Chun, Guo-Lin Jhuang, and Chua-Chin Wang. "A Direct Digital Frequency Synthesizer with CMOS OTP ROM§." In 2007 International Symposium on Integrated Circuits - ISIC 2007. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441804.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "Digital CMOS integrated circuits"

1

Resnick, Douglas, and Konstantin Likharev. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada487894.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Van Duzer, T., Stephen R. Whiteley, Lizhen Zheng, et al. Hybrid Josephson-CMOS Random Access Memory with Interfacing to Josephson Digital Circuits. Defense Technical Information Center, 2013. http://dx.doi.org/10.21236/ada596658.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Grein, Matthew E., Steven J. Spector, Anatol Khilo, et al. Demonstration of a 10 GHz CMOS-Compatible Integrated Photonic Analog-to-Digital Converter. Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada540334.

Full text
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!