Relevant bibliographies by topics / Digital CMOS integrated circuits / Dissertations / Theses
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Dissertations / Theses on the topic 'Digital CMOS integrated circuits'

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Published: 4 June 2021
Last updated: 6 February 2022

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1

Jiang, Wenjie 1963. "Hot-carrier reliability assessment in CMOS digital integrated circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47514.

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2

Miranda, Fernando Pedro Henriques de. "Estudo e projeto de circuitos dual-modulus prescalers em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-154818/.

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Este trabalho consiste no estudo e projeto de circuitos Dual-Modulus Prescaler utilizados em sistemas de comunicação RF (radio frequency). Sistemas de comunicação RF trabalham em bandas de freqüência pré-definidas e dentro destas há, normalmente, vários canais para transmissão. Neste caso, decidido o canal onde se vai trabalhar, o receptor e o transmissor geram, através de um circuito chamado Sintetizador de Freqüências, sinais que têm a freqüência igual a freqüência central do canal utilizado. Esses sinais ou tons são empregados na modulação e demodulação das informações transmitidas ou receb
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3

Maiuri, Ovidio V. "Testing of digital CMOS integrated circuits : the multidimensional testing paradigm." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299132.

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4

Iyer, Gopal Balakrishnan. "Digital communication and control circuits for 60ghz fully integrated CMOS digital radio." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39589.

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Emerging "bandwidth hungry" applications such as high definition video distribution and ultra fast multimedia side-loading have extended the need for multi-gigabit wireless solutions beyond the reach of conventional WLAN technology or even more recently emerging UWB and MIMO systems. The availability of 7GHz of unlicensed bandwidth in the 60GHz spectrum, represents a unique opportunity to address such data-throughput requirements. The 60GHz Integrated CMOS digital radio chipset comprises of PHY and MAC layers, RF transceiver, High-Speed Digital Interface and an underlying Serial Communication
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5

Kasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /." View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.

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6

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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7

Johnstone, Kevin Kennedy. "On the nature and effect of power distribution noise in CMOS digital integrated circuits." Thesis, Middlesex University, 1991. http://eprints.mdx.ac.uk/13368/.

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The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,0
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8

Lee, Myunghee. "A quasi-monolithic optical receiver using a standard digital CMOS technology." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14720.

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9

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

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10

Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuito
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11

Xiong, Zhijie. "Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5043.

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Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design o
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12

Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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13

Sudirgo, Stephen. "The integration of Si-based resonant interband tunnel diodes with CMOS /." Online version of thesis, 2003. http://hdl.handle.net/1850/5192.

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14

Carr, Richard D. "Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA293356.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994.<br>"December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.
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15

Manich, Bou Salvador. "Anàlisi de l'energia de transició màxima en circuits combinacionals CMOS." Doctoral thesis, Universitat Politècnica de Catalunya, 1998. http://hdl.handle.net/10803/6361.

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En la dècada actual, l'augment del consum energètic dels circuits integrats està tenint un impacte cada vegada més important en el disseny electrònic. Segons l'informe de la Semiconductor Industry Association de l'any 1997, es preveu que aquest impacte serà encara major en la propera dècada. En la bibliografia existeixen diversos treballs on es relaciona un consumo energètic elevat amb la degradació de les prestacions i la fiabilitat del xip. Per aquesta raó, el consum energètic ha estat incorporat com a un altre paràmetre a tenir en compte en el disseny dels circuits integrats. Es coneix com
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16

Oliveira, Vlademir de Jesus Silva [UNESP]. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.

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Made available in DSpace on 2014-06-11T19:30:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-11-25Bitstream added on 2014-06-13T21:01:20Z : No. of bitstreams: 1 oliveira_vjs_dr_ilha.pdf: 2584742 bytes, checksum: ae7b3113a196a5051a808dbb371dece4 (MD5)<br>Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)<br>Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzi
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17

Kešner, Filip. "Design of Digital Circuits at Transistor Level." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236048.

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This work aims to design process of integrated circuits on the transistor level, specially using evolutionary algorithm. For this purpose it is necessary to choose reasonable level of abstraction during simulation, which is used for evaluation candidate solutions by fitness function. This simulation has to be fast enough to evaluate thousands of candidate solutions within seconds. This work discusses already used techniques for transistor level circuit design and it chooses useful parts for new design of faster and more reliable automated design process, which would be able to design complex l
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18

Aparicio, Rodriguez Marina. "Modelling and Simulation of the IR-Drop phenomenon in integrated circuits." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2013. http://tel.archives-ouvertes.fr/tel-00998547.

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Scaling technology in deep-submicron has reduced the voltage supply level and increased the number of transistors in the chip, increasing the power supply noise sensitivity of the ICs. Excessive power supply noise affects the timing performance increasing the gate delay and may cause timing faults. Specifically, power supply noise induced by the currents that flow through the resistive parasitic elements of the Power Distribution Network (PDN) is called IR-Drop. This thesis deals with the modelling and simulation of logic circuits in the context of IR-drop. An original algorithm is proposed al
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19

Germanovix, Walter. "Analogue techniques for micro-power cochlear implants." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313753.

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20

Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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21

Mäntyniemi, A. (Antti). "An integrated CMOS high precision time-to-digital converter based on stabilised three-stage delay line interpolation." Doctoral thesis, University of Oulu, 2004. http://urn.fi/urn:isbn:951427461X.

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Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings
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22

Oliveira, Vlademir de Jesus Silva. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS /." Ilha Solteira : [s.n.], 2009. http://hdl.handle.net/11449/100280.

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Orientador: Nobuo Oki<br>Banca: Suely Cunha Amaro Mantovani<br>Banca: Jozué Vieira Filho<br>Banca: Marcelo Arturo Jara Perez<br>Banca: Paulo Augusto Dal fabbro<br>Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência
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23

Douglas, Dale Scott. "Flicker noise in cmos lc oscillators." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.

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Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted. A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techn
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24

Pimentel, Henrique Luiz Andrade. "Projeto de um amplificador de baixo ruído em tecnologia CMOS 130nm para frequências de 50MHZ a 1GHz." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67180.

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O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássi
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25

Butzen, Paulo Francisco. "Aging aware design techniques and CMOS gate degradation estimative." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/61868.

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O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o cons
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26

Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.

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The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system. The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis, Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure. The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a mu
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27

Soukup, Luděk. "Návrh digitálně-analogového převodníku typu sigma-delta v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219761.

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This master’s thesis deals with the issue of digital to analog conversion and possibility of its realization in digital circuits. Goal of this project is to design sigma-delta digital to analog converter with resolution of 14 bits and frequency band (0 ÷ 20) kHz. Main functional blocks: interpolator and modulator sigma-delta will be realized like digital structures. Reconstruction filter will be realized like an analog structure. For design a check of parameters of designed converter programs MATLAB and Simulink are used. Designed digital structures will be described by VHDL language.
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28

Lee, Hyung-Jin. "Digital CMOS Design for Ultra Wideband Communication Systems: from Circuit-Level Low Noise Amplifier Implementation to a System-Level Architecture." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26195.

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CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range
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29

Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion." Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.

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Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement
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30

Song, Tae Joong. "A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34760.

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This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is perf
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31

Carvalho, Paulo Roberto Bueno de. "Projeto de circuito oscilador controlado numericamente implementado em CMOS com otimização de área." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26012017-085719/.

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Este trabalho consiste no projeto e implementação em CMOS de um circuito integrado digital para geração de sinais, denominado Oscilador Controlado Numericamente. O circuito será aplicado em um sistema de Espectroscopia por Bioimpedância Elétrica, utilizado como método para detecção precoce de câncer do colo do útero. Durante o trabalho, realizou-se o estudo dos requisitos do sistema de espectroscopia e as especificações dos tipos de sinais a serem gerados. Levantou-se, na bibliografia, algumas técnicas de codificação em linguagem de hardware para otimização do projeto nos quesitos área, potênc
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32

Mathieu, Brandon Lee. "Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236.

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33

Levski, Deyan. "Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7.

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This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of sing
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34

Marble, William Joel. "Design and Analysis of Charge-Transfer Amplifiers for Low-Power Analog-to-Digital Converter Applications." BYU ScholarsArchive, 2004. https://scholarsarchive.byu.edu/etd/35.

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The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic model of the voltage
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35

Barazi, Yazan. "Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology." Thesis, Toulouse, INPT, 2020. http://www.theses.fr/2020INPT0091.

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Les transistors de puissance grands gaps tels que les MOSFETs SiC et HEMT GaN repoussent les compromis classiques en électronique de puissance. Brièvement, des gains significatifs ont été démontrés par les transistors SiC et GaN: meilleurs rendements, couplés à une augmentation des densités de puissance offertes par la montée en fréquence de découpage. Les MOSFET SiC à haute tension présentent des spécificités telles qu'une faible tenue en court-circuit (SC) par rapport aux IGBT Si et un oxyde de grille aminci, et une tension de commande rapprochée grillesource élevée. La polarisation négative
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Zhao, Wei. "Development of CMOS sensor with digital pixels for ILD vertex detector." Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAE004/document.

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La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex de l’ILD (International Large Detector). Motivé par la physique dans l’ILC (International Linear Collider), une précision élevée est nécessaire pour les détecteurs. La priorité des capteurs qui montre sur les couches externes est une faible consommation d’énergie en raison du rapport élevé de couverture de la surface sensible (~90%) dans le détecteur de vertex. Le CPS intégré avec CAN est un choix approprié pour cette application. L’architecture de
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Marefat, Fatemeh. "Toward Cuffless Blood Pressure Monitoring: Integrated Microsystems for Implantable Recording of Photoplethysmogram." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1595441087168539.

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38

Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.

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A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura osci
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39

Shenoy, Sandeep P. (Sandeep Pundalika). "Switching activity in CMOS digital circuits." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24071.

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In (48, 47) a pattern-independent method to estimate the switching activity of a CMOS circuit was presented. The technique relies on the use of abstract waveforms, described down to the level of individual transitions, which are propagated through the circuit. In order to improve the switching activity estimate so obtained, case analysis is undertaken on nodes with large fanout.<br>The objective of this thesis is to develop and implement a method to further improve upon the switching activity estimate through consideration of reconvergent fanout regions in the circuit. The idea is to impose fu
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40

Söderquist, Ingemar. "CMOS circuits for digital RF systems /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek775s.pdf.

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41

Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.

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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which se
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42

Nissinen, J. (Jan). "Integrated CMOS circuits for laser radar transceivers." Doctoral thesis, Oulun yliopisto, 2011. http://urn.fi/urn:isbn:9789514295454.

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Abstract The main aim of this work was to design CMOS receiver channels for the integrated receiver chip of a pulsed time-of-flight (TOF) laser rangefinder. The chip includes both the receiver channel and the time-to-digital converter (TDC) in a single die, thus increasing the level of integration of the system, with the corresponding advantages of a cheaper price and lower power consumption, for example. Receiver channels with both linear and leading edge timing discriminator schemes were investigated. In general the receiver channel consists of a preamplifier, a postamplifier and a timing co
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43

Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.

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44

Chan, Na-Han. "Rapid current analysis for CMOS digital circuits." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=26380.

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A versatile and efficient computer-aided analysis tool, CUREST, has been developed for the analysis of supply currents in CMOS digital circuits. It is based on Nabavi-Lishi's semi-analytical model for computing the current and delay in a CMOS logic gate which, when compared to HSPICE running the level-3 MOSFET model, is more than three orders of magnitude faster, and accurate to within 10%. CUREST is built on top of the timing analyser TAMIA and, in particular, uses its circuit parser and its data structure to store the circuit topology and primary input pattern.<br>Extension tests on benchmar
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45

Smith, Anthony V. W. "Implementation of neural networks as CMOS integrated circuits." Thesis, University of Edinburgh, 1988. http://hdl.handle.net/1842/11408.

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This thesis describes research into the VLSI implementation of neural networks. A novel approach is detailed, which uses streams of pulses to signal neural states and chopping clocks to perform multiplication on these streams of pulses. Practical results, using custom VLSI devices, are presented. A second approach uses reduced precision arithmetic as the basis of a digital neural simulator and shows how this arithmetic technique can be used to solve neural problems. Simulation results confirm the viability of this method.
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46

Fan, Xinyue. "Intra-gate fault diagnosis of CMOS integrated circuits." Thesis, University of Oxford, 2006. http://ora.ox.ac.uk/objects/uuid:0cd2ed35-1e98-427e-a402-a27fd50752d1.

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Knowing the root cause of why an Integrated Circuit (1C) device fails to function properly is the key to provide the corrective measures to increase the yield and shorten the time to market. In recent years, electrical fault diagnosis method has received growing attention due to the effective and indispensable guiding role it plays in modern fault localization practice when physical measures are more and more confined by the shrinking feature size and condensed internal structure. While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the tran
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47

SamadiBoroujeni, MohammadReza. "High performance CMOS integrated circuits for optical receivers." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1108.

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48

Yang, Hai-Gang. "Timing verification in digital CMOS VLSI design." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387095.

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49

Li, Bo. "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00782429.

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Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédicti
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50

Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.

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