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Journal articles on the topic 'Digital CMOS integrated circuits'

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Published: 4 June 2021

Last updated: 6 February 2022

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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de Sousa, J. J. H. T., F. M. Goncalves, and J. P. Teixeira. "Physical design of testable CMOS digital integrated circuits." IEEE Journal of Solid-State Circuits 26, no. 7 (1991): 1064–72. http://dx.doi.org/10.1109/4.92027.

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Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Mark, Andrew G., Emmanuel Suraniti, Jérôme Roche, et al. "On-chip enzymatic microbiofuel cell-powered integrated circuits." Lab on a Chip 17, no. 10 (2017): 1761–68. http://dx.doi.org/10.1039/c7lc00178a.

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

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Daoming, Ke, Feng Yaolan, Tong Qinyi, and Ke Xiaoli. "Transient characteristic analysis of high temperature CMOS digital integrated circuits." Journal of Electronics (China) 11, no. 2 (1994): 104–15. http://dx.doi.org/10.1007/bf02778359.

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Song, Hang, Afreen Azhari, Xia Xiao, Eiji Suematsu, Hiromasa Watanabe, and Takamaro Kikkawa. "Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom." International Journal of Antennas and Propagation 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/6757048.

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A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS) integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T) switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

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Liu, Lun Cai, Xiao Zong Huang та Wen Gang Huang. "An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process". Applied Mechanics and Materials 251 (грудень 2012): 206–9. http://dx.doi.org/10.4028/www.scientific.net/amm.251.206.

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A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in a low-cost standard CMOS process with 0.6μm featured size, taking area of 600μm×150μm excluding the bonding pads.

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FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

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Aull, Brian. "Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits." Sensors 16, no. 4 (2016): 495. http://dx.doi.org/10.3390/s16040495.

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Wu, Kefei, Sriram Muralidharan, and Mona Mostafa Hella. "Decoupling Structures for Millimeter Wave Integrated Circuits in Digital CMOS Processes." IEEE Transactions on Electron Devices 65, no. 2 (2018): 788–92. http://dx.doi.org/10.1109/ted.2017.2780117.

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Frankiewicz, Maciej, and Andrzej Kos. "Maximum Temperature Detection System for Integrated Circuits." Journal of Electrical Engineering 66, no. 2 (2015): 79–84. http://dx.doi.org/10.1515/jee-2015-0012.

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Abstract The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

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Kalra, Shruti, та A. B. Bhattacharyya. "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model". Journal of Integrated Circuits and Systems 11, № 1 (2016): 57–68. http://dx.doi.org/10.29292/jics.v11i1.430.

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Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.

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Xu, Bin, Yong Gang Yuan, Ding Ma, Neng Bin Cai, and Xiang Yang Li. "Readout Integrated Circuits with Pixel-Level ADC for Ultraviolet FPA Applications." Applied Mechanics and Materials 229-231 (November 2012): 1499–502. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1499.

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An array of 128×128 digital pixel sensors (DPS) that performs both in pixel light current integration and analog-to-digital conversion is presented. The pixel fabricated on a DP4M CMOS process provides a digital output of ultraviolet light intensity via an integrated multiple-channel bit-serial (MCBS) ADC. Due to low light current (~pA) of ultraviolet focal-plane-array, the architecture of capacitive trans-impedance amplifier (CTIA) is used. The proposed readout integrated circuits have a 12-bit resolution, 70dB dynamic range and 99% of linearity.

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Kappert, Holger, Stefan Dreiner, Dirk Dittrich, et al. "High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000154–58. http://dx.doi.org/10.4071/hitec-wa14.

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Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper.

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Ramsay, E. P., D. T. Clark, J. D. Cormack, et al. "Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000373–77. http://dx.doi.org/10.4071/hitec-thp11.

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A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

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Kerkhoff, Hans G., and Hassan Ebrahimi. "Investigation of Intermittent Resistive Faults in Digital CMOS Circuits." Journal of Circuits, Systems and Computers 25, no. 03 (2015): 1640023. http://dx.doi.org/10.1142/s0218126616400235.

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No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50[Formula: see text]ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.

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Young, R. A. R., David T. Clark, Jennifer D. Cormack, et al. "High Temperature Digital and Analogue Integrated Circuits in Silicon Carbide." Materials Science Forum 740-742 (January 2013): 1065–68. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1065.

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Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in discrete power components, bringing system advantages such as reduced cooling requirements [1]. Therefore there is an emerging need for control ICs mounted on the same modules and being capable of operating at the same temperatures. In addition, several application areas are pushing electronics to higher temperatures, particularly sensors and interface devices required for aero engines and in deep hydrocarbon and geothermal drilling. This paper discusses a developing CMOS manufacturing process using a 4H SiC substrate, which has been used to fabricate a range of simple logic and analogue circuits and is intended for power control and mixed signal sensor interface applications [2]. Test circuits have been found to operate at up to 400°C. The introduction of a floating capacitor structure to the process allows the use of switched capacitor techniques in mixed signal circuits operating over an extended temperature range.

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Jung, Wee-Shin, Seung-Soo Kim, Yong-Guk Park, Kwang-Ho Won та Hyun-Chol Shin. "Indictor Library for RF Integrated Circuits in Standard Digital 0.18 μm CMOS Technology". Journal of Korean Institute of Electromagnetic Engineering and Science 18, № 5 (2007): 530–38. http://dx.doi.org/10.5515/kjkiees.2007.18.5.530.

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Honda, Wataru, Takayuki Arie, Seiji Akita, and Kuniharu Takei. "Bendable CMOS Digital and Analog Circuits Monolithically Integrated with a Temperature Sensor." Advanced Materials Technologies 1, no. 5 (2016): 1600058. http://dx.doi.org/10.1002/admt.201600058.

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Baze, M. P., W. G. Bartholet, J. C. Braatz, and T. A. Dao. "Single event upset test structures for digital CMOS application specific integrated circuits." IEEE Transactions on Nuclear Science 40, no. 6 (1993): 1703–8. http://dx.doi.org/10.1109/23.273490.

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Asghar, Malik Summair, Saad Arslan, and Hyungwon Kim. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits." Sensors 21, no. 13 (2021): 4462. http://dx.doi.org/10.3390/s21134462.

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To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

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HUNG, YU-CHERNG, SHAO-HUI SHIEH, and CHIOU-KOU TUNG. "A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 89–105. http://dx.doi.org/10.1142/s0218126611007104.

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Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.

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Carta, Fabio, Htay Hlaing, Hassan Edrees, Shyuan Yang, Mingoo Seok, and Ioannis Kymissis. "Co-development of complementary technology and modified-CPL family for organic digital integrated circuits." MRS Proceedings 1795 (2015): 19–25. http://dx.doi.org/10.1557/opl.2015.564.

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ABSTRACTWe present a novel logic family alternative to classic CMOS logic and its experimental demonstration for digital application of organic electronics. The proposed logic family is a modified version of the complementary pass-transistor logic (mCPL), which allows use of a stronger transistor (in our case the p-FET) to provide more of the current required to switch the capacitance in the device. We report the integration and characterization of this new class of gates and compare them with the equivalent CMOS structures. The characterization of inverters shows improved tolerance to process variation, up to 2.5× better delay, and 1.7× smaller area for the mCPL devices. Comparison of NOR and NAND gates shows 1.8× and 4.1× reduced gate delay. A 3× reduced energy consumption per operation is also simulated. The improved performance of the mCPL design makes it an alternative architecture for logic application of organic electronics.

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Appels, Karel, and Jeffrey Prinzie. "Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits." Electronics 9, no. 11 (2020): 1936. http://dx.doi.org/10.3390/electronics9111936.

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This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

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Kmon, P. "Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments." Bulletin of the Polish Academy of Sciences Technical Sciences 64, no. 3 (2016): 615–24. http://dx.doi.org/10.1515/bpasts-2016-0069.

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Abstract This paper presents techniques introduced to minimize both power and silicon area of the multichannel integrated recording circuits dedicated to biomedical experiments. The proposed methods were employed in multichannel integrated circuit fabricated in CMOS 180nm process and were validated with the use of a wide range of measurements. The results show that both a single recording channel and correction blocks occupy about 0.061 mm2 of the area and consume only 8.5 μW of power. The input referred noise is equal to 4.6 μVRMS. With the use of additional digital circuitry, each of the recording channels may be independently configured. The lower cut-off frequency may be set within the range of 0.1 Hz–700 Hz, while the upper cut-off frequency, depending on the recording mode chosen, can be set either to 3 kHz/13 kHz or may be tuned in the 2 Hz–400 Hz range. The described methods were introduced in the 64-channel integrated circuit. The key aspect of the proposed design is the fact that proposed techniques do not limit functionality of the system and do not deteriorate its overall parameters.

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Abedi, Zahra, Sameer Hemmady, Thomas Antonsen, Edl Schamiloglu, and Payman Zarkesh-Ha. "Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates." Energies 14, no. 10 (2021): 2906. http://dx.doi.org/10.3390/en14102906.

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In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

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Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.

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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>

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Kim, Min-Su, Youngoo Yang, Hyungmo Koo, and Hansik Oh. "The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology." Applied Sciences 11, no. 1 (2021): 429. http://dx.doi.org/10.3390/app11010429.

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To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (2000): 107–13. http://dx.doi.org/10.1155/2000/52658.

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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.

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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

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Sankar, P. A. Gowri, and G. Sathiyabama. "A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application." International Journal of Engineering Research in Africa 19 (October 2015): 19–36. http://dx.doi.org/10.4028/www.scientific.net/jera.19.19.

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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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Ryu, S., K. T. Kornegay, J. A. Cooper, and M. R. Melloch. "Monolithic CMOS digital integrated circuits in 6H-SiC using an implanted p-well process." IEEE Electron Device Letters 18, no. 5 (1997): 194–96. http://dx.doi.org/10.1109/55.568759.

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Marranghello, Felipe S., André I. Reis, and Renato P. Ribas. "Improving Analytical Delay Modelingfor CMOS Inverters." Journal of Integrated Circuits and Systems 10, no. 2 (2015): 123–34. http://dx.doi.org/10.29292/jics.v10i2.414.

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Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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Azaïs, Florence, Stéphane David-Grignot, Laurent Latorre, and François Lefevre. "Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits." Journal of Circuits, Systems and Computers 25, no. 03 (2015): 1640014. http://dx.doi.org/10.1142/s0218126616400144.

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This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140[Formula: see text]nm technology occupies only 7,885[Formula: see text][Formula: see text]m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

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Prinzie, Jeffrey, Karel Appels, and Szymon Kulis. "Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies." Electronics 8, no. 4 (2019): 432. http://dx.doi.org/10.3390/electronics8040432.

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This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Chiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front." Microscopy Today 7, no. 2 (1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.

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Although the Charge-Coupled Device (CCD) imaging chip is the standard in today's video and digital cameras, things may change during the coming year. The CCD chip is being challenged by a competing device, the CMOS ("C-moss") chip.CMOS is the most widely used type of integrated circuit for memory and digital processing, virtually everything in computers is CMOS based. The economies of scale and production of CMOS devices are the main reasons why computer prices have continued to drop during the past few years. If a device or an instrument has a microprocessor in it, chances are it includes CMOS technology..

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ZHANG, YAJING, WENGAO LU, GUANNAN WANG, ZHONGJIAN CHEN, and YACONG ZHANG. "A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA." Journal of Circuits, Systems and Computers 22, no. 09 (2013): 1340015. http://dx.doi.org/10.1142/s021812661340015x.

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A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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Caselli, Michele, Marco Ronchi, and Andrea Boni. "Power Management Circuits for Low-Power RF Energy Harvesters." Journal of Low Power Electronics and Applications 10, no. 3 (2020): 29. http://dx.doi.org/10.3390/jlpea10030029.

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The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments.

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Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.

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In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for future Integrated Circuits (ICs). A quantum dot cellular automaton complex gate is composed from simple 3-input majority gate. In this paper, a 8-3 encoder circuit is proposed based on QCA logic gates: the 4-input Majority Voter (MV) OR gate. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, 2-input AND and 2-input OR gates, 2-input complex gates, multi-input complex gates. The proposed circuit has a promising future in the area of nano-computing information processing system and can be stimulated with higher digital applications in QCA.

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Liu, Zilong, Xiaosuo Wu, Huifu Xiao, et al. "On-chip optical parity checker using silicon photonic integrated circuits." Nanophotonics 7, no. 12 (2018): 1939–48. http://dx.doi.org/10.1515/nanoph-2018-0140.

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AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.

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Huang, Tsung-Ching, Ting Lei, Leilai Shao, et al. "Process Design Kit and Design Automation for Flexible Hybrid Electronics." Journal of Microelectronics and Electronic Packaging 16, no. 3 (2019): 117–23. http://dx.doi.org/10.4071/imaps.925849.

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Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (&lt;50 μm) silicon chips on soft, thin, and flexible substrates for a wide range of applications, from flexible displays to wearable medical devices. Here, we report (1) a process design kit (PDK) to enable FHE design automation for large-scale FHE circuits and (2) solution process-proven intellectual property blocks for TFT circuits design, including Pseudo-Complementary Metal-Oxide-Semiconductor (Pseudo-CMOS) flexible digital logic and analog amplifiers. The FHE-PDK is fully compatible with popular silicon design tools for design and simulation of hybrid-integrated flexible circuits.

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LEE, JANGJOON, SRIKAR BHAGAVATULA, SWARUP BHUNIA, KAUSHIK ROY, and BYUNGHOO JUNG. "SELF-HEALING DESIGN IN DEEP SCALED CMOS TECHNOLOGIES." Journal of Circuits, Systems and Computers 21, no. 06 (2012): 1240011. http://dx.doi.org/10.1142/s0218126612400117.

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CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for a new design methodology that can provide high yield and reliability under severe parametric variations. Although several post-silicon calibration and repair strategies have been proposed to address the PVT variations, no coherent design strategy for a SoC has been developed so far. We espouse a self-healing technique based on real-time sensing and built-in feedback due to its inherent advantage of dynamic adaptation to temporal variations. This tutorial paper outlines our vision of improving marginalities in deep scaled CMOS technologies using a generic and systematic self-healing design including a system-level auto-correction algorithm. It also illustrates this methodology with design examples.

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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.

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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

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Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.

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Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.

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Ma, Dongsheng, and Chuang Zhang. "Thermal Compensation Method for CMOS Digital Integrated Circuits Using Temperature-Adaptive DC–DC Converter." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 11 (2006): 1284–88. http://dx.doi.org/10.1109/tcsii.2006.882346.

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Paschalidis, N. P., A. G. Andreou, and E. T. Sarris. "A CMOS analog-digital integrated circuit for charged particle spectrum measurements." IEEE Transactions on Nuclear Science 40, no. 4 (1993): 1313–18. http://dx.doi.org/10.1109/tns.1993.8526782.

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Wilkinson, Brian, Kent Walters, and Paul Ellerman. "High Temperature Characterization and Reliability Data of Key Semiconductor Technologies for Power and Control Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (2013): 000088–95. http://dx.doi.org/10.4071/hiten-mp16.

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An increasing number of extreme temperature operating applications require temperatures that can range from −65°C to 300°C, driving semiconductor suppliers to innovate new analog, digital, and mixed-signal solutions based on technologies including SiC, GaN, Si, SOI and CMOS. In addition, the paper will briefly highlight Microsemi's real-world results including characterization and reliability data on discrete power products including diodes and bridge rectifiers, and integrated circuits for demanding applications including down-hole drilling, commercial aviation, power sub-systems and power distribution in military vehicles.

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