Relevant bibliographies by topics / Digital controlled oscillator (DCO)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Digital controlled oscillator (DCO)'

Author: Grafiati
Published: 5 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Digital controlled oscillator (DCO)"

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Selvaraj, Santthosh, Erkan Bayram, and Renato Nega. "Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator." Technologies 9, no. 2 (2021): 38. http://dx.doi.org/10.3390/technologies9020038.

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This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.
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Zhao, Jun, and Yong-Bin Kim. "A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops." VLSI Design 2010 (January 19, 2010): 1–11. http://dx.doi.org/10.1155/2010/946710.

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A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset proces
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Zuo, Shi, Jianzhong Zhao та Yumei Zhou. "A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme". Electronics 10, № 7 (2021): 805. http://dx.doi.org/10.3390/electronics10070805.

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This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at
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LUO, ZHIHONG, YEUNG ON AU, BENJAMIN LAU, and HENRY LAW. "A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS." Journal of Circuits, Systems and Computers 21, no. 08 (2012): 1240026. http://dx.doi.org/10.1142/s0218126612400269.

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A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND
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Sheng, Duo, Wei-Yen Chen, Hao-Ting Huang, and Li Tai. "Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation." Sensors 21, no. 4 (2021): 1377. http://dx.doi.org/10.3390/s21041377.

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This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the
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Xu, Shuning, Lu Tang, and Junhao Yang. "Time-domain modelling and performance research of millimeter-wave all-digital phase-locked loop." Journal of Physics: Conference Series 2245, no. 1 (2022): 012018. http://dx.doi.org/10.1088/1742-6596/2245/1/012018.

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Abstract In this paper, a modified time-domain model of millimeter-wave all-digital phase-locked loop (ADPLL) is implemented. In order to reflect the true behaviour of ADPLL, a quantified output digitally controlled-oscillator (DCO) with time domain jitter is proposed. In this ADPLL time-domain model, the DCO model can only output discrete frequency points to imitate the quantization effect of true DCO, and the overlap of different level tuning band is added into this model to imitate the true situation. In addition, the DCO time domain jitter and wander are also added into this model by using
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Lim, Tae Ho, Ki Jin Kim, S. H. Park, and K. H. Ahn. "A Fast-Locking ADPLL with Time Measurable DCO." Advanced Materials Research 433-440 (January 2012): 6267–71. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.6267.

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This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.
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R, Swetha, J. Manjula, and A. Ruhan bevi. "Design of All Digital Phase Locked Loop for Wireless Applications." International Journal of Engineering & Technology 7, no. 3.12 (2018): 836. http://dx.doi.org/10.14419/ijet.v7i3.12.16513.

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This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.
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Ishak, S. N., J. Sampe, Z. Yusoff, and M. Faseehuddin. "ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW." Jurnal Teknologi 84, no. 1 (2021): 219–30. http://dx.doi.org/10.11113/jurnalteknologi.v84.17123.

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An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, th
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S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

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An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)
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Dissertations / Theses on the topic "Digital controlled oscillator (DCO)"

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Balasubramanian, Manikandan, and Saravana Prabhu Vijayanathan. "Design of a DCO for an All Digital PLL for the 60 GHz Band : Design of a DCO for an All Digital PLL for the 60 GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89134.

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The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages ov
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Suraparaju, Eswar Raju. "Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.

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Rosenthal, Glenn K. "A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM." International Foundation for Telemetering, 1991. http://hdl.handle.net/10150/613103.

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International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>Recent advancements in high-speed Digital Signal Processing (DSP) concepts and devices permit digital hardware implementation of relatively high-frequency signal processing, which formerly required analog circuitry. Systems utilizing this technology can provide a high degree of software programmability; improved reproducibility, reliability, and maintainability; immunity to temperature induced drift errors; and compare favorably in cost to their analog counterpar
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Jung, Seok Min, and Seok Min Jung. "Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/621292.

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The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generat
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Natali, Francis D., and Gerard G. Socci. "DIGITAL RECEIVER PROCESSING TECHNIQUES FOR SPACE VEHICLE DOWNLINK SIGNALS." International Foundation for Telemetering, 1985. http://hdl.handle.net/10150/615711.

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International Telemetering Conference Proceedings / October 28-31, 1985 / Riviera Hotel, Las Vegas, Nevada<br>Digital processing techniques and related algorithms for receiving and processing space vehicle downlink signals are discussed. The combination of low minimum signal to noise density (C/No), large signal dynamic range, unknown time of arrival, and high space vehicle dynamics that is characteristic of some of these downlink signals results in a difficult acquisition problem. A method for rapid acquisition is described which employs a Fast Fourier Transform (FFT). Also discussed are digi
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Girija, Satyanarayana, and J. Girija. "PC- Based S-Band Down Converter / FM Telemetry Receivers." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611444.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Di
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Yoder, Samantha. "Analysis and Modeling of Non-idealities in VCO-Based Quantizers Using Frequency-to-Digital and Time-to-Digital Converters." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1283951960.

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Hordeski, Theodore J. "Digital FSK/AM/PM Sub-Carrier Modulator on a 6U-VME-Card." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611475.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a si
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Pham, Long. "Lookup-Table-Based Background Linearization for VCO-Based ADCs." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/586.

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Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to
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Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.

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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a syste
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Book chapters on the topic "Digital controlled oscillator (DCO)"

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Abdollahi, S. R., B. Bakkaloglu, and S. K. Hosseini. "A Fully Digital Numerical-Controlled-Oscillator." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39762-5_45.

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Swathi, Y., and N. Mohankumar. "Design and FPGA Realization of Digital Lightweight Numerically Controlled Quadrature Wave Oscillator." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2612-1_53.

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"Digitally Controlled Oscillator." In All-Digital Frequency Synthesizer in Deep-Submicron CMOS. John Wiley & Sons, Inc., 2005. http://dx.doi.org/10.1002/9780470041956.ch2.

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"LowLatency, HighSpeed Numerically Controlled Oscillator Using ProgressionorStates Technique." In Direct Digital Frequency Synthesizers. IEEE, 2010. http://dx.doi.org/10.1109/9780470544396.ch8.

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"An Exact Spectral Analysis of a Number Controlled Oscillator Based Synthesizer." In Direct Digital Frequency Synthesizers. IEEE, 2010. http://dx.doi.org/10.1109/9780470544396.ch15.

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"A 700MHz 24b Pipelined Accumulator in 1.2m CMOS for Application as a Numerically Controlled Oscillator." In Direct Digital Frequency Synthesizers. IEEE, 2010. http://dx.doi.org/10.1109/9780470544396.ch43.

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Conference papers on the topic "Digital controlled oscillator (DCO)"

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Snehalatha, G., and Podduturi Vineetha. "Design of Computation-in-Memory Using ReRAM and Voltage Controlled Oscillator based Analog to Digital converter." In 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE). IEEE, 2024. http://dx.doi.org/10.1109/icspcre62303.2024.10675139.

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Hu, Zerong, Donghang Wang, Zekuan Lin, Shaolin Liao, and Xianbo Li. "A Time-to-Digital Converter Employing a Voltage-Controlled Ring Oscillator with High Gain Linearity for LiDAR Applications." In 2025 IEEE 8th Information Technology and Mechatronics Engineering Conference (ITOEC). IEEE, 2025. https://doi.org/10.1109/itoec63606.2025.10968027.

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Kitaike, Hiroaki, Masaharu Inada, Mitsuru Terauchi, et al. "A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631372.

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Elrabaa, Muhammad E. S. "A portable high-frequency digitally controlled oscillator (DCO)." In the 23rd ACM international conference. ACM Press, 2013. http://dx.doi.org/10.1145/2483028.2483065.

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Jafarzade, Samira, and Abumoslem Jannesari. "A precise ΔΣ-based Digitally Controlled Oscillator (DCO) for all-digital PLL." In 2013 21st Iranian Conference on Electrical Engineering (ICEE). IEEE, 2013. http://dx.doi.org/10.1109/iraniancee.2013.6599744.

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Giebel, Burkhard, Jurgen Lutz, and Paul O'Leary. "Digital Controlled Oscillator." In Fourteenth European Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/esscirc.1988.5468292.

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Lou, Liheng, Bo Chen, Kai Tang, and Yuanjin Zheng. "A CMOS digital-controlled oscillator for All-digital PLL frequency synthesizer." In 2016 International Symposium on Integrated Circuits (ISIC). IEEE, 2016. http://dx.doi.org/10.1109/isicir.2016.7829720.

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Badarov, Dimiter Hristov, and Georgy Slavchev Mihov. "Studying Digitally Controlled Oscillator Circuits for Digital Phase Synchronizers." In 2019 IEEE XXVIII International Scientific Conference Electronics (ET). IEEE, 2019. http://dx.doi.org/10.1109/et.2019.8878655.

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Raghunandan, K. R., T. Lakshmi Viswanathan, and T. R. Viswanathan. "Linear current-controlled oscillator for analog to digital conversion." In 2014 IEEE Custom Integrated Circuits Conference - CICC 2014. IEEE, 2014. http://dx.doi.org/10.1109/cicc.2014.6946121.

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Khalirbaginov, Rustam, and Haymin Alexandr. "Novel HDL design of Digital Controlled Oscillator for ADPLL." In 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2019. http://dx.doi.org/10.1109/eiconrus.2019.8657238.

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