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Balasubramanian, Manikandan, and Saravana Prabhu Vijayanathan. "Design of a DCO for an All Digital PLL for the 60 GHz Band : Design of a DCO for an All Digital PLL for the 60 GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89134.
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The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages over analog counterpart when they arecompared with each other. Digital circuit could be scaled down or scaled up evenafter the circuits were designed. It could be designed for low power supply voltageand easy to construct in a 65 nm process. The digital circuit was widely chosento make life easier. In most of the application PLL’s were used for clock and data recovery purpose,from that perspective jitter will stand as a huge problem for the designers. Themain aim of this thesis was to design a DCO that should bring down the jitter asdown as possible which was designed as standalone, the designed DCO would belater placed in an all-digital PLL. To understand the concept and problem aboutjitter at the early stage of the project, an analog PLL was designed in block leveland tested for different types of jitter and then design of a DCO was started. This document was about the design of a digitally controlled oscillator whichoperates with the center frequency of 2.145 GHz. In the first stage of the projectthe LC tank with NMOS structure was built and tested. In the latter stage the LCtank was optimized by using PMOS structure as negative resistance and eventuallyended up with NMOS and PMOS cross coupled structure. Tuning banks were oneof the main design in this project which plays a key role in locking the system ifthe DCO is placed in an all-digital PLL system. So, three types of tuning bankswere introduced to make the system lock more precisely. The control circuits andthe varactors built were all digital and hence it is called as digitally controlledoscillator. Digital control circuits, other sub-blocks like differential to single endedand simple buffers were also designed to optimize the signal and the results wereshown.DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shownin the final chapter simulation and results.
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Suraparaju, Eswar Raju. "Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.
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Rosenthal, Glenn K. "A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM." International Foundation for Telemetering, 1991. http://hdl.handle.net/10150/613103.
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International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>Recent advancements in high-speed Digital Signal Processing (DSP) concepts and devices permit digital hardware implementation of relatively high-frequency signal processing, which formerly required analog circuitry. Systems utilizing this technology can provide a high degree of software programmability; improved reproducibility, reliability, and maintainability; immunity to temperature induced drift errors; and compare favorably in cost to their analog counterparts.
This paper describes the DSP implementation of a software programmable, digital frequency multiplexed FM system providing up to 4 output multiplexes, containing up to 36 subcarrier channels extending up to 4 MHZ, and accommodating modulating frequencies up to 64 kHz. System overall design goals and the implementation of these goals are presented.
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Jung, Seok Min, and Seok Min Jung. "Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/621292.
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The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.
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Natali, Francis D., and Gerard G. Socci. "DIGITAL RECEIVER PROCESSING TECHNIQUES FOR SPACE VEHICLE DOWNLINK SIGNALS." International Foundation for Telemetering, 1985. http://hdl.handle.net/10150/615711.
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International Telemetering Conference Proceedings / October 28-31, 1985 / Riviera Hotel, Las Vegas, Nevada<br>Digital processing techniques and related algorithms for receiving and processing space vehicle downlink signals are discussed. The combination of low minimum signal to noise density (C/No), large signal dynamic range, unknown time of arrival, and high space vehicle dynamics that is characteristic of some of these downlink signals results in a difficult acquisition problem. A method for rapid acquisition is described which employs a Fast Fourier Transform (FFT). Also discussed are digital techniques for precise measurement of space vehicle range and range rate using a digitally synthesized number controlled oscillator (NCO).
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Girija, Satyanarayana, and J. Girija. "PC- Based S-Band Down Converter / FM Telemetry Receivers." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611444.
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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.
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Yoder, Samantha. "Analysis and Modeling of Non-idealities in VCO-Based Quantizers Using Frequency-to-Digital and Time-to-Digital Converters." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1283951960.
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Hordeski, Theodore J. "Digital FSK/AM/PM Sub-Carrier Modulator on a 6U-VME-Card." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611475.
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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.
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Pham, Long. "Lookup-Table-Based Background Linearization for VCO-Based ADCs." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/586.
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Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to-noise (SNR) performance better than -40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. A further challenge is implementing calibration without degrading energy efficiency performance. This thesis project discusses a complete design of a 10 bit three stage ring VCO-based ADC. A lookup-table (LUT) digital correction technique enabled by the "Split ADC" calibration approach is presented suitable for linearization of the ADC. An improvement in the calibration algorithm is introduced to ensure LUT continuity. Measured results for a 10 bit 48.8-kSps ADC show INL improvement of 10X after calibration convergence.
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Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.
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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.
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Klecl, Martin. "Digitální elektronický hudební syntezátor s analogovým řízením pro platformu Eurorack." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399607.
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This work explores the topic of digital audio signal processing for modular synthesizers and the design of digital oscillator for modular standard known as Eurorack. Introduction of the theoretical part is dedicated to basic terms and blocks used in modular synthesizers. The thesis also characterizes and presents the methods of sound synthesis. The second part of the theory concerns analog and digital signal conversion made by digital signal processors DSP, focusing on ARM with focus on ARM architecture. The practical part of the thesis concerns design and construction of the digital oscillator which generates periodic waveforms without aliasing distortion. The oscillator also allows several types of modulations and waveforming and the module has several inputs for connecting control voltages or external audio signals.
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Opperman, Tjaart Adriaan Kruger. "A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method." Diss., Pretoria : [s.n.], 2009. http://upetd.up.ac.za/thesis/available/etd-04082009-171225/.
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Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009.<br>Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.
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Carvalho, Paulo Roberto Bueno de. "Projeto de circuito oscilador controlado numericamente implementado em CMOS com otimização de área." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26012017-085719/.
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Este trabalho consiste no projeto e implementação em CMOS de um circuito integrado digital para geração de sinais, denominado Oscilador Controlado Numericamente. O circuito será aplicado em um sistema de Espectroscopia por Bioimpedância Elétrica, utilizado como método para detecção precoce de câncer do colo do útero. Durante o trabalho, realizou-se o estudo dos requisitos do sistema de espectroscopia e as especificações dos tipos de sinais a serem gerados. Levantou-se, na bibliografia, algumas técnicas de codificação em linguagem de hardware para otimização do projeto nos quesitos área, potência dissipada e frequência máxima de funcionamento. Para implementar o circuito, também se pesquisou o fluxo de projeto de circuitos digitais, focando as etapas de codificação em linguagem de descrição de hardware Verilog e os resultados de síntese lógica e de layout. Foram avaliadas duas arquiteturas, empregando-se algumas das técnicas de codificação levantadas durante o estudo bibliográfico. Estas arquiteturas foram implementadas, verificadas em plataforma programável, sintetizadas e mapeadas em portas lógicas no processo TSMC 180 nm, onde foram comparados os resultados de área e dissipação de potência. Observou-se, nos resultados de síntese lógica, redução de área de 78% e redução de 83% na dissipação de potência total no circuito em que se aplicou uma das técnicas de otimização em comparação com o circuito implementado sem otimização, utilizando uma arquitetura CORDIC do tipo unrolled. A arquitetura com menor área utilizada - 0,017 mm2 - foi escolhida para fabricação em processo mapeado. Após fabricação e encapsulamento do circuito, o chip foi montado em uma placa de testes desenvolvida para avaliar os resultados qualitativos. Os resultados dos testes foram analisados e comparados aos obtidos em simulação, comprovando-se o funcionamento do circuito. Observou-se uma variação máxima de 0,00623% entre o valor da frequência do sinal de saída obtido nas simulações e o do circuito fabricado.<br>The aim of this work is the design of a digital integrated circuit for signal generation called Numerically Controlled Oscillator, designed in 180 nm CMOS technology. The application target is for Electrical Bioimpedance Spectroscopy system, and can be used as a method for early detection of cervical cancer. Throughout the work, the spectroscopy system requirements and specifications of the types of signals to be generated were studied. Furthermore, the research of some coding techniques in hardware language for design optimization in terms of area, power consumption and frequency operation was conducted looking into the bibliography. The digital design flow was studied focusing on the Verilog hardware description language and the results of logic synthesis and layout, in order to implement the circuit. Reviews of two architectures have been made, using some of the encoding techniques that have been raised during the bibliographical study. These architectures have been implemented, verified on programmable platform, synthesized and mapped to standard cells in TSMC 180 nm process, which compared the area and total power consumption of results. Based on the results of logic synthesis, a 78% area reduction and 83% power consumption reduction were obtained on the implemented circuit with encoding techniques for optimization in comparison with the another circuit using a CORDIC unrolled architecture. The architecture with smaller area - 0.017 mm2 - was chosen for implementation in the mapped process. After the circuit fabrication and packaging, the chip was mounted on an evaluation board designed to evaluate the functionality. The test results were analyzed and compared with the simulation results, showing that the circuit works as expected. The output signals were compared between theoretical and experimental results, showing a maximum deviation of 0.00623%.
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"Design of CMOS digital controlled oscillator (DCO)." 1998. http://library.cuhk.edu.hk/record=b5889586.
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by Cheuk-Him, To.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.<br>Includes bibliographical references.<br>Abstract also in Chinese.<br>ACKNOWLEDGMENT --- p.I<br>ABSTRACT (ENGLISH) --- p.II<br>ABSTRACT (CHINESE) --- p.III<br>CONTENTS --- p.IV<br>TABLE OF FIGURES --- p.VI<br>Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1<br>Chapter 1.1 --- Introduction --- p.1-1<br>Chapter 1.2 --- Different types of DCO --- p.1-2<br>Chapter 1.2.1 --- Divided by N counter --- p.1-2<br>Chapter 1.2.2 --- Increment-decrement counter --- p.1-2<br>Chapter 1.2.3 --- Controlled delay ring oscillator --- p.1-4<br>Chapter 1.3 --- Problems suffered from these circuits --- p.1-4<br>Chapter 1.4 --- Characteristics of the proposed circuit --- p.1-5<br>Chapter CHAPTER 2 --- BACKGROUND THEORY --- p.2-1<br>Chapter 2.1 --- Ring Oscillator --- p.2-1<br>Chapter 2.2 --- Differential Pair --- p.2-1<br>Chapter 2.3 --- Injection Locked Oscillator (ILO) --- p.2-2<br>Chapter 2.4 --- Digital Controlled Oscillator --- p.2-3<br>Chapter CHAPTER 3 --- DESIGN --- p.3-1<br>Chapter 3.1 --- Circuit Description --- p.3-1<br>Chapter 3.1.1 --- D/A converter --- p.3-2<br>Chapter 3.1.2 --- Injection Locked Oscillator (ILO) --- p.3-3<br>Chapter 3.2 --- Design Characteristics --- p.3-5<br>Chapter 3.2.1 --- D/A converter --- p.3-5<br>Chapter 3.2.2 --- ILO --- p.3-7<br>Chapter 3.2.3 --- Physical Design (Layout Drawing) --- p.3-8<br>Chapter CHAPTER 4 --- RESULTS --- p.4-1<br>Chapter 4.1 --- Chip1 --- p.4-1<br>Chapter 4.1.1 --- Simulation --- p.4-3<br>Chapter 4.1.2 --- Measurement --- p.4-15<br>Chapter 4.1.3 --- Evaluation --- p.4-23<br>Chapter 4.2 --- Chip2 --- p.4-25<br>Chapter 4.2.1 --- Simulation --- p.4-25<br>Chapter 4.2.2 --- Measurement --- p.4-36<br>Chapter 4.2.3 --- Evaluation --- p.4-47<br>Chapter CHAPTER 5 --- CONCLUSION --- p.5-1<br>REFERENCES: --- p.1<br>APPENDIX: --- p.1
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Ζωγράφος, Βασίλης. "Σχεδίαση και ανάπτυξη ψηφιακά ελεγχόμενου ταλαντωτή (Digitally Controlled Oscillator) στις συχνότητες 1.6-2 GHz". Thesis, 2013. http://hdl.handle.net/10889/7866.
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Σε αυτήν την εργασία μελετήθηκε και σχεδιάστηκε ένας ψηφιακά ελεγχόμενος ταλαντωτής (DCO) με σκοπό GSM εφαρμογή. Οι συχνότητες λειτουργίας κυμαίνονται στο φάσμα 1.6GHz – 2GHz με βήμα 20kHz. Ο θόρυβος φάσης ποσοτικοποιείται στα -160dB/Hz σε 20 MHz απόκλιση. Ο έλεγχος του DCO γίνεται πλήρως ψηφιακά επιτρέποντας την υλοποίηση πλήρους ψηφιακού βρόχου κλειδώματος φάσης (ADPLL) και καθολικού system on chip design (SoC). Ο ταλαντωτής καταναλώνει 4,5 mWatt με 3,76 mA ρεύμα σε 1.2 V τροφοδοσία.<br>A Digitally Controlled Oscillator is studied and designed for GSM application. The operating frequencies are 1.6-2GHz with tuning range of 400MHz and finest step size 20 KHz. A fully digital control is achieved form where arises the opportunity for fabrication of an All-Digital Phase Locked Loop (ADPLL) and the whole system on chip (SoC). The proposed DCO core consumes 3.76mA from a 1.2V supply.
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Hsu, Li-Fan, and 徐立凡. "ALL DIGITAL PHASE-LOCKED LOOP WITH HIGH RESOLUTION DIGITAL CONTROLLED OSCILLATOR." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03532117016625588613.
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碩士<br>大同大學<br>通訊工程研究所<br>98<br>In this thesis, we implement an all digital phase locked loop (ADPLL) with high resolution digital controlled oscillator. We use time to digital converter to quantize phase error and use a high resolution ring oscillator to be the digital controlled oscillator in the circuit. Working frequency ranges for this ADPLL is about 212~366MHz. When reference signal is 5MHz and a multiplication factor of 64, the lock-in time is about 3.5 s. The feasibility and performance of the ADPLL is verified with the MATLAB Simulink.
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Adhikari, Soumalya, Saptarshi Pal Choudhuri, and Supriya Sneha. "Study of voltage controlled oscillator based analog-to-digital converter." Thesis, 2011. http://ethesis.nitrkl.ac.in/2272/1/thesis.pdf.
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A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This thesis analyzes the performance of VCO-based ADCs in the presence of non idealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described.
Further, the study involves the use of VCO based Dual-slope A/D converter and its behaviour under different input voltage level. Graph is plotted between output voltages of the integrator vs. time. Digital circuits like a bit-counter and logic circuits are used for operation mode. A normal VCO model is also done in MATLAB-simulink environment and studied under variable input frequency and corresponding output plots are viewe
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賴榮欽. "The study of Wideband, Cell-based Digital Controlled Oscillator and its Implementations." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/97138953753733432566.
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碩士<br>國立交通大學<br>理學院碩士在職專班應用科技學程<br>96<br>The thesis is based on All-digital-Phase-Locked- Loops (ADPLL).. We will discuss wide band, cell-based digital controlled oscillator (DCO) in this thesis. In our design, there is a wide bandwidth DCO. The frequency is from 0.66~ 460MHz step by 2.16ns. It is designed by Digital-to-Time (DTC) scheme. We also use AOI and OAI as Fine-tune cells. The best resolution of this design is 0.01 pico-seconds. We use UMC 90nm standard cell AOI to get this performance. In another way, we put current mirror in DCO for reduction of bounce noise. That will effectively reduce jitter caused by ground bounce. The wide bandwidth DCO use DTC to do the internal count for different bandwidth. That is a double loops scheme. AOI cell is the standard cell for fine tune solution. When we change the control bits of AOI, it change the capacitance of additional capacitor. The resolution of 0.01 pico-seconds is a good performance for DCO design. The output jitter is another issue. When the design is working, the transient current will make a serious ground bounce. It is the major source of jitter. How to reduce the ground bounce and jitter is the important topic for DCO design. Here we use current mirror to reduce the ground bounce and make the clean signal.
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Yeh, Chi-Lung, and 葉啟龍. "A Novel Structure of Digitally Controlled Oscillator for All-Digital Phase-Locked Loop." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/14350903718844927363.
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碩士<br>國立中興大學<br>電機工程學系<br>91<br>This thesis describes the architecture and design of digitally controlled oscillator（DCO） for all-digital phase-locked loop（ADPLL）, which uses a novel structure to improve the drawback of the traditional DCO structure. The proposed DCO design has characteristics of superior linearity, better oscillatory waveform, smaller Jitter, and higher oscillatory frequency. The novel DCO has a 14-bit digitally controlled word and is implemented by the TSMC 0.35μm 1P4M technology. The supply voltage is 3V.
The simulation results show 14-bit resolution of DCO. When DCO operates with digitally controlled words of 0 ~ 16383, the frequency range is 860 MHz ~ 1.328 GHz. The jitter is 0.13 ps at a center frequency of 1.1GHz. The least significant bit resolution（LSB resolution）is 22.5 fs.
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Lin, Chien-Li, and 林建禮. "Design of an All-Digital Frequency Synthesizer with a Temperature Compensated Digitally Controlled Oscillator." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/6hrvxy.
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碩士<br>國立交通大學<br>電機工程學系<br>103<br>This thesis presents a design of the clock generator for the application of GALS (Globally-Asynchronous Locally-Synchronous) system. The clock source has the ability of fast-locking and alleviating the impact of output frequency deviation due to temperature variations.
The all-digital frequency-locked loop generates the output frequency of the digitally controlled oscillator as the target frequency first by means of negative feedback. Then the feedback loop was disconnected and the oscillator tuning word was kept so that the oscillator outputs the target frequency at free-running to serve as the clock source that the GALS system needs. By doing so, the clock generator does not need a continuous reference clock. Hence, the reference clock generator can then be shutdown. SoC system can save much of the silicon area and its power, which makes it much more attractive.
Since the open-loop oscillator's output frequency is sensitive to the supply voltage and temperature variations, we propose a temperature compensated circuit design to make it less sensitive to temperature variations.
To achieve fast lock-in, the Regula Falsi method has been used in the design of the all-digital frequency-locked loop. When the output frequency is closed to the expected frequency, the loop switches to a closed loop with a digital filter. Initially, the filter is set to have a wide bandwidth for a faster locking process. After the output frequency is locked to the expected frequency, the filter's bandwidth is set to a smaller one for stable output frequency. Measurement results show that the lock-in process is less than 11 cycles at its worst.
To address the output frequency deviations of the free-running digitally controlled oscillator due to the temperature variations, a constant-gm circuit is used to alleviate the parameter change of the transistors in the delay cells. In particular, the proposed method works under different control voltages.
A test chip has been implemented in TSMC 0.18μm CMOS technology. The core area is 0.239 〖mm〗^2 and the whole-chip area with bonding pads is 0.895 〖mm〗^2. Measurement results show that the chip can operate correctly when the output frequency is between 1.85 GHz and 3.0 GHz. When the output frequency is 2.4 GHz, the lock-in time needs 7 reference cycles. The measured rms jitter is 0.545% unit-interval (U.I.) and the peak-to-peak jitter is 4.334% unit-interval (U.I.). The phase noise spectral density at 1 MHz offset is measured to be -84.09(dBc/Hz). The power consumption of the core circuits is 17.74 mW.
The measured effective temperature coefficient of the free-running digitally controlled oscillator is 186 ppm/℃ in the range between -40℃ and 100℃.
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Lan, Jhih-Ci, and 藍志錡. "Low-Power And Delay Monotonicity Digitally Controlled Oscillator For All-Digital Phase-Locked Loop Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/26786096094798248691.
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碩士<br>輔仁大學<br>電機工程學系<br>100<br>In this thesis, a low-power and delay monotonicity digitally controlled oscillator (DCO) for all-digital phase-locked loop (ADPLL) applications is presented. The proposed DCO can achieve high delay resolution, wide frequency range and low power consumption while maintaining delay monotonicity that can easily be used to different ADPLL applications. Besides, the proposed DCO is portable that can easily migrate to different technology. As a result, the proposed design is very suitable for system-on-chip (SoC) applications.
There are two type DCO structures have been proposed: interpolator DCO and varactor-interpolator DCO. The proposed interpolator DCO power consumption is 0.3368 mW at 1118 MHz, the delay resolution is 0.82 ps and the delay range is 424~1118 MHz in 90 nm CMOS process technology. The varactor-interpolator DCO power consumption is 0.2053 mW at 838 MHz, the delay resolution is 2.98 ps and the delay range is 322~838 MHz in 90 nm CMOS process technology.
The proposed DCO is integrated into an ADPLL which is an important clocking module in SoC applications. The proposed design of ADPLL is discussed with some simple block that can use gate-level or Verilog Hardware Description Language (Verilog HDL) to implement. So, the design time and design complexity can be reduced by using Verilog HDL.
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Tang, Yi Fu, and 湯益福. "A 12-bit Time-Domain Analog-to-Digital Converter With a Multiphase Voltage-Controlled Oscillator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93859287530846279552.
Full textAbstract:
碩士<br>長庚大學<br>電機工程學系<br>100<br>This thesis intends to discuss on how to construct an analog-to-digital conveter (ADC) by using the conversion of time-domain signals. We try to transform the analog voltage signal into digital time-pulse signal hence to form the digitally assisted analog circuit design. In theorical view, while the characteristic length of CMOS gates continuously shrinks to the nano-meter scale, the variations of analog signal increase, the current leakage of gates increases, and the open loop gain decreases…etc., more and more disadvantages occur. Since the accuracy and stability of analog voltage have been decreased ever, researchers want to use the digital signals and circuits to assist traditional analog structures with their advantage of scaling, for example, faster gates and lower power.
Here we construct a conversion system including multiphase voltage-controlled oscillator (VCO), 6-bit time domain analog-to-digital converter (coarse controller), and 6-bit multiphase time-to-digital converter (fine controller). The VCO oscillates at 1 GHz with 16 phases for the fine controller and a frequency divider that provides the counting frequency and sampling frequency for the system. The coarse controller transforms the analog voltage input into time-pulse signals by the ramp generator. The combination of coarse controller and ramp calibrator has enhanced the reliablility of the ramp hence makes the conversions under accurate range of voltage. The fine controller uses the 16 phases from VCO and combines the novel phase expander circuit, it not only increases the resolution, but also has the advantages such as monotonicity of phase triggering and variations resisting due to the synchronization of phases and sampling frequency. The fine controller collects the time residue of the coarse conversion and calculates the time residue to gain extra resolution thus increase the overall accuracy of the system.
This thesis uses the TSMC 0.18μm 1P6M Mixed Signal process to tapeout, the supply voltage is 1.8 V, the sampling frequency is 1 MHz, the counting frequency is 256 MHz, and the phase frequency is 1.024 GHz. The total power dissipation measured is 50.7 mW, the chip size (including pads) is 1.02 mm2, the core circuit size is 0.25 mm2. By simulation: The input signal is about 10 KHz and the results of coarse controller are 36.3 dB for signal-to-noise-and-distortion ratio (SNDR) and 41.5 dB for spurious-free dynamic range (SFDR). The fine controller has differential nonlinearity (DNL) less than 0.25 LSB and integral nonlinearity (INL) less than 0.48 LSB. By measurement: The jitter of the VCO is 10 ps under 10,000 hits of clock, and the dynamic verification has obtained 36.3 dB for SNDR, 44.8 dB for SFDR, and 5.74 bits for ENOB.
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Yeke, Yazdandoost Mohammad. "Photon Quantum Noise Limited Pixel and Array architectures in a-Si Technology for Large Area Digital Imaging Applications." Thesis, 2011. http://hdl.handle.net/10012/6220.
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A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application.
Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time.
A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work
v
aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.
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Turker, Didem 1981. "Frequency Synthesis in Wireless and Wireline Systems." Thesis, 2010. http://hdl.handle.net/1969.1/148459.
Full textAbstract:
First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed.
Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency
synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed
delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output
waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation.
We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the
proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption.
An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial
link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology
without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability
of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting
mechanisms.
The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control
complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter
and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.
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Kliko, Roman Vladimirovitch. "Design of a Digital Temperature Sensor based on Thermal Diffusivity in a Nanoscale CMOS Technology." Master's thesis, 2016. http://hdl.handle.net/10362/82837.
Full textAbstract:
Temperature sensors are widely used in microprocessors to monitor on-chip temperature gradients and hot-spots, which are known to negatively impact reliability. Such sensors should be small to facilitate floor planning, fast to track millisecond thermal transients, and easy to trim to reduce the associated costs. Recently, it has been shown that thermal diffusivity (TD) sensors can meet these requirements. These sensors operate by digitalizing the temperature-dependent delay associated with the diffusion of heat pulses through an electro-thermal filter (ETF), which, in standard CMOS, can be readily implemented as a resistive heater surrounded by a thermopile. Unlike BJT-based temperature sensors, their accuracy actually improves with CMOS scaling, since it is mainly limited by the accuracy of the heather/thermopile spacing. In this work is presented the electrical design of an highly digital TD sensor in 0.13 µm CMOS with an accuracy better than 1 ºC resolution at with 1 kS/s sampling rate, and which compares favourably to state-of-the-art sensors with similar accuracy and sampling rates [1][2][3][4]. This advance is mainly enabled by the adoption of a highly digital CCO-based phasedomain ΔΣ ADC. The TD sensor presented consists of an ETF, a transconductance stage, a current-controlled oscillator (CCO) and a 6 bit digital counter. In order to be easily ported to nanoscale CMOS technologies, it is proposed to use a sigmadelta modulator based on a CCO as an alternative to traditional modulators. And since 70% of the sensor’s area is occupied by digital circuitry, porting the sensor to latest CMOS technologies process should reduce substantially the occupied die area, and thus reduce significantly the total sensor area.
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Elshazly, Amr. "Performance enhancement techniques for low power digital phase locked loops." Thesis, 2012. http://hdl.handle.net/1957/31116.
Full textAbstract:
Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions.
In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.<br>Graduation date: 2013<br>Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014