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Journal articles on the topic 'Digital controlled oscillator (DCO)'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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1

Selvaraj, Santthosh, Erkan Bayram, and Renato Nega. "Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator." Technologies 9, no. 2 (2021): 38. http://dx.doi.org/10.3390/technologies9020038.

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This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.

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2

Zhao, Jun, and Yong-Bin Kim. "A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops." VLSI Design 2010 (January 19, 2010): 1–11. http://dx.doi.org/10.1155/2010/946710.

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A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset proces

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3

Zuo, Shi, Jianzhong Zhao та Yumei Zhou. "A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme". Electronics 10, № 7 (2021): 805. http://dx.doi.org/10.3390/electronics10070805.

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This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at

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4

LUO, ZHIHONG, YEUNG ON AU, BENJAMIN LAU, and HENRY LAW. "A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS." Journal of Circuits, Systems and Computers 21, no. 08 (2012): 1240026. http://dx.doi.org/10.1142/s0218126612400269.

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A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND

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5

Sheng, Duo, Wei-Yen Chen, Hao-Ting Huang, and Li Tai. "Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation." Sensors 21, no. 4 (2021): 1377. http://dx.doi.org/10.3390/s21041377.

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This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the

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6

Xu, Shuning, Lu Tang, and Junhao Yang. "Time-domain modelling and performance research of millimeter-wave all-digital phase-locked loop." Journal of Physics: Conference Series 2245, no. 1 (2022): 012018. http://dx.doi.org/10.1088/1742-6596/2245/1/012018.

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Abstract In this paper, a modified time-domain model of millimeter-wave all-digital phase-locked loop (ADPLL) is implemented. In order to reflect the true behaviour of ADPLL, a quantified output digitally controlled-oscillator (DCO) with time domain jitter is proposed. In this ADPLL time-domain model, the DCO model can only output discrete frequency points to imitate the quantization effect of true DCO, and the overlap of different level tuning band is added into this model to imitate the true situation. In addition, the DCO time domain jitter and wander are also added into this model by using

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7

Lim, Tae Ho, Ki Jin Kim, S. H. Park, and K. H. Ahn. "A Fast-Locking ADPLL with Time Measurable DCO." Advanced Materials Research 433-440 (January 2012): 6267–71. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.6267.

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This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.

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8

R, Swetha, J. Manjula, and A. Ruhan bevi. "Design of All Digital Phase Locked Loop for Wireless Applications." International Journal of Engineering & Technology 7, no. 3.12 (2018): 836. http://dx.doi.org/10.14419/ijet.v7i3.12.16513.

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This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

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9

Ishak, S. N., J. Sampe, Z. Yusoff, and M. Faseehuddin. "ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW." Jurnal Teknologi 84, no. 1 (2021): 219–30. http://dx.doi.org/10.11113/jurnalteknologi.v84.17123.

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An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, th

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10

S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

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An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)

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Radhapuram, Saichandrateja, Takuya Yoshihara, and Toshimasa Matsuoka. "Design and Emulation of All-Digital Phase-Locked Loop on FPGA." Electronics 8, no. 11 (2019): 1307. http://dx.doi.org/10.3390/electronics8111307.

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This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the

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Jurgo, Marijan, and Romualdas Navickas. "Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications." Electronics 8, no. 1 (2018): 29. http://dx.doi.org/10.3390/electronics8010029.

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In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TD

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13

Biereigel, Stefan, Szymon Kulis, Paulo Moreira, Alexander Kölpin, Paul Leroux, and Jeffrey Prinzie. "Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS." Electronics 10, no. 22 (2021): 2741. http://dx.doi.org/10.3390/electronics10222741.

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This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock

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14

Chatterjee, Basab, Surjadeep Sarkar, and Falguni Sinhababu. "Modification over Dithered DPLL to reduce the effect of narrowband channel interference." YMER Digital 21, no. 06 (2022): 383–91. http://dx.doi.org/10.37896/ymer21.06/37.

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Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and

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15

Deng, Xiaoying, Huazhang Li, and Mingcheng Zhu. "A Novel Fast-Locking ADPLL Based on Bisection Method." Electronics 10, no. 12 (2021): 1382. http://dx.doi.org/10.3390/electronics10121382.

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Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and hi

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16

Kim, Nam-Seog. "An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications." Sensors 24, no. 16 (2024): 5255. http://dx.doi.org/10.3390/s24165255.

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To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully integrated all-digital phase-locked loop (ADPLL)-based Gaussian frequency shift keying (GFSK) modulator incorporating two-point modulation (TPM). The modulator aims to enhance the efficiency of BLE communication in these networks. The design includes a time-to-digital converter (TDC) with the following three key features to improve linearity a

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17

Heo, Yoon, and Won-Young Lee. "An All-Digital Dual-Mode Clock and Data Recovery Circuit for Human Body Communication Systems." Electronics 13, no. 23 (2024): 4832. https://doi.org/10.3390/electronics13234832.

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This paper describes an all-digital clock and data recovery (CDR) circuit for implementing edge processing with a wireless body area network (WBAN). The CDR circuit performs delay-locked loop (DLL)-based and phase-locked loop (PLL)-based operations depending on the use of an external reference clock and is implemented using a digital method that is robust against external noise. The clock generator circuit shared by the two operation methods is described in detail, and the CDR circuit recovers 42 Mb/s input data and a 42 MHz clock, which are the specifications of human body communication (HBC)

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18

Kang, Byeongseok, Youngsik Kim, Hyunwoo Son, and Shinwoong Kim. "A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning." Electronics 13, no. 13 (2024): 2638. http://dx.doi.org/10.3390/electronics13132638.

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This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, d

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19

R., Dinesh, and Marimuthu Ramalatha. "An analysis of ADPLL applications in various fields." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 18, no. 2 (2020): 856–66. https://doi.org/10.11591/ijeecs.v18.i2.pp856-866.

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ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and dig

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20

Kim, Seojin, Youngsik Kim, Hyunwoo Son, and Shinwoong Kim. "A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations." Electronics 13, no. 18 (2024): 3598. http://dx.doi.org/10.3390/electronics13183598.

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This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this pr

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21

Butryn, Igor, Krzysztof Siwiec, and Witold Adam Pleskacz. "Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture." Electronics 10, no. 10 (2021): 1132. http://dx.doi.org/10.3390/electronics10101132.

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Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power t

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22

Macaitis, Vytautas, and Romualdas Navickas. "Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems." Electronics 8, no. 1 (2019): 72. http://dx.doi.org/10.3390/electronics8010072.

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This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The

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23

Elrabaa, Muhammad E. S. "A portable high-frequency digitally controlled oscillator (DCO)." Integration 47, no. 3 (2014): 339–46. http://dx.doi.org/10.1016/j.vlsi.2013.10.009.

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Saad, Sehmi, Mongia Mhiri, Aymen Ben Hammadi, and Kamel Besbes. "A 5-mW, 1.2–3.5-GHz Capacitive Degeneration in LC-Digitally-Controlled Oscillator for Nano-Satellite Frequency Synthesizers in 90-nm CMOS." Journal of Circuits, Systems and Computers 25, no. 12 (2016): 1650159. http://dx.doi.org/10.1142/s0218126616501590.

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This paper proposes an 8-bit LC tuned digitally-controlled oscillator (DCO) that exploits a new tunable active inductor (TAI) with a high [Formula: see text]-factor. This TAI achieves a maximum [Formula: see text]-factor value of 98 over a frequency range of 1770[Formula: see text]MHz. It tunes from 3.55[Formula: see text]nH to 15.2[Formula: see text]nH. The proposed TAI is used in the resonator of a wide tunable low-phase-noise DCO-LC oscillator. The tuning circuitry of the DCO with an additional resistance contributes to better effective capacitance characteristics as compared to the basic t

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Jurgo, Marijan, та Romualdas Navickas. "Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS". Journal of Electrical Engineering 67, № 2 (2016): 143–48. http://dx.doi.org/10.1515/jee-2016-0020.

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Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Struc

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Huang, Cheng, Zixuan Wang, Chao Chen, and Jianhui Wu. "A Review of LC-Based Digitally Controlled Oscillator with High Frequency Resolution." Journal of Circuits, Systems and Computers 24, no. 05 (2015): 1530002. http://dx.doi.org/10.1142/s0218126615300020.

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In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds

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27

Rahman, Mohammad Anisur, Habibah Mohamed, Mamun Ibne Reaz, Sawal Hamid Md Ali, and Wan Mimi Diyana Wan Zaki. "Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)." International Journal on Electrical Engineering and Informatics 6, no. 2 (2014): 297–305. http://dx.doi.org/10.15676/ijeei.2014.6.2.6.

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Wang, Zixuan, Hongyang Wu, Xin Wang, et al. "A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique." Electronics 8, no. 11 (2019): 1336. http://dx.doi.org/10.3390/electronics8111336.

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This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the nu

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29

Kim, Min-Su, and Sang-Sun Yoo. "Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System." Applied Sciences 11, no. 3 (2021): 1059. http://dx.doi.org/10.3390/app11031059.

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This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a

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Ma, Lei, Na Yan, Sizheng Chen, Yangzi Liu, and Hao Min. "A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO." Wireless Communications and Mobile Computing 2018 (2018): 1–8. http://dx.doi.org/10.1155/2018/4968391.

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This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V volt

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Dwivedi, Dileep, and Manoj Kumar. "Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning." Analog Integrated Circuits and Signal Processing 100, no. 3 (2019): 613–20. http://dx.doi.org/10.1007/s10470-019-01506-x.

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Chan, Cheong F., and Oliver Choy. "A low power digital controlled oscillator." International Journal of Electronics 88, no. 4 (2001): 463–66. http://dx.doi.org/10.1080/00207210110037268.

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Donzellini, G., D. D. Caviglia, G. Parodi, D. Ponta, and P. Repetto. "A digital controlled oscillator based on controlled phase shifting." IEEE Transactions on Circuits and Systems 36, no. 8 (1989): 1101–5. http://dx.doi.org/10.1109/31.192420.

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Yoo, Sang-Sun, and Kang-Yoon Lee. "Design of 0.68-mW LC-based Digitally Controlled Oscillator (DCO) for Bluetooth Low Energy (BLE) Transceiver." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17, no. 5 (2017): 611–20. http://dx.doi.org/10.5573/jsts.2017.17.5.611.

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35

Staszewski, R. B., D. Leipold, K. Muhammad, and P. T. Balsara. "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 50, no. 11 (2003): 815–28. http://dx.doi.org/10.1109/tcsii.2003.819128.

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Reddy, Gujjula Ramana, Chitra Perumal, Prakash Kodali, and Bodapati Venkata Rajanna. "Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 78. http://dx.doi.org/10.11591/ijres.v12.i1.pp78-86.

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The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (P

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Ramana, Reddy Gujjula, Perumal Chitra, Kodali Prakash, and Venkata Rajanna Bodapati. "Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 78–86. https://doi.org/10.11591/ijres.v12.i1.pp78-86.

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The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (P

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Boutahiri, Abdelali El, Mounir Ouremchi, Ahmed Rahali, et al. "Design of 2MHz OOK transmitter/receiver for inductive power and data transmission for biomedical implant." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (2019): 2779. http://dx.doi.org/10.11591/ijece.v9i4.pp2779-2787.

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<p>In this work a 2 MHz on-off keying (OOK) transmitter/receiver for inductive power and data transmission for biomedical implant system is presented. Inductive link, driven by a Class E power amplifier (PA) is the most PA used to transfer data and power to the internal part of biomedical implant system. Proposed transmitter consists of a digital control oscillator (DCO) and a class E PA which uses OOK modulation to transfer both data and power to a biomedical implant. In proposing OOK transmitter when the transmitter sends binary value “0” the DCO and PA are turned off. With this archit

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39

Abdelali, El Boutahiri, Ouremchi Mounir, Rahali Ahmed, et al. "Design of 2MHz OOK transmitter/receiver for inductive power and data transmission for biomedical implant." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (2019): 2779–87. https://doi.org/10.11591/ijece.v9i4.pp2779-2787.

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In this work a 2 MHz on-off keying (OOK) transmitter/receiver for inductive power and data transmission for biomedical implant system is presented. Inductive link, driven by a Class E power amplifier (PA) is the most PA used to transfer data and power to the internal part of biomedical implant system. Proposed transmitter consists of a digital control oscillator (DCO) and a class E PA which uses OOK modulation to transfer both data and power to a biomedical implant. In proposing OOK transmitter when the transmitter sends binary value “0” the DCO and PA are turned off. With this arc

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40

Zhang, Chaozhu, Jinan Han, and Ke Li. "Design and Implementation of Hybrid CORDIC Algorithm Based on Phase Rotation Estimation for NCO." Scientific World Journal 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/897381.

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The numerical controlled oscillator has wide application in radar, digital receiver, and software radio system. Firstly, this paper introduces the traditional CORDIC algorithm. Then in order to improve computing speed and save resources, this paper proposes a kind of hybrid CORDIC algorithm based on phase rotation estimation applied in numerical controlled oscillator (NCO). Through estimating the direction of part phase rotation, the algorithm reduces part phase rotation and add-subtract unit, so that it decreases delay. Furthermore, the paper simulates and implements the numerical controlled

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Wu, Xiu Long, Fa Niu Wang, Zhi Ting Lin, and Jun Ning Chen. "A Digitally Controlled Oscillator for ADPLL Application." Applied Mechanics and Materials 229-231 (November 2012): 1515–18. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1515.

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In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication. This new type of oscillator uses MOS varactor arrays to moderating the output frequency, through the using of digitally Sigma-Delta technology, we can get more precise resolution , and through using three modes progressively working way can make this kind of structure easily implement in process.

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Koo, Jabeom, Kannan Sankaragomathi, Richard Ruby, and Brian Otis. "A ± 1.55ppm Stable FBAR Reference Clock with Oven-Controlled Temperature Compensation." Journal of Electrical and Computer Engineering 2018 (July 2, 2018): 1–8. http://dx.doi.org/10.1155/2018/5453432.

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We present an oven-controlled FBAR oscillator that achieves a frequency stability of +/-1.55ppm from -5°C to 85°C. The highly integrated system includes a 0.64mm2 FBAR chip with integrated heater and sensor resistors and a 3 mm2 CMOS chip with the control electronics. The oscillator achieves an Allen deviation of 4ppb enabled by a temperature-to-digital converter (TDC) with a 150uK resolution. It corresponds to a 1.68JK2 FOM. The heater consumes a power of 14mW at -5°C and the oscillator consumes only 0.25mW. The ovenized oscillator meets the stringent frequency stability requirements (2 ppm)

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Lai, Wen-Cheng. "Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing." Sensors 22, no. 7 (2022): 2570. http://dx.doi.org/10.3390/s22072570.

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5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not onl

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Gujjula, Ramana Reddy, Chitra Perumal, Prakash Kodali, and Bodapati Venkata Rajanna. "Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4935. http://dx.doi.org/10.11591/ijece.v12i5.pp4935-4943.

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In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values

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Noer Soedjarwanto, Anang Budikarso, Kukuh Setyadjit, et al. "RANCANG BANGUN SPREAD SPECTRUM DENGAN METODE SINKRONISASI SERIAL CORRELATOR BERBASIS FPGA." Jurnal Teknik Ilmu Dan Aplikasi 3, no. 2 (2022): 8–11. http://dx.doi.org/10.33795/jtia.v1i1.92.

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Makalah ini menitik-beratkan pada pembuatan sistem sinkronisasi pada teknik pentransmisian spread spectrum asinkron. Dalam merealisasikan modul digunakan Field Programmable Gate Array ( FPGA ) Spartan II XC2S100-5 tq 144 yang terintegrasi pada Board XSA 100, implementasinya digunakan board XSA 100 dan software Xilinx ISE 6.1i. Modul terhubung secara wireline dan dirancang seperti terhubung secara wireless dimana pengaruh delay transmisi sangat besar pada proses tersebut. Dalam perancangan dan implementasi modul ini digunakan sistem Direct Sequence Spread Spectrum dan kode acak semu (pseudorand

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Huang, Hong-Yi, and Jen-Chieh Liu. "All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator." Analog Integrated Circuits and Signal Processing 68, no. 3 (2011): 245–55. http://dx.doi.org/10.1007/s10470-011-9654-1.

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Xu, Jian, Ting Lin, and Zhi Yin Gan. "A Low Noise and Computer Controllable Oscillator for CPT Atomic Clock." Applied Mechanics and Materials 433-435 (October 2013): 1423–26. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1423.

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This paper presents an digital microwave oscillator which employs a phase lock loop (PLL) chip and a direct digital synthesizer (DDS) chips to realize a pure frequency at 3.417GHz (half of the 87Rb atom ground-state hyperfine transition frequency) for the coherent population trapping (CPT) atomic clock application. And at this frequency, the oscillator demonstrates low noise (lower than-50dBc/Hz@100Hz and lower than-55dBc/Hz@1kHz) and purity. Moreover, based on the communication between a computer and the MCU, this oscillator could be completely controlled by self-developed user interface.

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Ramana, Reddy Gujjula, Perumal Chitra, Kodali Prakash, and Venkata Rajanna Bodapati. "Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4935–43. https://doi.org/10.11591/ijece.v12i5.pp4935-4943.

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Abstract:

In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital converter (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding

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Seo, Seong-Young, Jung-Hoon Chun, Young-Hyun Jun, and Kee-Won Kwon. "An all-digital PLL with supply insensitive digitally controlled oscillator." IEICE Electronics Express 10, no. 5 (2013): 20120902. http://dx.doi.org/10.1587/elex.10.20120902.

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Kang, Jin-Gyu, Jeongpyo Park, Min-Gyu Jeong, and Changsik Yoo. "Digital Low-Dropout Regulator With Voltage-Controlled Oscillator Based Control." IEEE Transactions on Power Electronics 37, no. 6 (2022): 6951–61. http://dx.doi.org/10.1109/tpel.2021.3138648.

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