Academic literature on the topic 'Digital down converter (DDC)'

<p>In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.</p><p> The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.</p><p>This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.</p><br><p>I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.</p><p>Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.</p><p>Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.</p>

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.

Recent developments in the field of phased array feeds for radio astronomical reflector antennas, have opened a new frontier for array signal processing for radio astronomy observations. The goal is to replace single horn feeds with a phased array feed, so as to enable astronomers to cover more sky area in less time. The development of digital backend signal processing systems has been a major area of concentration for the development of science-ready phased array feeds for radio astronomers. This thesis focuses on the development of analog down-converter receivers and an FPGA-based digital backend for real-time data processing and analysis support for phased array feeds. Experiments were conducted with new receiver boards and both single-polarization and dual-polarization phased array feeds at the Arecibo Observatory, Puerto Rico and at the 20-meter telescope at Green Bank, WV, and results were analyzed. The experiments were performed as a part of a feasibility study for phased array feeds. The new receiver boards were developed as an upgrade to the earlier connectorized receivers as the number of input channels increased from 19 to 38 and space constraints arose due to the large size of the earlier receivers. Each receiver card has four independent channels on it. The receiver cards were found to have lower cross-coupling between the channels in comparison to the earlier receivers. The development of a FPGA-based real time digital backend focused on a real-time spectrometer, beamformer and a correlator for all the 64-channels using a x64 ADC card and ROACH FPGA boards. The backend can plot results in real time and can stream and store the data on the computers for purpose of post-processing and data analysis. The design process uses libraries and blocks provided by the Center for Astronomy Signal Processing and Electronics Research (CASPER) community.

<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p><br>Report code: LiU-Tek-Lic-2005:68.

This diploma thesis is focused on complete construction of lab source which is controlled and powered by USB in personal computer. Different types of possible solutions are mentioned and finally one of them has been picked up as a best choice, which is developed in the rest of this thesis. Besides hardware construction there is also shown creation of main program for PIC18F14K50 microcontroller and main application that provides controlling of USB source via personal computer.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California<br>This paper presents a practical implementation of a hardware design for transmission of data over aircraft power lines. The intent of such hardware is to significantly reduce the wiring in the aircraft instrumentation system. The potential usages of this technology include pulse code modulation (PCM), Ethernet and other forms data communications. Details of the fieldprogrammable gate array (FPGA) and printed circuit board (PCB) designs of the digital and analog front end will be discussed. The power line is not designed for data transmission. It contains considerable noise, multipath effects, and time varying impedance. Spectral analysis data of an aircraft is presented to indicate the difficulty of the problem at hand. A robust modulation is required to overcome the harsh environment and to provide reliable transmission. Orthogonal frequency division multiplexing (OFDM) has been used in power line communication industry with a great deal of success. OFDM has been deemed the most appropriate technology for high-speed data transmission on aircraft power lines. Additionally, forward error correction (FEC) techniques are discussed.

Down converter is a mixer which have a three ports. Two ports are refered as input ports and one port is ouput. One input port is connected to a signal which is transmited by meteorological satellites at frequency 1,7 GHz this frequency falls within the L–band. Meteorogical images are trasmited in L-band. The second input port is connected to a local oscillator in this case voltage control oscillator. The output signal includes sum and differential products, for down conversion is logically used differential product. Down conversion is used to convert data that are transmitted at high frequency to lower frequency which can be futher processed and then displayed data on the end device.

碩士<br>國立臺灣大學<br>電信工程學研究所<br>91<br>Orthogonal frequency division multiplex (OFDM) becomes one of the promising techniques because it can efficiently combat multipath propagation and provide high-rate data transmission. And many Standards, such as IEEE802.11a, DVB etc., have adopted the attractive technique. Intrinsically, OFDM signals are sensitive to subtle changes in phase and magnitude. Any wireless transceiver front-end impairment may lead to system performance degradation. In this thesis, we set up an OFDM link in Matlab Simulink to analyze the front-end requirement. First, we focus on relationship of digital clipping and transmit symbol wordlength. Second, we study the non-ideal front-end effects, such as amplifier nonlinearity, oscillator phase noise and IQ-imbalance. On the other hand, we utilize Filter-bank theory and multirate signal processing skills to investigate digital IF receiver architecture based on OFDM system. We propose both “CP-saving” and “windowing” Digital-Down Converter (DDC) architecture and suggest a DDC FIR filter design method to improve system performance. Finally, we complete a 4-IF DDC architecture RTL design by using VHDL.