Relevant bibliographies by topics / Digital down converter (DDC)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Digital down converter (DDC)'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Digital down converter (DDC)"

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Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (August 5, 2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.

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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.
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Cui, Shu Lin, and Xu Li. "FPGA-Based Design of Resource-Efficient Digital down Converter." Applied Mechanics and Materials 128-129 (October 2011): 878–81. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.878.

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Digital down converter (DDC) is based on the theory of Software Defined Radio (SDR) and multirate signal processing, extensively applied in digital receivers of communications systems. An improved resource-efficient DDC with polyphase architecture and distributed arithmetic (DA) is presented in this paper. The design based on Xilinx FPGA Virtex-5 has more flexible characters and higher precision computation with less resource consumption.
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Traykov, Metodi, Radoslav Mavrevski, and Ivan Trenchev. "Modeling of digital converter for GSM signals with MATLAB." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (October 1, 2019): 4417. http://dx.doi.org/10.11591/ijece.v9i5.pp4417-4422.

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In this study will simulate steady state of Digital Down Convertor (DDC) for GSM signal with a narrow frequency range. The MATLAB model that is described in this article simulates the work of the TIGC4016 Quad Digital Down Converter. This converter is used for digital mixing (down conversion) of signals, narrow band low-pass filtering and decimation. To implementation of the model, we use high sample-rate (69,333 MSPS) bandpass signal. The result contains low sample-rate (270.83 KSPS) baseband signal, thus facilitating the demodulation process.
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Telagathoti, Pitchaiah, Moparthi Aparna, and P. V. Sridevi. "Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver." International Journal of Engineering & Technology 7, no. 2-1 (March 23, 2018): 421. http://dx.doi.org/10.14419/ijet.v7i2.9242.

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Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.
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Jeong, Kil-Hyun. "The Implementation of DDC for the WLAN Receiver." Journal of the Korea Society of Computer and Information 17, no. 2 (February 29, 2012): 113–18. http://dx.doi.org/10.9708/jksci.2012.17.2.113.

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Wang, Wen Bin, Dao Yuan Liu, and Yu Qin Yao. "Research and Design of Digital down Converter Based on Software Defined Radio." Applied Mechanics and Materials 513-517 (February 2014): 1803–6. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.1803.

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This paper makes a brief introduction on the current development trend of software radio and digital down converter status. The basic theoretical knowledge: Band-pass sampling theorem, digital signal orthogonal transformation theory, multi-rate signal processing theory. Based on these theories, use MATLAB complete the design and verification of mixing module, the extraction module (CIC filter, half-band filter and FIR filters), finally verify the correctness of the design, and implement DDC.
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Xu, Ping, Wei Xia, and Zi Shu He. "A Design of VB-DDC Using DA-Based Systolic FIR Filter." Applied Mechanics and Materials 130-134 (October 2011): 3950–53. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.3950.

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In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.
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Sahukar, Latha, and Dr M. Madhavi Latha. "Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 88. http://dx.doi.org/10.14419/ijet.v7i2.16.11422.

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This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time occupies only 10% of the slices of FPGA.
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Deng, Jun, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, and Lun Cai Liu. "Design of a SoC With High-Speed DDC for Software Radio Receiver." Advanced Materials Research 605-607 (December 2012): 1875–79. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1875.

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This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.
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Abbas, Ghulam, Jason Gu, Umar Farooq, Muhammad Abid, Ali Raza, Muhammad Asad, Valentina Balas, and Marius Balas. "Optimized Digital Controllers for Switching-Mode DC-DC Step-Down Converter." Electronics 7, no. 12 (December 8, 2018): 412. http://dx.doi.org/10.3390/electronics7120412.

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In this paper, a nonlinear least squares optimization method is employed to optimize the performance of pole-zero-cancellation (PZC)-based digital controllers applied to a switching converter. An extensively used step-down converter operating at 1000 kHz is considered as a plant. In the PZC technique, the adverse effect of the (unwanted) poles of the buck converter power stage is diminished by the complex or real zeros of the compensator. Various combinations of the placement of the compensator zeros and poles can be considered. The compensator zeros and poles are nominally/roughly placed while attempting to cancel the converter poles. Although PZC techniques exhibit satisfactory performance to some extent, there is still room for improvement of the controller performance by readjusting its poles and zeros. The (nominal) digital controller coefficients thus obtained through PZC techniques are retuned intelligently through a nonlinear least squares (NLS) method using the Levenberg-Marquardt (LM) algorithm to ameliorate the static and dynamic performance while minimizing the sum of squares of the error in a quicker way. Effects of nonlinear components such as delay, ADC/DAC quantization error, and so forth contained in the digital control loop on performance and loop stability are also investigated. In order to validate the effectiveness of the optimized PZC techniques and show their supremacy over the traditional PZC techniques and the ones optimized by genetic algorithms (GAs), simulation results based on a MATLAB/Simulink environment are provided. For experimental validation, rapid hardware-in-the-loop (HiL) implementation of the compensated buck converter system is also performed.
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Dissertations / Theses on the topic "Digital down converter (DDC)"

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Ohlsson, Henrik. "Studies on Design and Implementation of Low-Complexity Digital Filters." Doctoral thesis, Linköping : Dept. of Electrical Engineering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/49/index.html.

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Krantz, Emil. "Design of a Digital Down Converter for LTE in an FPGA." Thesis, University of Gävle, Faculty of Engineering and Sustainable Development, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-6879.

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In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.

 The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.

This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.


I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.

Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.

Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.

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Girija, Satyanarayana, and J. Girija. "PC- Based S-Band Down Converter / FM Telemetry Receivers." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611444.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California
In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.
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Asthana, Vikas. "Development of L-Band Down Converter Boards and Real-Time Digital Backend for Phased Array Feeds." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3162.

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Recent developments in the field of phased array feeds for radio astronomical reflector antennas, have opened a new frontier for array signal processing for radio astronomy observations. The goal is to replace single horn feeds with a phased array feed, so as to enable astronomers to cover more sky area in less time. The development of digital backend signal processing systems has been a major area of concentration for the development of science-ready phased array feeds for radio astronomers. This thesis focuses on the development of analog down-converter receivers and an FPGA-based digital backend for real-time data processing and analysis support for phased array feeds. Experiments were conducted with new receiver boards and both single-polarization and dual-polarization phased array feeds at the Arecibo Observatory, Puerto Rico and at the 20-meter telescope at Green Bank, WV, and results were analyzed. The experiments were performed as a part of a feasibility study for phased array feeds. The new receiver boards were developed as an upgrade to the earlier connectorized receivers as the number of input channels increased from 19 to 38 and space constraints arose due to the large size of the earlier receivers. Each receiver card has four independent channels on it. The receiver cards were found to have lower cross-coupling between the channels in comparison to the earlier receivers. The development of a FPGA-based real time digital backend focused on a real-time spectrometer, beamformer and a correlator for all the 64-channels using a x64 ADC card and ROACH FPGA boards. The backend can plot results in real time and can stream and store the data on the computers for purpose of post-processing and data analysis. The design process uses libraries and blocks provided by the Center for Astronomy Signal Processing and Electronics Research (CASPER) community.
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Billman, Steven John. "Design of a Low Power and Area Efficient Digital Down Converter and SINC Filter in CMOS 90-nm Technology." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1307746437.

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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.

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High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.

To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.

The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.

The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.

A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.


Report code: LiU-Tek-Lic-2005:68.
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Pytela, Ondřej. "Řízený zdroj napětí a proudu připojitelný přes USB." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-220377.

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This diploma thesis is focused on complete construction of lab source which is controlled and powered by USB in personal computer. Different types of possible solutions are mentioned and finally one of them has been picked up as a best choice, which is developed in the rest of this thesis. Besides hardware construction there is also shown creation of main program for PIC18F14K50 microcontroller and main application that provides controlling of USB source via personal computer.
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Tian, Hai, Tom Trojak, and Charles H. Jones. "COMMUNICATIONS OVER AIRCRAFT POWER LINES: A PRACTICAL IMPLEMENTATION." International Foundation for Telemetering, 2006. http://hdl.handle.net/10150/603939.

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ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California
This paper presents a practical implementation of a hardware design for transmission of data over aircraft power lines. The intent of such hardware is to significantly reduce the wiring in the aircraft instrumentation system. The potential usages of this technology include pulse code modulation (PCM), Ethernet and other forms data communications. Details of the fieldprogrammable gate array (FPGA) and printed circuit board (PCB) designs of the digital and analog front end will be discussed. The power line is not designed for data transmission. It contains considerable noise, multipath effects, and time varying impedance. Spectral analysis data of an aircraft is presented to indicate the difficulty of the problem at hand. A robust modulation is required to overcome the harsh environment and to provide reliable transmission. Orthogonal frequency division multiplexing (OFDM) has been used in power line communication industry with a great deal of success. OFDM has been deemed the most appropriate technology for high-speed data transmission on aircraft power lines. Additionally, forward error correction (FEC) techniques are discussed.
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Bürger, David. "Konvertor pro příjem digitálních družicových snímků v pásmu L." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316413.

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Down converter is a mixer which have a three ports. Two ports are refered as input ports and one port is ouput. One input port is connected to a signal which is transmited by meteorological satellites at frequency 1,7 GHz this frequency falls within the L–band. Meteorogical images are trasmited in L-band. The second input port is connected to a local oscillator in this case voltage control oscillator. The output signal includes sum and differential products, for down conversion is logically used differential product. Down conversion is used to convert data that are transmitted at high frequency to lower frequency which can be futher processed and then displayed data on the end device.
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Chang, Cheng-Chun, and 張正春. "DESIGN A DIGITAL-DOWN CONVERTER FOR OFDM SYSTEM." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/77588275305061140081.

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碩士
國立臺灣大學
電信工程學研究所
91
Orthogonal frequency division multiplex (OFDM) becomes one of the promising techniques because it can efficiently combat multipath propagation and provide high-rate data transmission. And many Standards, such as IEEE802.11a, DVB etc., have adopted the attractive technique. Intrinsically, OFDM signals are sensitive to subtle changes in phase and magnitude. Any wireless transceiver front-end impairment may lead to system performance degradation. In this thesis, we set up an OFDM link in Matlab Simulink to analyze the front-end requirement. First, we focus on relationship of digital clipping and transmit symbol wordlength. Second, we study the non-ideal front-end effects, such as amplifier nonlinearity, oscillator phase noise and IQ-imbalance. On the other hand, we utilize Filter-bank theory and multirate signal processing skills to investigate digital IF receiver architecture based on OFDM system. We propose both “CP-saving” and “windowing” Digital-Down Converter (DDC) architecture and suggest a DDC FIR filter design method to improve system performance. Finally, we complete a 4-IF DDC architecture RTL design by using VHDL.
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Book chapters on the topic "Digital down converter (DDC)"

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Chang, Henry, Edoardo Charbon, Umakanta Choudhury, Alper Demir, Eric Felt, Edward Liu, Enrico Malavasi, Alberto Sangiovanni-Vincentelli, and Iasson Vassiliou. "Σ-Δ Analog-To-Digital Converter Design Example." In A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, 247–87. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8752-5_10.

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Chang, Henry, Edoardo Charbon, Umakanta Choudhury, Alper Demir, Eric Felt, Edward Liu, Enrico Malavasi, Alberto Sangiovanni-Vincentelli, and Iasson Vassiliou. "Current Source Digital-To-Analog Converter Design Example." In A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, 223–45. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8752-5_9.

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Jun-min, Kang. "Research and Implementation for Quadrature Digital Down Converter of Low Intermediate Frequency Signal Based on FPGA." In Advances in Intelligent Systems and Computing, 693–705. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-38789-5_76.

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Onabajo, Marvin, Yong-Bin Kim, Yongsuk Choi, Hari Chauhan, Chun-hsiang Chang, and In-Seok Jung. "Digitally Assisted Performance Tuning of Analog/RF Circuits with an On-Chip FFT Engine." In Advances in Computer and Electrical Engineering, 236–67. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch010.

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A serious drawback associated with systems-on-a-chip integration and CMOS technology scaling trends is the increasing susceptibility to manufacturing process variations and aging effects. Consequently, it is critical to improve on-chip measurement and self-calibration capabilities as well as the testability of single-chip systems. This chapter describes a robust design methodology for enhanced reliability of analog front-end circuits in mixed-signal chips. The system under development is comprised of small blocks close to high-frequency analog circuits under test to down-convert signals to low frequencies such that they can be routed to an on-chip analog-to-digital converter architecture for built-in testing applications. An efficient Fast Fourier Transform (FFT) engine is used to calculate the frequency spectrum of the signal with significantly less chip area compared to existing FFT engines. The self-contained system provides the measurement results in digital form to support digital calibration approaches, particularly those that involve digitally assisted analog blocks.
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Conference papers on the topic "Digital down converter (DDC)"

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Pavlenko, Mykola, and Alexander Kalyuzhny. "Analysis of quantization noises in multistage signal processing systems: A case study of digital down converters (DDC)." In 2017 IEEE First Ukraine Conference on Electrical and Computer Engineering (UKRCON). IEEE, 2017. http://dx.doi.org/10.1109/ukrcon.2017.8100360.

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Luo, Feng, and Dongsheng Ma. "Integrated adaptive step-up/down switching DCDC converter with tri-band tri-mode digital control for dynamic voltage scaling." In 2008 IEEE International Symposium on Industrial Electronics (ISIE 2008). IEEE, 2008. http://dx.doi.org/10.1109/isie.2008.4677168.

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Gerhardt, Joe, and Saiyu Ren. "Digital Down Converter optimization." In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2013. http://dx.doi.org/10.1109/mwscas.2013.6674824.

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Petrowski, M., D. B. Chester, and W. R. Young. "Single chip digital down converter architecture." In Proceedings of ICASSP '93. IEEE, 1993. http://dx.doi.org/10.1109/icassp.1993.319127.

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MalmirChegini, M., Hamed Haghshenas, and F. Marvasti. "A novel iterative digital down converter." In 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications. IEEE, 2007. http://dx.doi.org/10.1109/ictmicc.2007.4448677.

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Liyun, Bai, and Wen Biyang. "Digital Down Converter Based on Walsh Transform for Digital Receiver." In Chengdu, China. IEEE, 2007. http://dx.doi.org/10.1109/iwsda.2007.4408362.

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Datta, Debarshi, Partha Mitra, and Himadri Sekhar Dutta. "FPGA-Based Digital Down Converter for GSM Application." In 2020 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2020. http://dx.doi.org/10.1109/vlsidcs47293.2020.9179939.

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Xu, Xiaoxiao, Xianzhong Xie, and Fei Wang. "Digital Up and Down Converter in IEEE 802.16d." In 2006 8th international Conference on Signal Processing. IEEE, 2006. http://dx.doi.org/10.1109/icosp.2006.344450.

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Yu, Qian, and Bao-Yong Chi. "A programmable digital down-converter for SDR receivers." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6467915.

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Curticapean, F., and J. Niittylahti. "An improved digital quadrature frequency down-converter architecture." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.987704.

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