Dissertations / Theses on the topic 'Digital down converter (DDC)'

<p>In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.</p><p> The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.</p><p>This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.</p><br><p>I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.</p><p>Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.</p><p>Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.</p>

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.

Recent developments in the field of phased array feeds for radio astronomical reflector antennas, have opened a new frontier for array signal processing for radio astronomy observations. The goal is to replace single horn feeds with a phased array feed, so as to enable astronomers to cover more sky area in less time. The development of digital backend signal processing systems has been a major area of concentration for the development of science-ready phased array feeds for radio astronomers. This thesis focuses on the development of analog down-converter receivers and an FPGA-based digital backend for real-time data processing and analysis support for phased array feeds. Experiments were conducted with new receiver boards and both single-polarization and dual-polarization phased array feeds at the Arecibo Observatory, Puerto Rico and at the 20-meter telescope at Green Bank, WV, and results were analyzed. The experiments were performed as a part of a feasibility study for phased array feeds. The new receiver boards were developed as an upgrade to the earlier connectorized receivers as the number of input channels increased from 19 to 38 and space constraints arose due to the large size of the earlier receivers. Each receiver card has four independent channels on it. The receiver cards were found to have lower cross-coupling between the channels in comparison to the earlier receivers. The development of a FPGA-based real time digital backend focused on a real-time spectrometer, beamformer and a correlator for all the 64-channels using a x64 ADC card and ROACH FPGA boards. The backend can plot results in real time and can stream and store the data on the computers for purpose of post-processing and data analysis. The design process uses libraries and blocks provided by the Center for Astronomy Signal Processing and Electronics Research (CASPER) community.

<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p><br>Report code: LiU-Tek-Lic-2005:68.

This diploma thesis is focused on complete construction of lab source which is controlled and powered by USB in personal computer. Different types of possible solutions are mentioned and finally one of them has been picked up as a best choice, which is developed in the rest of this thesis. Besides hardware construction there is also shown creation of main program for PIC18F14K50 microcontroller and main application that provides controlling of USB source via personal computer.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California<br>This paper presents a practical implementation of a hardware design for transmission of data over aircraft power lines. The intent of such hardware is to significantly reduce the wiring in the aircraft instrumentation system. The potential usages of this technology include pulse code modulation (PCM), Ethernet and other forms data communications. Details of the fieldprogrammable gate array (FPGA) and printed circuit board (PCB) designs of the digital and analog front end will be discussed. The power line is not designed for data transmission. It contains considerable noise, multipath effects, and time varying impedance. Spectral analysis data of an aircraft is presented to indicate the difficulty of the problem at hand. A robust modulation is required to overcome the harsh environment and to provide reliable transmission. Orthogonal frequency division multiplexing (OFDM) has been used in power line communication industry with a great deal of success. OFDM has been deemed the most appropriate technology for high-speed data transmission on aircraft power lines. Additionally, forward error correction (FEC) techniques are discussed.

Down converter is a mixer which have a three ports. Two ports are refered as input ports and one port is ouput. One input port is connected to a signal which is transmited by meteorological satellites at frequency 1,7 GHz this frequency falls within the L–band. Meteorogical images are trasmited in L-band. The second input port is connected to a local oscillator in this case voltage control oscillator. The output signal includes sum and differential products, for down conversion is logically used differential product. Down conversion is used to convert data that are transmitted at high frequency to lower frequency which can be futher processed and then displayed data on the end device.

碩士<br>國立臺灣大學<br>電信工程學研究所<br>91<br>Orthogonal frequency division multiplex (OFDM) becomes one of the promising techniques because it can efficiently combat multipath propagation and provide high-rate data transmission. And many Standards, such as IEEE802.11a, DVB etc., have adopted the attractive technique. Intrinsically, OFDM signals are sensitive to subtle changes in phase and magnitude. Any wireless transceiver front-end impairment may lead to system performance degradation. In this thesis, we set up an OFDM link in Matlab Simulink to analyze the front-end requirement. First, we focus on relationship of digital clipping and transmit symbol wordlength. Second, we study the non-ideal front-end effects, such as amplifier nonlinearity, oscillator phase noise and IQ-imbalance. On the other hand, we utilize Filter-bank theory and multirate signal processing skills to investigate digital IF receiver architecture based on OFDM system. We propose both “CP-saving” and “windowing” Digital-Down Converter (DDC) architecture and suggest a DDC FIR filter design method to improve system performance. Finally, we complete a 4-IF DDC architecture RTL design by using VHDL.

碩士<br>國立交通大學<br>工學院精密與自動化工程學程<br>103<br>Downconverters are radio receivers in satellite antenna systems and are indispensable components for satellite television reception. With the advance of communication technologies and the advent of digital era, satellite television systems must provide diversified services and high-quality images for the increasing user demands. This study investigated heat transfer and distribution in digital downconverters. Various mechanical materials were used to verify and improve the overheating problems of downconverter products. CFdesign thermal simulation software was used to calculate the temperature distribution in the downconverter. Additionally, product temperatures were physically measured using a thermostatic-humidistat testing machine. Finally, the simulated and experimentally measured temperatures were compared to complete the analysis. The results showed that using high-k (thermal conductivity) materials facilitated thermal conduction. Moreover, the temperature distribution from the CFdesign simulation and that from thermostatic-humidistat experiment yielded similar results, with errors of less than 4 °C. In summary, the CFdesign software was verified to be a feasible design aid for simulating temperature distributions during product development, thereby reducing the modifications and costs involved after molding a product and streamlining the development process.

碩士<br>國立暨南國際大學<br>電機工程學系<br>95<br>In this paper, we present a digital IF down converter architecture for a W-CDMA terminal based on the software defined radio. Digital IF down converter includes many elements. There are NCO, the CIC filter, and the FIR filter. First, the NCO is implemented in the method of LUT and it could have higher speed. Second, CIC filter is a flexible and multiplier-free filter suitable for hardware implementation. Third, the FIR filter is implemented in the method of Distributed Arithmetic Algorithm that can save area and increase handling speed. Finally, we adopt hardware description language Verilog HDL for RTL design and using ModelSim software to accomplish timing verification; therefore, we can logic synthesis and then complete digital IF down converter design.

碩士<br>國立中央大學<br>通訊工程研究所<br>93<br>Orthogonal frequency-division multiplexing (OFDM) is a favored technique in digital broad-band wireless communications due to its easiness to combat highly dispersive transmission. The feasible implementation of an OFDM receiver relies on fully digital technique. In this thesis, we discuss the issue regarding to the design of an efficient lowpass filter specifically for the digital down converter (DDC) in OFDM receivers with digital intermediate frequency (IF) input. The lowpass filter in the DDC possesses the function to suppress both the image band signal due to frequency mixing and the noise residing in aliasing bands resulted from decimation. The lowpass filter designed with a newly proposed criterion exhibits performance improvement comparing to those designed with traditional specification.

碩士<br>國立中央大學<br>電機工程研究所<br>85<br>In this thesis, a novel architecture of IF digital frequency down conversion process is presented. The architecture design is the coombination of IF oversampling technique and multistage interpolated finite impulse response (IEIR) filter design based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency of the whole system. It is also suitable for the digital IF signal processing with a higher IF frequency. A chip implementation of 2V low-powre IF digital frequency down converter (DFDC) based on this proposed architecture is also presented for the IS-95 CDMA digital forward ling receive. It accepts a 5-bits digitized IF frequency input signal and generates a pair of 12-bits in-phase and quadrature baseband signals. For further hardwarew simpli-fications, several methodologies are adopted to reduce the hardwarew complexity of FIR filters and mixers at architectural and circuit levels. This chip is fabricated with 0.6μm DPDM CMOS technology and contains approximately 3,1000 transistors in an area of 1800I1800?m2. The power dissipation of its core is simulated to be 1.5mW at 20 MHz clock rate.

碩士<br>國立中央大學<br>電機工程學系<br>86<br>In this thesis, an analog front-end for IF/baseband digital down conversion adopted current-mode techniques is presented. The analog front-end consists of a 6th order Chebyshev bandpass filter for the input 4.9152MHz IF signal, and a 5-bit 20MHz flash A/D converter for the IF analog signal digitizaion. Current mode techniques are employed in designing the whole analog part to obtain a good dynamic range and in low-voltage constraint. Besides, current mode technique is attractive due to its high speed and compatibility on standard CMOS digital technology. A 2V low-voltage low-power analog front-end circuitry has been designed for IF/baseband digital down converter based on the IS-95 CDMA communication system. It filters the input IF signal and generates digital bits for the following digital down conveter. The circuits are simulated and verified by HSPICE. This chip was fabricated in TSMC 0.6um SPDM CMOS digital technology. The core area of the analog part is 2200um X 500um. And the power dissipation of the core is simulated to be 34.7mW at 5MHz input signal and 20MHz clock from a single 2V supply voltage.

碩士<br>國立成功大學<br>電機工程學系<br>86<br>This thesis presents the design, implementation, and measurement of a L-band downconverter, VHF circuits, and related RFICs for a digital audio broadcasting (DAB) receiver RF front- end. A dual frequency conversion strategy is employed in this RF front-end (1.452-1.492 GHz). The 1st LO is at 1.28 GHz and the 1st IF is from 172 MHz to 212 MHz. The 2nd LO (for VHF tuner) is from 215 MHz to 255 MHz and the 2nd IF is 43 MHz. The L-band downconverter includes a single-stage low noise amplifier (9.7 dB gain and 1.65 noise figure) , a voltage control amplifier (50 dB turning range and 17 dB gain), a phase-locked oscillator (6 dBm output power and -95 dBc/Hz@ 10 kHz), and an active mixer (8 dB noise figure, 15 dB conversion gain and 15 dBm OIP3 ). The L-band downconverter with 43 MHz voltage control amplifier (70 dB turning range and 38 dB gain) are design and combined with suitable IF ICs and filters to form a DAB receiver RF front-end (not including the VHF frequency synthesizer). The DAB receiver RF front-end has 65 dB conversion gain, 5 dB noise figure and 19 dBm OIP3. In digital modulation measurements, a 384 kbps p/4-DQPSK signal is applied to the DAB receiver RF front-end and measured by a HP 89410A vector signal analyzer. The measured error vector magnitude (EVM) is 1.3% and adjacent channel power (ACP) is 43 dBc. For 1.6 Mbps 16-QAM digital modulation, the error vector magnitude is 2.6% and adjacent channel power is 38 dBc. This thesis also presents the design and measured performance of a DAB L- band LNA and mixer RFICs. For RFIC design, the equivalent circuits of RFIC/MMIC components are developed by using the HP- MDS RF/Microwave circuit CAD tool. The two-stage LNA RFIC has 18.2 dB gain, 3.2 dB noise figure and 18.4 dBm OIP3. The dual- gate mixer RFIC has 2 dB conversion loss, 20 dB LO-RF isolation and 9.4 dB OIP3.

碩士<br>國立成功大學<br>電機工程學系<br>89<br>This thesis presents the design and implementation of L-band DAB downconverter RFICs, including LNA/mixer/AGC and phase-locked oscillator (PLO), in a standard 0.35m CMOS technology. The RF is from 1.452 to 1.492 GHz, the LO is at 1.28 GHz and the IF is from 172 MHz to 212 MHz. The single-stage LNA has 3.2 dB noise figure and only 3dB gain. The single-balanced mixer has 20dB noise figure , 16dB conversion loss. Simulation results of the 1.28 GHz PLO show that the output power is —2 dBm and the locking time is 15s. An external hybrid-circuit LNA with 26 dB gain and 2.2 dB noise figure is added, due to the low gain result of the implemented LNA RFIC. The LNA and a 250 MHz IF lowpass filter with the LNA/mixer/AGC RFIC construct a hybrid/RFIC downconverter (not including the PLO RFIC) for receiving measurement. The hybrid/RFIC downconverter has 13dB gain, 3.5 dB noise figure, -17 dBm P1dB and —7.5 dBm OIP3. For 1.2Msps 32-QAM digital modulation, the measured error vector magnitude (EVM) is 1.2%. With a DAB test encorder and a DAB test receiver for OFDM signal receiving test, the adjacent channel power ratio (ACPR) is —30.61 dBc and the sensitivity is -90dBm (BER=10-4 ) or -97dBm (BER=10-2 ). Further effort will be devoted to design and implement a complete CMOS L-band DAB downconverter RFIC.

碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>99<br>In this thesis, we propose a novel Digital-Down-Converter (DDC) architecture for PC-based software Digital Video Broadcasting-Terrestrial (DVB-T) receiver. We let A/D sampling rate be 192/7 MHz and the order of the lowpass FIR filter be seven (8 coefficients) in DDC. We then propose combining the mixer and filter (CMF), that is, pre-processing the mixer and filter coefficients and storing the results in a look-up table. If the input data of length N, the proposed CMF scheme has 2N multiplications but the previous architecture, which does not pre-process the mixer and filter coefficients together in advance, has 3N multiplications. Finally, we optimize our algorithm in assembly code to satisfy DVB-T real-time reception requirement.

碩士<br>國立清華大學<br>電機工程學系<br>103<br>This thesis presents design and implementation of an isolated two-stage dc/dc converter with division-summation (D-Σ) digital control. The first stage is a buck converter, and the second stage is a full-bridge converter with current-doubler rectifier which is controlled with phase-shift switching method. Therefore, the primary-side power devices can achieve zero voltage switching. With D-Σ digital control, the converter is allowed to have wide inductance variation caused by high current flowing through inductor, and to track current reference precisely for achieving tight output voltage regulation. This paper derives D-Σ control law for dc/dc converter in detail, and initiates the application of D-Σ control in DCM operation. The major contributions of this paper is: this research applies D-Σ digital control on dc/dc converter unprecedentedly, and verify that the control can reduce steady-state error as compared with peak current-mode control and achieve faster dynamic response over average current-mode control. Moreover, it presents a modified D-Σ control law for DCM operation to enables the applicability of the control in both CCM and DCM operation. Last, the research implements a high voltage step-down dc/dc converter with input voltage 600 V, output voltage 26 V and power rating 2.6 kW.

碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>This thesis aims to design and achieve a non-isolated step-down DC-DC converter with non-linear voltage transfer ratio by digital-controlled. In the condition of high step-down conversion ratio and transformerless, classical buck converter needs very small duty. However, step-down DC-DC converter with non-linear conversion has larger duty than classical buck converter. It will raise the switch’s utilization and conversion efficiency. This thesis uses TMS320F28035 DSP chip for digital-controlled which is made by TI Inc. By using current loop and voltage loop, the thesis’s structure achieves the CC/CV multi charging scheme and to be applied in charge system. Initially, it analyzes the operating principle and derives the small signal in this thesis. Next, it introduces the digital-controlled system of this thesis’s structure. Then, it explains the design of the circuit element, parameter of digital-control and compensator. After all, it achieves a non-linear conversion DC-DC converter to be applied in charge system with 400 V input voltages, 48 V maximum output voltage and 600 W maximum output power.

碩士<br>國立交通大學<br>電信工程系<br>90<br>In this paper, an alternative approach for the design of an IEEE 802.11a standard digital IF up/down converter is presented. The signal up or down conversion are achieved by integrating half-band filter architecture with polyphase decomposition technique used in multi-rate signal processing. According to multi-rate system theory, while on the one hand, the signal sampling frequency can be increased four times by interpolation, on the other hand, the ADC output signal sampling frequency can be decreased four times by decimation. At the same time, we apply the theory of time shift and frequency shift to realize the conversion between baseband and low IF. This paper also addresses efficient implementation of the up/down converter architecture. By means of an unconventional number representation and high-rate compressor, the power consumption and the complexity of circuits can be decreased significantly. Furthermore, applying the interleaving method to simplify the structure, better resource sharing can be achieved and accordingly the implementation cost can be reduced.

Die vorliegende Arbeit beschreibt die Analyse und den Entwurf eines vollintegrierten Empfängers im UHF-Bereich mit dem Ziel, für die Verwendung im Mobilfunkstandard der vierten Generation geeignet zu sein, aber auch eine Einschätzung bezüglich der Anwendbarkeit eines solchen Empfängers für Geräte der fünften Generation vorzunehmen. Bei dem Empfängerkonzept handelt es sich um einen direkt digitalisierenden Empfänger, d.h. das Empfangssignal wird direkt mittels Analog-Digital-Umsetzer digitalisiert und vorher nicht auf eine niedrigere Trägerfrequenz abwärtsgemischt. Der Analogteil eines direkt digitalisierenden Empfängers besteht also nur aus einem LNA und einem ADU. Diese Empfängertopologie stellt hohe Anforderungen an den ADU und bildet deshalb den Fokus dieser Arbeit. Für die Untersuchungen des Empfängerkonzepts wurde sich auf eine Implementierung für niedrige Mobilfunkfrequenzbänder beschränkt, weshalb für den Entwurf festgelegt wurde, eine Trägerfrequenz von 750MHz mit einer Signalbandbreite von 20MHz empfangen und verarbeiten zu können. Der Entwurf erfolgte in einer 28nm CMOS Technologie, sollte flächen- und stromsparend sein, sich aber auch für zukünftige Technologieknoten mit noch höherer Integrationsdichte eignen, ohne die analogen Schaltblöcke gesondert bei der Technologiewahl berücksichtigen zu müssen. Somit konnten integrierte Spulen in der Empfängerkette nicht verwendet werden. Zugleich muss im Empfänger der Alias-Effekt unterdrückt werden. Um diese strengen Rahmenbedingungen ohne exorbitante Stromaufnahme zu erfüllen, kommt als ADU-Topologie nur ein zeitkontinuierlicher Sigma-Delta-Modulator in Frage. Dazu musste das Schleifenfilter des Sigma-Delta-Modulators komplett neu entworfen werden, was u.a. den Entwurf einer einstellbaren hochgütigen aktiven Spule erforderte. Das Empfängerkonzept konnte erfolgreich an der gefertigten Schaltung verifiziert werden, der gemessene dynamische Bereich blieb jedoch weit hinter dem ursprünglich anvisierten Ziel von 84dB zurück. Es konnte lediglich ein dynamischer Bereich von 59dB bei einer Leistungsaufnahme von 36,4mW und einer maximalen Auflösung von 4,5 Bit erreicht werden. Nachfolgende Untersuchungen des Konzepts zeigen aber Lösungsansätze auf, mit denen die Auflösung auf 8,7 Bit und der Dynamikbereich auf 69dB gesteigert werden kann.

Fixed Broadband Wireless Access (FBWA) is a technology aimed at providing high-speed wireless Internet access, over a wide area, from devices such as personal computers and laptops. FBWA channels are defined in the range of 1-20 MHz which makes the RF front end (RFE) design extremely challenging. In its pursuit to standardize the Broadband Wireless Access (BWA) technologies, IEEE working group 802.16 for Broadband Wireless Access has released the fixed BWA standard IEEE 802.16 – 2004 in 2004. This standard is further backed by a consortium, of leading wireless vendors, chip manufacturers and service providers, officially known as Wireless Interoperability for Microwave Access (WiMAX). In general, any wireless base station (BS), supporting a number of contiguous Frequency Division Multiplexed (FDM) channels has to incorporate an RF front end (RFE) for each RF channel. The precise job of the RFE is to filter the desired channel from a group of RF channels, digitize it and present it to the subsequent baseband system at the proper sampling rate. The system essentially has a bandpass filter (BPF) tuned to the channel of interest followed by a multiplier which brings the channel to a suitable intermediate frequency (IF). The IF output is digitized by an ADC and then brought to the baseband by an appropriate digital multiplier. The baseband samples, thus generated, are at the ADC sampling rate which is significantly higher than the target sampling rate, which is defined by the wireless protocol in use. As a result a sampling rate conversion (SRC) is performed on these baseband samples to bring the channel back to the target sampling rate. Since the input sampling rate need not be an integer multiple of the target sampling rate, Fractional SRC (FSRC) is required in most of the cases. Instead of using a separate ADC and IF section for each individual channels, most systems use a common IF section, followed by a wideband ADC, which operates over a wide frequency band containing a group of contiguous FDM channels. In this case a channelizer is employed to digitally extract the individual channels from the digital IF samples. We formally call this system a receiver channelizer. Such an implementation presents considerable challenge in terms of the computational requirement and of course the cost of the BS. The computational complexity further goes up for FBWA system where channel bandwidth is in the order of several MHz. Though such a system has been analyzed for narrow band wireless systems like GSM, to the best of our knowledge no analysis seems to have been carried out for a wideband system such as WiMAX. In this work, we focus on design of a receiver channelizer for WiMAX BS, which can simultaneously extract a group of contiguous FDM RF channels supported by the BS. The main goal is to obtain a simple, low cost channelizer architecture, which can be implemented in an FPGA. There are a number of techniques available in the literature, from Direct Digital Conversion to Polyphase FFT Filter Banks (PFFB), which can do the job of channelization. But each of them operates with certain constraints and, as a result, suits best to a particular application. Further all of these techniques are generic in nature, in the sense that their structure is independent of any particular standard. With regard to computational requirement of these techniques, PFFB is the best, with respect to the number of complex multiplications required for its implementation. But it needs two very stringent conditions to be satisfied, viz. the number of channels to be extracted is equal to the decimation factor and the sampling rate is a power of 2 times baseband bandwidth. Clearly these conditions may not be satisfied by different wireless communication standards, and in fact, this is not satisfied by the WiMAX standard. This gives us the motivation to analyze the receiver channelizer for WiMAX BS and to find an efficient and low cost architecture of the same. We demonstrate that even though the conditions required by PFFB are not satisfied by the WiMAX standard, we can modify the overall architecture to include the PFFB structure. This is achieved by dividing the receiver channelizer into two blocks. The first block uses the PFFB structure to separate the desired number of channels from the input samples. This process also achieves an integer SRC by a factor that is equal to the number of channels being extracted. This block generates baseband outputs whose sampling rates are related to their target sampling rate by a fractional multiplication factor. In order to bring the channels to their target sampling rate, each output from the PFFB block is fed to a FSRC block, whose job is to use an efficient FSRC algorithm to generate the samples at the target sampling rate. We show that the computational complexity, as compared to the direct implementation, is reduced by a factor, which is approximately equal to the square of the number of channels. After mathematically formulating the receiver channelizer for WiMAX BS, we perform the simulation of the system using a software tool. There are two basic motives behind the simulation of the system which has a mathematical model. Firstly, the software simulation will give an idea whether the designed system is physically realizable. Secondly, this will help in designing the logic for different blocks of the system. Once these individual blocks are simulated and tested, they can be smoothly ported onto an FPGA. For simulation purpose, we parameterize the receiver channelizer in such a way that it can be reconfigured for different ADC sampling rates and IF frequencies, by changing the input clock rate. The system is also reconfigurable in terms of the supported channel bandwidth. This is achieved by storing all the filter coefficients pertaining to each channel type, and loading the required coefficients into the computational engine. Using this methodology we simulate the system for three different IF frequencies (and the corresponding ADC sampling rates) and three different channel types, thus leading to nine different system configurations. The simulation results are in agreement with the mathematical model of the system. Further, we also discuss some important implementation issues for the reconfigurable receiver channelizer. We estimate the memory requirement for implementing the system in an FPGA. The implementation delay is estimated in terms of number of samples. The thesis is organized in five chapters. Chapter 1 gives a brief introduction about the WiMAX system and different existing channelization architecture followed by the outline of the proposed receiver channelizer. In chapter 2, we analyze the proposed receiver channelizer for WiMAX BS and evaluate its computational requirements. Chapter 3 outlines the procedure to generate the WiMAX test signal and specification of the all the filters used in the system. It also lists the simulation parameters and records the results of the simulation. Chapter 4 presents the details of a possible FPGA implementation. We present the concluding remarks and future research directions in the final chapter.