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Journal articles on the topic 'Digital down converter (DDC)'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (August 5, 2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.

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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

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2

Cui, Shu Lin, and Xu Li. "FPGA-Based Design of Resource-Efficient Digital down Converter." Applied Mechanics and Materials 128-129 (October 2011): 878–81. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.878.

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Digital down converter (DDC) is based on the theory of Software Defined Radio (SDR) and multirate signal processing, extensively applied in digital receivers of communications systems. An improved resource-efficient DDC with polyphase architecture and distributed arithmetic (DA) is presented in this paper. The design based on Xilinx FPGA Virtex-5 has more flexible characters and higher precision computation with less resource consumption.

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3

Traykov, Metodi, Radoslav Mavrevski, and Ivan Trenchev. "Modeling of digital converter for GSM signals with MATLAB." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (October 1, 2019): 4417. http://dx.doi.org/10.11591/ijece.v9i5.pp4417-4422.

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In this study will simulate steady state of Digital Down Convertor (DDC) for GSM signal with a narrow frequency range. The MATLAB model that is described in this article simulates the work of the TIGC4016 Quad Digital Down Converter. This converter is used for digital mixing (down conversion) of signals, narrow band low-pass filtering and decimation. To implementation of the model, we use high sample-rate (69,333 MSPS) bandpass signal. The result contains low sample-rate (270.83 KSPS) baseband signal, thus facilitating the demodulation process.

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4

Telagathoti, Pitchaiah, Moparthi Aparna, and P. V. Sridevi. "Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver." International Journal of Engineering & Technology 7, no. 2-1 (March 23, 2018): 421. http://dx.doi.org/10.14419/ijet.v7i2.9242.

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Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.

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5

Jeong, Kil-Hyun. "The Implementation of DDC for the WLAN Receiver." Journal of the Korea Society of Computer and Information 17, no. 2 (February 29, 2012): 113–18. http://dx.doi.org/10.9708/jksci.2012.17.2.113.

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6

Wang, Wen Bin, Dao Yuan Liu, and Yu Qin Yao. "Research and Design of Digital down Converter Based on Software Defined Radio." Applied Mechanics and Materials 513-517 (February 2014): 1803–6. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.1803.

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This paper makes a brief introduction on the current development trend of software radio and digital down converter status. The basic theoretical knowledge: Band-pass sampling theorem, digital signal orthogonal transformation theory, multi-rate signal processing theory. Based on these theories, use MATLAB complete the design and verification of mixing module, the extraction module (CIC filter, half-band filter and FIR filters), finally verify the correctness of the design, and implement DDC.

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7

Xu, Ping, Wei Xia, and Zi Shu He. "A Design of VB-DDC Using DA-Based Systolic FIR Filter." Applied Mechanics and Materials 130-134 (October 2011): 3950–53. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.3950.

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In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

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8

Sahukar, Latha, and Dr M. Madhavi Latha. "Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 88. http://dx.doi.org/10.14419/ijet.v7i2.16.11422.

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This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time occupies only 10% of the slices of FPGA.

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9

Deng, Jun, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, and Lun Cai Liu. "Design of a SoC With High-Speed DDC for Software Radio Receiver." Advanced Materials Research 605-607 (December 2012): 1875–79. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1875.

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This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

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10

Abbas, Ghulam, Jason Gu, Umar Farooq, Muhammad Abid, Ali Raza, Muhammad Asad, Valentina Balas, and Marius Balas. "Optimized Digital Controllers for Switching-Mode DC-DC Step-Down Converter." Electronics 7, no. 12 (December 8, 2018): 412. http://dx.doi.org/10.3390/electronics7120412.

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In this paper, a nonlinear least squares optimization method is employed to optimize the performance of pole-zero-cancellation (PZC)-based digital controllers applied to a switching converter. An extensively used step-down converter operating at 1000 kHz is considered as a plant. In the PZC technique, the adverse effect of the (unwanted) poles of the buck converter power stage is diminished by the complex or real zeros of the compensator. Various combinations of the placement of the compensator zeros and poles can be considered. The compensator zeros and poles are nominally/roughly placed while attempting to cancel the converter poles. Although PZC techniques exhibit satisfactory performance to some extent, there is still room for improvement of the controller performance by readjusting its poles and zeros. The (nominal) digital controller coefficients thus obtained through PZC techniques are retuned intelligently through a nonlinear least squares (NLS) method using the Levenberg-Marquardt (LM) algorithm to ameliorate the static and dynamic performance while minimizing the sum of squares of the error in a quicker way. Effects of nonlinear components such as delay, ADC/DAC quantization error, and so forth contained in the digital control loop on performance and loop stability are also investigated. In order to validate the effectiveness of the optimized PZC techniques and show their supremacy over the traditional PZC techniques and the ones optimized by genetic algorithms (GAs), simulation results based on a MATLAB/Simulink environment are provided. For experimental validation, rapid hardware-in-the-loop (HiL) implementation of the compensated buck converter system is also performed.

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11

Sokolov, Kirill Yu, Vladimir S. Priputin, and Elizaveta O. Lobova. "Implementation of Cosine Modulated Digital Filter Bank on Processor with ARM Architecture." T-Comm 14, no. 11 (2020): 57–63. http://dx.doi.org/10.36724/2072-8735-2020-14-11-57-63.

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This paper presents a class of multichannel cosine-modulated filter banks (CMFB) of analysis based on the modulation effect with a fast discrete-cosine transformation of the fourth type (DCT-IV), which is calculated using the fast Fourier transform. As a prototype filter, a low-frequency filter with a finite pulse characteristic was used, frequency-shifted copies of which were made using an effective technology for polyphase representation of the filter Bank. The comparison of the number of arithmetic operations performed by digital down converter (DDC) based on cascade integral-comb (CIC) and CMFB based on different number of channels is given. A software description of the CMFB algorithm is presented in the form of block diagrams describing the capabilities of the Opencl and clfft software libraries for implementing the DCT-IV filter Bank and modulation algorithm on a GPU. The obtained algorithm was tested on an ARM family processor and a mali GPU with a table with sample rate for different number of channels with the maximum load of the graphics processor (GPU) and the minimum load of the Central processor (CPU).

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Калиниченко, С. В., Ю. С. Балашов, Д. Г. Харин, and А. С. Шнайдер. "METHOD FOR NONLINEARITY MINIMIZATION OF MULTIPLYING DIGITAL-TO-ANALOG CONVERTER BY LOW RESOLUTION CALIBRATION CONVERTER." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 2 (May 11, 2021): 87–93. http://dx.doi.org/10.36622/vstu.2021.17.2.014.

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Представлен метод минимизации нелинейности передаточной характеристики прецизионного умножающего цифро-аналогового преобразователя (ЦАП) с помощью вспомогательного корректирующего ЦАП малой разрядности. В данном методе вспомогательный ЦАП формирует искаженную передаточную характеристику, которая в сумме с передаточной характеристикой основного ЦАП позволяет уменьшить результирующую интегральную и дифференциальную нелинейность. Коэффициенты коррекции, рассчитанные согласно представленному в статье алгоритму, однократно записываются в энергонезависимую память и преобразуются в управляющий сигнал для калибрующего ЦАП с помощью арифметико-логического устройства (АЛУ) в зависимости от входных данных. Для проведения экспериментальных исследований был разработан макет системы калибровки на основе программируемой логической интегральной схемы (ПЛИС) и демонстрационной платы с микросхемой двухканального 16-разрядного ЦАП с сегментированной структурой. Представлены экспериментальные результаты, которые показывают, что в данной системе коррекции собственная нелинейность калибрующего ЦАП не оказывает существенного влияния на итоговую передаточную характеристику. Приведенный алгоритм расчета коэффициентов позволяет эффективно уменьшить абсолютную интегральную и дифференциальную нелинейность 16-разрядного ЦАП до значений менее 1 единицы веса младшего разряда (ЕМР) In this paper, we present a method for nonlinearity minimization of precision multiplying digital-to-analog converter (DAC) by utilizing low resolution calibration DAC. In this method the calibration DAC generates distorted transfer characteristic which is added to the main DAC characteristic and provides resulting integral and differential nonlinearity reduction. The calibration coefficients are calculated following the presented algorithm and saved in nonvolatile memory and then are converted to controlling digital code of calibration DAC by arithmetical-logical unit (ALU) depending on input data. For experimental research we designed a model of calibration system based on field programmable gate array (FPGA) and a demo board with dual 16-bit segmented DAC. Then we give experimental results which show that inherent nonlinearity of calibration DAC does not significantly affect overall nonlinearity. The proposed calculation algorithm obtains effective integral and differential nonlinearity minimization of 16-bit DAC down to values of less than one least significant bit (LSB)

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13

Karcher, N., D. Richter, F. Ahrens, R. Gartmann, M. Wegner, O. Krömer, S. Kempf, C. Enss, M. Weber, and O. Sander. "SDR-Based Readout Electronics for the ECHo Experiment." Journal of Low Temperature Physics 200, no. 5-6 (April 30, 2020): 261–68. http://dx.doi.org/10.1007/s10909-020-02463-w.

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Abstract Due to their excellent energy resolution, the intrinsically fast signal rise time, the huge energy dynamic range, and the almost ideally linear detector response, metallic magnetic calorimeters (MMC)s are very well suited for a variety of applications in physics. In particular, the ECHo experiment aims to utilize large-scale MMC-based detector arrays to investigate the mass of the electron neutrino. Reading out such arrays is a challenging task which can be tackled using microwave SQUID multiplexing. Here, the detector signals are transduced into frequency shifts of superconducting microwave resonators, which can be deduced using a high-end software-defined radio (SDR) system. The ECHo SDR system is a custom-made modular electronics, which provides 400 channels equally distributed in a 4 to 8 GHz frequency band. The system consists of a superheterodyne RF frequency converter with two successive mixers, a modular conversion, and an FPGA board. For channelization, a novel heterogeneous approach, utilizing the integrated digital down conversion (DDC) of the ADC, a polyphase channelizer, and another DDC for demodulation, is proposed. This approach has excellent channelization properties while being resource-efficient at the same time. After signal demodulation, on-FPGA flux-ramp demodulation processes the signals before streaming it to the data processing and storage backend.

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14

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

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15

Wu, Zhang Yu, Xian Wang, Ye Hui Wu, and Long Cheng Que. "An N-Bit DAC with Adjustable Precision and Range." Advanced Materials Research 846-847 (November 2013): 822–25. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.822.

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Now some special circuits need higher precision in relatively fixed range. While the precision of a common digital-to-analog converter (DAC) is equidistant, which means the higher the precision is, the greater the number of bits. The increase of number of bits will slow down the speed of converter. This architecture we present here aims at finding a way of solving the problem. It uses M bits of the N-bit DAC to adjust precision by changing the current of the voltage division circuit, which alters the range of the DAC to a certain extent.

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16

SHIN, YOUNG SAN, JAE-KYUNG WEE, JONG-CHAN HA, JI-HOON LIM, YONG-JU KIM, and YOUNG-SANG SON. "A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS." Journal of Circuits, Systems and Computers 20, no. 04 (June 2011): 741–56. http://dx.doi.org/10.1142/s021812661100758x.

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A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

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17

Ameur, Noura Ben, Nouri Masmoudi, and Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

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18

Wei, Jingwei, Xuan Li, Lei Sun, and Dongmei Li. "A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors." Electronics 9, no. 5 (May 4, 2020): 757. http://dx.doi.org/10.3390/electronics9050757.

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A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.

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Bekal, Anush, Shabi Tabassum, and Manish Goswami. "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC." Journal of Circuits, Systems and Computers 26, no. 05 (February 8, 2017): 1750077. http://dx.doi.org/10.1142/s0218126617500773.

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The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

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Zhang, Shao Rong, Zhi Li, and Ai Jun Zhu. "FPGA-Based High Precision and Low EMI Switching Power Supply Design." Applied Mechanics and Materials 496-500 (January 2014): 1442–47. http://dx.doi.org/10.4028/www.scientific.net/amm.496-500.1442.

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We analyze the reasons why DC-DC switching power supply generates the electromagnetic interference (EMI), and through the FPGA control the digital-to-analog converter (DAC) to output the pulse width modulation (PWM) signal with high precision and slew rate controlled, the slew rates of the voltage and current of external N-channel MOSFET are controlled. So, dv/dt and di/dt can be decreased in the circuit; and the ripple noise and EMI of switching power supply are reduced vastly in this way. Experimental results show that the ripple noise of switching power supply could be reduced by 80% and EMI reduced 15dBμV. The experiment has proved that we can cut down the ripple noise and EMI of switching power supply by lessening the slew rates of the voltage and current of MOSFET switching tube.

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Xia, Ming, Zunkai Huang, Li Tian, Ning Wang, Yongxin Zhu, Hui Wang, and Songlin Feng. "An Area-Efficient 10-Bit Buffer-Reused DAC for AMOLED Column Driver ICs." Electronics 9, no. 2 (January 22, 2020): 208. http://dx.doi.org/10.3390/electronics9020208.

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In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm2, which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

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22

Guo, Lianping, Feng Tan, Peng Zhang, and Hao Zeng. "Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750126. http://dx.doi.org/10.1142/s0218126617501262.

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The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO’s output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique.

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23

Yan, Ji Hong, Zi Shu He, Xiao Hong Tang, and Dao Guo Yang. "A Wideband DDC Design Using Distributed Arithmetic." Applied Mechanics and Materials 321-324 (June 2013): 1303–6. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.1303.

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In this paper, the technique of distributed arithmetic (DA) and digital down conversion (DDC) are described. Then, an efficient wideband DDC based on polyphase structure with intermediate frequency (IF) bandpass sampling is presented. An optimized distributed arithmetic is used for saving the FPGA multiplier consumption. A design example is given and the FPGA resource consumption saving is discussed also. The corresponding test results demonstrate the effectiveness of the proposed DDC design using distributed arithmetic.

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Prof R.A.Patil, J.S. Pillai, Ganesh P. Sonar,. "Digital down Converter for Pulse Radar Receiver." International Journal of Innovative Research in Computer and Communication Engineering 03, no. 05 (May 30, 2015): 4000–4006. http://dx.doi.org/10.15680/ijircce.2015.0305038.

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Xie, Xiao Ming, and Hui Meng Huang. "Design and Analysis of Digital Filter in Digital Down Converter." Advanced Materials Research 433-440 (January 2012): 2844–49. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.2844.

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In this paper, based on the analysis and discussion of multistage decimation structure, we have studied and analyzed some key technologies of the digital filter in digital down conversion. Meanwhile, we have analyzed and summarized the decimation filter modules as CIC, HB, FIR of the digital filter, and a multistage decimation filter design program is given in this paper. An optimum design method is proposed in this article, which greatly reduce the complexity of system design and memory usage and has upgrade the data rate operation with great extent.

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He, Hong, De Peng Sha, and Hong Sun. "The SIMULINK Modeling and FPGA Realization of Digital down Converter." Advanced Materials Research 186 (January 2011): 131–35. http://dx.doi.org/10.4028/www.scientific.net/amr.186.131.

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Digital down converter is the core technology of soft radio receiver. It lets the high-speed-sampled digital signals down-conversion to base band down and then are decimated and high-passed filtered. This paper puts the main emphasis on analyzing the modeling and simulation by SIMULINK of digital mixing converter part and CIC decimation filter part of digital down converter and the realization on FPGA. It has been showed by the results that the problem that the operational pressure is too big to DSP and much too wide bandwidth gose against the channel separation when processing digital signal directly after A/D sampler has been solved well by digital down converter and decimating to reduce unnecessary data.

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Wang, Hong-xian, Gang Li, Meng-dao Xing, and Shou-hong Zhang. "Design of Digital Down Converter of Mini SAR." JOURNAL OF ELECTRONICS INFORMATION & TECHNOLOGY 32, no. 2 (March 17, 2010): 485–89. http://dx.doi.org/10.3724/sp.j.1146.2008.01770.

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Singh, Charanjit. "Design of programmable digital down converter for WiMAX." Indian Journal of Science and Technology 2, no. 3 (March 20, 2009): 1–2. http://dx.doi.org/10.17485/ijst/2009/v2i3.13.

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Li, Yao. "Design and Research of Digital Decimation Filter Based on FPGA." Applied Mechanics and Materials 105-107 (September 2011): 2086–91. http://dx.doi.org/10.4028/www.scientific.net/amm.105-107.2086.

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This paper studies and analyses various digital filter and decimation structure. On this basis, by using QUARTUS development system design the decimation device modules, through the waveform simulation validated its correctness. Finally,a program is written into FPGA chip by the hardware platform. In the digital down conversion (DDC), CIC (cascade integral comb) filter plays an important role. It is mainly used for sampling rate, as well as low-pass filter effect. The main characteristics of CIC filter, using only adders, subtractor and register (no multiplier), so fewer resources occupied, implementation is simple and high speed. Based on the analysis of the principle of CIC filter,simulate and synthesize based on the theory of using VHDL language in FPGA. And successful application in the development of DDC chip. Keyword: CIC (cascade integral comb) filter,FPGA,VHDL

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Han, Chun Yang, Wei Sun, and Gui Xin Han. "DDC Design for Multi-Frequency Receiver Based on RF Sampling." Applied Mechanics and Materials 651-653 (September 2014): 413–16. http://dx.doi.org/10.4028/www.scientific.net/amm.651-653.413.

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Multi-frequency receivers rely on GNSS to achieve high-precision positioning, high sensitivity and other functions. GNSS signal frequencies are widely distributed around 1.1GHz to 1.6GHz. Good performance RF front-end receiver will provide high-quality acquisition and tracking environment, reducing the SER to ensure CNR. RF sampling technique is widely used in software radio for its simple structure, flexible configuration, and other advantages, but rarely used in satellite navigation, because the high signal carrier frequency and sampling rate, down-conversion based on RF sampling becomes a big challenge. So, to solve the problems of widely distributed we design three signal bands, using different local oscillator to implement signal down-conversion; to solve the problems of high sampling rate, we propose a down-conversion program of using a cascade of CIC filter’s ployphase and FIR compensation filter. Through the simulation of MATLAB after tracking tests, analysis of CNR and other indicators of programs. Ultimately, we implement the program with Verilog language on the multi-frequency GNSS receiver. The results show that this scheme can achieve digital down-conversion and stable performance of tracking loop with less consumption of resources.

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Martens, E., and G. Gielen. "ANTIGONE: Top-down creation of analog-to-digital converter architectures." Integration 42, no. 1 (January 2009): 10–23. http://dx.doi.org/10.1016/j.vlsi.2008.07.001.

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Shyh-Jye Jou and Tsu-Lin Chen. "On-chip voltage down converter for low-power digital system." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 5 (May 1998): 617–25. http://dx.doi.org/10.1109/82.673644.

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Shyh-Jye Jou, Shou-Yang Wu, and Chorng-Kuang Wang. "Low-power multirate architecture for IF digital frequency down converter." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 11 (1998): 1487–94. http://dx.doi.org/10.1109/82.735360.

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Ruan, C. F., J. Y. Hua, W. K. Kuang, Z. J. Xu, and Z. L. Zheng. "A Multi-stage Design of Intermediate Frequency Digital down Converter." Information Technology Journal 11, no. 5 (April 15, 2012): 651–57. http://dx.doi.org/10.3923/itj.2012.651.657.

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Agarwal, Neeraj, Neeru Agarwal, Chih-Wen Lu, and Masahito Oh-e. "A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application." Electronics 10, no. 14 (July 20, 2021): 1743. http://dx.doi.org/10.3390/electronics10141743.

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This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

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Kim, Miyeon, and Seungjun Lee. "Design of Dual-Mode Digital Down Converter for WCDMA and cdma2000." ETRI Journal 26, no. 6 (December 9, 2004): 555–59. http://dx.doi.org/10.4218/etrij.04.0804.0013.

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., Shrita G. "AN AREA EFFICIENT DIGITAL DOWN CONVERTER USED IN 4G WIRELESS RECEIVERS." International Journal of Research in Engineering and Technology 04, no. 26 (December 25, 2015): 67–70. http://dx.doi.org/10.15623/ijret.2015.0426014.

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Pasko, R., L. Rijnders, P. R. Schaumont, S. A. Vernalde, and D. Durackova. "High-performance flexible all-digital quadrature up and down converter chip." IEEE Journal of Solid-State Circuits 36, no. 3 (March 2001): 408–16. http://dx.doi.org/10.1109/4.910479.

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Li, Bo, Xuefang Lin-Shi, and Bruno Allard. "Low Power Digital Alternative to Analog Control of Step-Down Converter." Journal of Low Power Electronics 8, no. 5 (December 1, 2012): 654–66. http://dx.doi.org/10.1166/jolpe.2012.1223.

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Li, Mei. "Using of Downsampling Theory Base on Shannon in Software Radio." Advanced Materials Research 1049-1050 (October 2014): 1526–30. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.1526.

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The theory of down sampling technique base on band-pass sampling and using inSoftware radio is introduced in this paper. We provided an achievement method ofNumerically controlled oscillator (NCO) in digital down converter of down samplingtechnique in the article.

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S, Parameshwar, M. Rajmohan, and Punithavathy Mohan. "AN EFFICIENT DESIGN OF DIGITAL DOWN CONVERTER FOR SOFTWARE DEFINED RADIO APPLICATION." International Journal of Advanced Research 5, no. 3 (March 31, 2017): 795–807. http://dx.doi.org/10.21474/ijar01/3574.

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DU Zhao-kai, 杜兆凯, 马宗方 MA Zong-fang, and 谷卓 GU Zhuo. "Design and implementation of digital down converter system based on optimized mixer." Chinese Journal of Liquid Crystals and Displays 33, no. 11 (2018): 943–49. http://dx.doi.org/10.3788/yjyxs20183311.0943.

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Abinaya, A., and M. Maheswari. "A survey of digital down converter architecture for next generation wireless applications." IOP Conference Series: Materials Science and Engineering 872 (June 27, 2020): 012037. http://dx.doi.org/10.1088/1757-899x/872/1/012037.

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Rana, Priya, and Rajesh Mehra. "Design Analysis of Channel Filter for Digital Down Converter in WiMAX Application." International Journal of Computer Applications 131, no. 16 (December 17, 2015): 17–22. http://dx.doi.org/10.5120/ijca2015907598.

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Hong, Do-Hyeong, Kyung Bo Lee, and Young-Chul Rhee. "Implementation of Wideband Low Noise Down-Converter for Ku-Band Digital Satellite Broadcasting." Journal of Korean Institute of Electromagnetic Engineering and Science 27, no. 2 (February 29, 2016): 115–22. http://dx.doi.org/10.5515/kjkiees.2016.27.2.115.

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N, Narendra, Degala Srilakshmi, and Mohankumar V. "DESIGN OF DIGITAL DOWN CONVERTER AND SIGNAL DETECTION TECHNIQUES FOR SOFTWARE DEFINED RADIO." International Journal of Engineering Applied Sciences and Technology 4, no. 1 (May 31, 2019): 98–102. http://dx.doi.org/10.33564/ijeast.2019.v04i01.017.

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Liu, Xue, Xin-Xin Yan, Ze-Ke Wang, and Qing-Xu Deng. "Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 12 (December 2017): 3548–52. http://dx.doi.org/10.1109/tvlsi.2017.2748603.

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harris, fred, Elettra Venosa, Xiaofei Chen, and Markku Renfors. "Cascade linear phase recursive half-band filters implement the most efficient digital down converter." Analog Integrated Circuits and Signal Processing 73, no. 2 (July 10, 2012): 531–43. http://dx.doi.org/10.1007/s10470-012-9905-9.

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Okcan, Burak, Patrick Merken, Georges Gielen, and Chris Van Hoof. "A cryogenic analog to digital converter operating from 300 K down to 4.4 K." Review of Scientific Instruments 81, no. 2 (February 2010): 024702. http://dx.doi.org/10.1063/1.3309825.

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Wang, Qing Dong, and Fei Wu. "An Improved Digital Servo Burst Signal Sampling Model for Disk Drives." Applied Mechanics and Materials 239-240 (December 2012): 857–60. http://dx.doi.org/10.4028/www.scientific.net/amm.239-240.857.

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In order to calculate the servo position error signal (PES) in the servo system, it is necessary to make high precision sampling and FFT calculation for the burst signal. Most designer s adopt 8bits ADC converter in the read write channel servo system of hard drive controller chip 88i6310 to cost down, and both servo system and signal system share the sampling circuit. Because of the quantitative noise disturbing during the sampling process, it is not enough to use 6bits ADC converter for the serve burst signal, and significant error exist for t he burst signal with the FFT calculation. This paper analyzed the existing servo over-sampling model via quantitative error model firstly, and provided the enhanced servo system sampling model. The simulation shows that, the enhanced solution reduces the average quantitative error from 0. 38 LSB to 0.14LSB, and improves the resolution of ADC converter from 9.5 bits to 10.8 bits.

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