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Dissertations / Theses on the topic 'Digital flesh'

Author: Grafiati
Published: 29 September 2023

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1

Ciacciulli, A. "FRUIT FLESH IN PEACH:CHARACTERIZATION OF THE 'SLOW SOFTENING' TEXTURE." Doctoral thesis, Università degli Studi di Milano, 2018. http://hdl.handle.net/2434/540666.

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The aim of this research was to deepen the knowledge about the slow softening texture in peach. The texture is a synthesis of several parameters detected by senses, derived from the food structure. The paramount sense in the texture perception is the tactile one, principally perceived by hand and mouth. The tactile perception is a combination of four classes of mechanoreceptors, each one specialized to perceive mechanic deformation with different speed. This combined perception influences the consumer evaluation of food quality, giving the texture importance among food characteristics. The t
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Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.

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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing s
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3

Puig, Mailhol Vincent. "Le numérique et l'esprit. Prendre soin des technologies numériques de l'esprit à la lumière de Gilbert Simondon, Maurice Merleau-Ponty, Henri Bergson." Electronic Thesis or Diss., Poitiers, 2023. http://www.theses.fr/2023POIT5001.

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Cette adresse aux designers procède d'une démarche de décentrement anthropologique pour tenter de penser et prendre soin du digital comme spiritual au sens où Derrida interprétait ainsi le processus de questionnement mais aussi la technique chez Heidegger. Cet itinéraire passe par une critique de la notion d'information chez Simondon pour repenser « l'âme des objets ». Il se poursuit par une analyse de la question de la chair à partir de Merleau-Ponty pour proposer le passage d'une « chair souffrante du numérique » à une organologie et une pharmacologie du geste digital. Il aborde enfin ce que
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4

Seto, Jim Carleton University Dissertation Engineering Electrical. "An 8 bit BiCMOS subranging flash analog to digital converter." Ottawa, 1991.

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5

Hassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

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<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion
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6

Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.

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7

Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.

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<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled
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8

Cicalo, James. "An embedded calibration technique for high-resolution flash time-to-digital converters." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31637.

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As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this Increase In operating frequency has resulted in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies
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9

Säll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator technology /." Linköping : Linköpings universitet, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.

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10

Guerrero, Maximiliano. "“3-1, shut your flash” : How shooter games convey agency." Thesis, Karlstads universitet, Institutionen för geografi, medier och kommunikation (from 2013), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-80328.

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This study aims to understand how games teach the player how to enact agency within them. Agency refers to the ability of the player to actively interact with the world around them, and understand the circumstances and results of those actions. Three games of the shooter sub-genre were selected: Call of Duty: Modern Warfare (2019), Cuphead, and Red Dead Redemption 2. These were chosen as they are modern representations of three of the most popular genres within the shooter mantle: First-Person Shooter, Run and Gun, and Third-Person Shooter, respectively. Each game’s first level was analyzed to
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11

Sheikhaei, Samad. "A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2746.

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The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampli
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12

Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.

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A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivato
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13

Säll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator CMOS technology /." Linköping : Department of Electrical Engineering, Linköping University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.

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14

Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage str
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15

Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa<br>More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, wh
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16

Brady, Philomena C. "Offset correction in flash ADCs using floating-gate circuits." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14832.

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17

Lindh, Lina, and Atena Ahmadi. "Digital presentation av Sunnerbogymnasiet : - En studie över hur VR kan användas för att locka nya elever." Thesis, University of Kalmar, School of Communication and Design, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hik:diva-2105.

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<p>Syftet med detta arbete är att skapa en applikation som ska hjälpa och gynna Sunnerbogymnasiet när det gäller att locka till sig elever som går på högstadiet. För att göra detta har gruppen använt sig av bland annat VR (Virtual Reality) och Panorama som metoder till att göra applikationen attraktiv för målgruppen. För att få fram vad som kan locka elever till att använda applikationen utfördes enkätundersökningar på målgruppen som är elever i årskurs 8-9. Genom undersökningarna fick gruppen fram vad för information applikationen bör innehålla för att locka till sig elever. Med hjälp utav in
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18

EL, RACHINI ALI. "Redundant analog to digital conversion architectures in CMOS technology." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266860.

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The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure
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19

Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.

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Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (
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20

Savory, Fuller Rebecca. "Embodying 'new India' through remixed global performance : flash mobs redefined in contemporary urban India, 2003-15." Thesis, University of Exeter, 2018. http://hdl.handle.net/10871/33146.

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This thesis conducts a history of flash mob performance in India, asking how the form has evolved over a 12-year period from its first emergence in 2003. Due to its rhizomatic appearance worldwide and its close association with internet technologies and digital culture, the flash mob has typically been treated as a ‘global’ phenomenon, and theories of flash mob performance derived from Euro-American contexts are frequently glossed as generic. However, this thesis asks what a close history of the genre in India can reveal, both in terms of the performance practice itself, and as a reflection of
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21

Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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22

Rossoni, Mattos Diego. "Design and characterization of an 8gsps flash analog-to-digital converter for radio astronomy and cosmology applications." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14653/document.

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Un Convertisseur Analogique-Numérique (CAN) pour les applications spatiales en astrophysique et cosmologie a été développé au cours de cette thèse. Cette catégorie de circuits demande des bandes passantes très larges, de très hautes fréquences d'échantillonnage et une faible résolution. L’architecture flash a été retenue pour sa rapidité et sa bande passante. La fréquence d’échantillonnage est de 8GHz. La technologie utilisée est la CMOS 65 nm de chez STMicroeletronics. La conception a été faite en deux phases. Une première qui a amené à un prototype d'un échantillonneur-bloqueur et une deuxiè
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23

Hennen, John Andrew. "Registration Algorithms for Flash Inverse Synthetic Aperture LiDAR." University of Dayton / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1576142937639181.

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24

Antonopoulou, Aikaterini. "From digital creations of space to analogous experiences of places : living in second life and acting in Flash Mob." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/2316.

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This dissertation aims to raise the question of how individuals and groups become placed – or take up place – in the contemporary environment and to consider what forms the need for situatedness takes today, by examining the phenomena of the Flash Mob and Second Life. In a Flash Mob, an email activates a virtual community and converts it into a physical performance in the city, challenging a new cognition of place, where place is constituted by the event. On the other hand, Second Life takes the form of a digitally constructed world, which opens the possibility of a “virtual place” that enable
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25

Kakizaki, Valter Eiji 1988. "Aspectos gerais e técnicos do violino/viola sob a perspectiva de Carl Flesch e Ivan Galamian : suas influências na era digital." [s.n.], 2014. http://repositorio.unicamp.br/jspui/handle/REPOSIP/285225.

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Orientador: Emerson Luiz De Biaggi<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Artes<br>Made available in DSpace on 2018-08-26T08:41:14Z (GMT). No. of bitstreams: 1 Kakizaki_ValterEiji_M.pdf: 7721830 bytes, checksum: 6364af8be28879188712d29b477bdcc2 (MD5) Previous issue date: 2014<br>Resumo: Este trabalho tem por finalidade a compreensão e comparação dos pensamentos de dois dos mais importantes pedagogos do ensino de violino no século XX, Carl Flesch e Ivan Galamian, e averiguar suas influências nos dias de hoje em vídeos disponibilizados na internet. Inicialm
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26

Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

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Stefanou, Nikolaos. "A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2469.

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Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av- eraging flash A/D converter using comparator chopping. Chopping of comparators in a flash A/D converter was never previously implemented due to lack of feasibility in implementing multiple, uncorrelated, high speed random number generators. This work proposes a novel array of uncorrelated truly binary random number generators working at 1GHz to chop all co
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Grillo, Kelly J. "An investigation of the effects of using digital flash cards to increase biology vocabulary knowledge in high school students with learning disabilities." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4907.

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The field of science education, specifically biology, is becoming more challenging due to richer and more rigorous content demands. Along with new demands is the emergence of National Common Core Standards and End of Course Exams. Despite these changes, one factor remains consistent: As content knowledge increases, language demands also increase. For students with learning disabilities (LD), specifically those with language-based disabilities, the increasing vocabulary demand can lead to failure due not to a lack of understanding biology but the vocabulary associated with the content. In an at
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29

Vaiho, :. Sara. "Konsten att döda en digital teknologi och tillvaron därefter : En kvalitativ studie om aktiviteter vid avvecklingen av ettinformationssystem." Thesis, Mittuniversitetet, Institutionen för data- och systemvetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41258.

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To end the use of a digital technology one must go througha process that research entitle information systems (IS)discontinuance. Prior research has developed phases andactivities that can be implemented in the IS discontinuanceprocess, but this knowledge is limited and has not beencompiled. This study purpose is therefore to create a modelof the IS discontinuance process and in it identify furtheractivities. To accomplish this, a real IS discontinuance hasbeen studied, who has had different circumstances andstakeholders than of previous studies. The discontinuanceprocess has occurred at a lar
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30

Josyula, Sai Prashanth. "On the Applicability of a Cache Side-Channel Attack on ECDSA Signatures : The Flush+Reload attack on the point multiplication in ECDSA signature generation process." Thesis, Blekinge Tekniska Högskola, Institutionen för datalogi och datorsystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10820.

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Context. Digital counterparts of handwritten signatures are known as Digital Signatures. The Elliptic Curve Digital Signature Algorithm (ECDSA) is an Elliptic Curve Cryptography (ECC) primitive, which is used for generating and verifying digital signatures. The attacks that target an implementation of a cryptosystem are known as side-channel attacks. The Flush+Reload attack is a cache side-channel attack that relies on cache hits/misses to recover secret information from the target program execution. In elliptic curve cryptosystems, side-channel attacks are particularly targeted towards the po
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31

Kučerka, Daniel. "Návrh animace digitálního spojovacího pole." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217315.

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This thesis describes types and parameters of memories used in communication engineering. The memory is a device which is able to record and to save information for the certain period of time. The memory is used in computers, measuring devices, consumer electronics etc. Main parameters of the memory are capacity, data stream speed, price of bit and time of memory cycle. The first part of this thesis deals with two types of memory – external and internal. External memories are removable media such as discs and magnetic tapes used for information saving and data backup for longtime period. Inner
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32

Queiroz, Alan Rômulo Silva. "Utilização de relés digitais para mitigação dos riscos envolvendo arco elétrico." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-30052012-124531/.

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O trabalho tem como objetivo avaliar e propor a utilização de soluções tecnológicas que permitam a redução dos riscos causados por arcos elétricos nas instalações de uma unidade industrial com sistema isolado de geração elétrica. Por ser extremamente danosa à segurança das pessoas que interagem com uma instalação elétrica e por causar danos significativos aos equipamentos e instalações, a energia incidente, proveniente de um arco elétrico, deve ser mensurada em conformidade com as normas existentes e os riscos devem ser controlados e mitiga
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33

Preston, Douglas. "Last Two Surface Range Detector for Direct Detection Multisurface Flash Lidar in 90nm CMOS Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright150392243439439.

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34

Bojan, Vujičić. "Detekcija nule A/D konvertorom niske rezolucije." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2017. https://www.cris.uns.ac.rs/record.jsf?recordId=104132&source=NDLTD&language=en.

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U tezi je rešavan centralni problem &ndash; detekcija nule dvobitnomstohastičkom digitalnom mernom metodom (SDMM). Formulisane sudve metode detekcije nule primenom dvobitne SDMM. Po prvoj metodidinamička rezerva je oko 100 dB a po drugoj ne manje od 160 dB. Obemetode su proverene teorijski, simulaciono i eksperimentalno. Poredrešenja centralnog problema, dato je i nekoliko rešenja problemakoji su sa njim vezani. Hipoteza ove teze &ndash; &bdquo;dvobitna SDMM je u opsegu0 % - 10% FS bolja od standardne sempling metode (SSM)&ldquo; &ndash; je potpunopotvrđena u svim razmatranim slučajevima.<br>T
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Marjan, Urekar. "Prilog optimizaciji performansi digitalnih merenja." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2018. https://www.cris.uns.ac.rs/record.jsf?recordId=107133&source=NDLTD&language=en.

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U tezi se razmatra kriterijum optimalnosti stohastičkog fleš A/D konvertora (SFADC) koji predstavlja osnovu stohastičke digitalne metode merenja (SDMM). Razvijen je matematički i simulacioni model višebitnog SFADC i određen optimum broja bita rezolucije. Napravljen je hardverski prototip 4-bitnog stohastičkog mernog instrumenta (SMI), koji je ispitan brojnim eksperimentima i upoređen sa teorijski određenim vrednostima performansi merenja. Hipoteza ove teze &ndash; da postoji optimalni broj bita rezolucije SMI pri kome se ostvaruje maksimalna dobit u preciznosti merenja po ceni dupliranja potre
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Sibanda, Phathisile. "Connection management applications for high-speed audio networking." Thesis, Rhodes University, 2008. http://hdl.handle.net/10962/d1006532.

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Traditionally, connection management applications (referred to as patchbays) for high-speed audio networking, are predominantly developed using third-generation languages such as C, C# and C++. Due to the rapid increase in distributed audio/video network usage in the world today, connection management applications that control signal routing over these networks have also evolved in complexity to accommodate more functionality. As the result, high-speed audio networking application developers require a tool that will enable them to develop complex connection management applications easily and w
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Kobal, Damjan. "The use of technology to motivate, to present and to deepen the comprehension of math." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-80412.

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The aim of the workshop is to present and discuss several ideas which relate to technology as well as to creative teaching. Educational experience, common sense and educational research have all proven how important for comprehensive understanding different cognitive representations are. We will present and discuss several elementary mathematical ideas of which mechanical realisations mean ingenius technological inventions (for example: ‘car differential’ and ‘digital sound technology’). Technological insights can provide deep intuitive understanding of otherwise abstract mathematical concepts
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.

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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (S
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Hancock, Amber N. "A Radical Approach to Syntheses and Mechanisms." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/77139.

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The critically important nature of radical and radical ion mechanisms in biology and chemistry continues to be recognized as our understanding of these unique transient species grows. The work presented herein demonstrates the versatility of kinetic studies for understanding the elementary chemical reactions of radicals and radical ions. Chapter 2 discusses the use of direct ultrafast kinetics techniques for investigation of crucially important enzymatic systems; while Chapter 3 demonstrates the value of indirect competition kinetics techniques for development of synthetic methodologies for co
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Huang, Chun-Cheng, and 黃鈞正. "Digitally-Calibrated Comparator and Its Application in Flash Analog-to-Digital Converters." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/60362296932435912652.

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博士<br>國立交通大學<br>電子研究所<br>98<br>This thesis presents a digital background calibration technique to trim the input-referred offsets of a comparator circuit. The calibration does not interrupt the normal operation of the comparator, hence is suitable for high speed and power efficient applications such as flash analog-to-digital converters(ADC). For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. A calibration loop is then used to adjust the comparator offset so that the offset is minimized. All procedures in the calibr
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Maleki, Mohammad. "Current-mode flash analog-to-digital converter." Thesis, 1992. http://hdl.handle.net/1957/37347.

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This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip area, and simple division of reference current based on current mirror. A current-mode comparator is designed consisting of a cascode current mirror and a current sense amplifier used as a latch. The new method allows effective and simple high-speed A/D conversion where the input is a current signal and the output of the latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using current
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Lin, Kaih-Ping, and 林凱評. "High Speed Flash Analog to Digital Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/12280330170131356783.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>91<br>Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. In this thesis, a flash ADC architecture is proposed to have 400 MHz samples rate with 6-bit resolution. We design the high speed architectu
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Sie, Ming-Jhou, and 謝明周. "4-Bit flash analog-to-digital converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60460902388790029068.

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碩士<br>建國科技大學<br>電子工程系暨研究所<br>99<br>We use TSMC0.35μm2P 4M technology to design a positive feedback 3-bit 20MHz flash analog-to-digital converter and a 4-bit 1GHz flash analog-to-digital converter with hysteresis comparator. Reference potential was generated by resistor array, then compared with the input potential, and the resulting thermometer code pass through the pre-encoding circuit (1-out-of-N) and post-encoding circuit (Binary Code) after output. The 4-bit flash analog-to-digital-converter features working voltage range from 0.9 to 2.2 V, sampling rate of 1GHz, the power consumption is 5
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Lin, Kai-Chie, and 林凱琪. "High Speed Flash Analog to Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56085018306124426889.

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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>90<br>Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, colour, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. The designs of analog to digital converter are innovative and versatile to have higher speed, more accuracy and stability, along with low operatin
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Chang, Hsuan-Yu, and 張軒瑜. "Design of Low-Power Flash Analog-to-Digital Converters Using Digital Calibration." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47809309624999322555.

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博士<br>國立中興大學<br>電機工程學系所<br>104<br>Flash-type ADCs have the inherent advantage on high-speed sampling rates. Although the flash ADC is superiority in sampling rate but its large power consumption makes itself bottleneck in many applications. Speed, power and accuracy are tradeoff in high-speed CMOS ADC design. Process technology scaling trends toward smaller transistor dimensions and low supply voltage, and thereby it leads to greatly reduce power consumption in flash ADCs. The never-ending story of CMOS technology trending toward smaller transistor dimensions has resulted to date in deep submi
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Hsu, Ying-Yu, and 徐瑛佑. "Ultra High-Speed Flash Analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/9wam6k.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>93<br>Due to the advance process technologies, the operating frequency and circuit complexity of integrated circuit increase. The interfaces between the analog and the digital parts are required to operate at ultra high speed (over giga samples per second). The high-bit-rate applications include DVD read channel, multi level receiver, channel equalizer, jitter measurement system, and Ethernet need Analog-to-Digital Converters. There are two major topics in this thesis. First, we focus on the high speed ADC circuit design. Thus, we propose a 4-bit flash ADC typi
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白薇詩. "Pipelined Encoding for a Flash Analog-to-Digital Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40064734984142616238.

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碩士<br>國立彰化師範大學<br>電機工程學系<br>96<br>In this research, fundamentals of power line signal sampling, quantization, and design of a pipelined encoder for flash analog to digital converter (Flash ADC) are presented. The current mode logic (CML) is applied because of lower voltage supply and faster processing time are considered. The second stage of this research is the analytical individual case of the electric power quality signal .The power quality has become an increasingly important topic due to rapid development of high-technology and precision instrument industries. Therefore, the quality of st
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Lien, Yu-Chang, and 連昱彰. "Low-Power High-Speed Flash Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/01613899949492304196.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cance
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WANG, GUO-LONG, and 王國隆. "A new current-mode flash analog-to-digital converter." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/27257510409184859270.

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Sajjadian, Farnad. "A 10MHz flash analog-to-digital converter system for digital oscilloscope and signal processing applications." 1985. http://hdl.handle.net/2097/27577.

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