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1
Cronin, Christopher Joseph. "Digital frequency demodulation for a laser vibrometer." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11102009-020344/.
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Peng, Song, Zhang XiaoLin, Cao Xue, and Qi Xia. "THE APPLICATION OF DIGITAL DEMODULATION TECHNIQUE FOR FREQUENCY MODULATION SIGNAL IN TELEMETRY RECEIVER." International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/604956.
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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, CaliforniaCombined with an example of digital telemetry receiver design, this paper mainly discusses the application of software radio in telemetry receiver. The paper begins with an introduction of applying high efficiency digital filter and math analysis in quadrature digital frequency modulation and demodulation to digital frequency conversion technique. Next, Simulink/Matlab is used to simulate digital telemetry receiver. The method of simulation, analysis and calculation of performance and result of simulation are all available. In the end, the paper discusses digital telemetry receiver design and implement by making use of software radio technique, the circuits apply HSP50214 chip of Intersil Co., CPLD implements of Altera Co. and PC Bus. The sample is an expansion card for personal computer. Result of test, performance of the receiver and conclusion are given out, which show fine performance of receiver and can be apply to practice. The lever of this technology has reached first class in the world.
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Monica, G. Della, and E. Tonello. "NEW GENERATION COMMAND RECEIVER FOR SATELLITE USING BENEFITS OF DIGITAL PROCESSING." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607344.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaPresentation of Alcatel Espace last studies and developments regarding TT&C receiver Products for satellite. This document lays on 3 parts: · a technical point of view showing digital demodulation principles used (base band recovery, analytical head, PM or FM demodulation) and their related offered possibilities(digital controlling loop, lock status detection, jammer detection,....) · a technology/design description · a synthesis showing performance and results
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Ozturk, Uygar. "Chaotic Digital Modulation And Demodulation." Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/2/12606895/index.pdf.
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This thesis considers a communication system with chaotic modulation. Noise-like signals are generated by chaotic systems with different parameters to modulate binary digital signals. Demodulation is performed by both the Extended Kalman Filter (EKF) and Optimum Decoding Based Smoothing Algorithm (ODSA). Simulations are performed using both of these algorithms for different parameters affecting the performance of the communication system. Simulation results of these algorithms are compared.
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Lin, Chun-Ching. "Demodulation of Narrowband Radio Frequency Signals by Aliasing Sampling." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5286.
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The objective of this thesis is to study the demodulation of narrowband radio frequency signals by aliasing sampling in order to reduce the sampling rate. The spectrum can be recreated at the lower frequency position by aliasing sampling. However, if the sampling rate is deviated from the desired one, error will occur. The sensitivity to the frequency error of aliasing sampling is studied. One main reason of the deviation of the sampling rate is the frequency drifting of the local oscillator. Being able to compensate the oscillator drifting errors inexpensively, automatic frequency control (AFC) loops are important at receivers. Two major digital AFC algorithms are studied. One is the Phase method AFC, and the other is the Magnitude method AFC. Study indicates that both methods perform almost equally well. One adaptive AFC algorithm is also proposed. The scheme of the adaptive AFC algorithm is to use Upper-bound and Lower-bound techniques to squeeze the frequency errors. It is shown that the adaptive AFC algorithm can achieve up to 20 dB average signal-to-noise power ratio over the Magnitude method AFC under a noisy environment.
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Yang, Runfeng. "Multiband orthogonal frequency division multiplexing modulation and demodulation for wireless universal serial bus." Thesis, University of Reading, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.499368.
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Wireless Universal Serial Bus (W-USB) has been proposed to offer a mechanism in short range and high speed Wireless Personal Area Networks (WPAN). Wireless USB has now been standardized by utilizing the common WiMedia Ultra Wideband (UWB) radio platform to use the services of Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) as the transport mechanism. With regards to the high data rate mode using DCM modulation scheme, different DCM demapping methods resulting in different system performance are presented, which include soft bit demapping, Maximum Likelihood (ML) soft bit demapping and I Log Likelihood Ratio (LLR) demapping. The proposed Channel State Information (CSl) aided scheme coupled with the band hopping information is used as the further technique to improve the DCM demapping performance.
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Raghu, Swathi. "Combinatorial Modulation and Coherent Demodulation of Bi-orthogonal M-ary Frequency Shift Keying." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1449108844.
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Ndovi, Lusungu. "Benefits to processor load for quadrature baseband versus radio frequency demodulation algorithms." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1946.
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Bax, Walter T. "Modulation and frequency synthesis for wireless digital radio." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0019/NQ48341.pdf.
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Bax, Walter T. (Walter Timothy) Carleton University Dissertation Engineering Electronics. "Modulation and frequency synthesis for wireless digital radio." Ottawa, 1999.
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Gendron, Paul John. "A comparison of digital beacon receiver frequency estimators." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-09292009-020307/.
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Doerr, Michael B., William H. Jr Hallidy, Gary B. McMillian, Lawrence W. Jr Burke, and Jonah N. Faust. "Digital FDM for the HSTSS DAC Program." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608712.
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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, NevadaThis paper presents the design of an innovative approach to Frequency Division Multiplexing (FDM) for the STRICOM Hardened Subminiature Telemetry and Sensor System (HSTSS) Data Acquisition Chipset (DAC) program. An ASIC (Application Specific Integrated Circuit) is being developed by Systems & Processes Engineering Corporation (SPEC) that implements this new digital FDM approach for telemetry applications. The FDM ASIC provides six channels that are IRIG-106 compatible, and may be used in conjunction with a Delay/Repeater ASIC. Together these ASICs make a complete instrumentation system for those applications requiring very small size, simplicity of use, and low cost, e.g. munitions/armament testing.
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Erdem, Erem. "Digital Modulation Recognition." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/12611281/index.pdf.
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In this thesis work, automatic recognition algorithms for digital modulated signals are surveyed.
Feature extraction and classification algorithm stages are the main parts of a modulation recognition system. Performance of the modulation recognition system mainly depends on the prior knowledge of some of the signal parameters, selection of the key features and classification algorithm selection.
Unfortunately, most of the features require some of the signal parameters such as carrier frequency, pulse shape, time of arrival, initial phase, symbol rate, signal to noise ratio, to be known or to be extracted. Thus, in this thesis, features which do not require prior knowledge of the signal parameters, such as the number of the peaks in the envelope histogram and the locations of these peaks, the number of peaks in the frequency histogram, higher order moments of the signal are considered. Particularly, symbol rate and signal to noise ratio estimation methods are surveyed. A method based on the cyclostationarity analysis is used for symbol rate estimation and a method based on the eigenvector decomposition is used for the estimation of signal to noise ratio. Also, estimated signal to noise ratio is used to improve the performance of the classification algorithm.
Two methods are proposed for modulation recognition:
1) Decision tree based method
2) Bayesian based classification method
A method to estimate the symbol rate and carrier frequency offset of minimum-shift keying (MSK) signal is also investigated.
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Cirineo, Tony, and Bob Troublefield. "STANDARD INTEROPERABLE DATALINK SYSTEM, ENGINEERING DEVELOPMENT MODEL." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/608398.
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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, NevadaThis paper describes an Engineering Development Model (EDM) for the Standard Interoperable Datalink System (SIDS). This EDM represents an attempt to design and build a programmable system that can be used to test and evaluate various aspects of a modern digital datalink. First, an investigation was started of commercial wireless components and standards that could be used to construct the SIDS datalink. This investigation lead to the construction of an engineering developmental model. This model presently consists of wire wrap and prototype circuits that implement many aspects of a modern digital datalink.
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Culha, Onur. "Noncoherent Differential Demodulation Of Cpm Signals With Joint Frequency Offset And Symbol Timing Estimation." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613729/index.pdf.
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In this thesis, noncoherent differential demodulation of CPM signals with joint
carrier frequency offset and symbol timing estimation is investigated. CPM is very
attractive for wireless communications owing to major properties: good spectral
efficiency and a constant envelope property. In order to demodulate the received
CPM signal differentially, the symbol timing and the carrier frequency offset have
to be estimated accurately. There are numerous methods developed for the
purpose. However, we have not encountered studies (which are based on autocorrelation
estimation and hence suitable for blind synchronization) that give
expectable performance for both M-ary and partial response signaling. Thus, in
this thesis we analyze a feedforward blind estimation scheme, which recovers the
symbol timing and the frequency offset of M-ary CPM signals and partial response
CPM signals. In addition, we surveyed low complexity symbol detection methods
for CPM signals. Reduced state Viterbi differential detector incorporated to the
joint frequency offset and symbol timing estimator is also examined. The
performance of the examined demodulator scheme is assessed for the AWGN
channel by computer simulations.
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Chopp, Philip. "Frequency-translating delta-sigma modulation for bandpass analog-to-digital conversion of high- frequency signals." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110454.
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A traditional heterodyne receiver downconverts its input signal to one or more intermediate frequencies (IFs) before digitizing it at baseband. In a digital-IF receiver, the input signal is digitized directly at an IF using a bandpass analog-to-digital converter (ADC). Accordingly, the digital-IF receiver replaces the image-reject mixers and baseband filters of a heterodyne receiver with accurate and effcient digital functions, and therefore provides greater potential for reconfigurability. In order to maximize the advantages of a digital-IF receiver, a common design objective is to position the bandpass ADC as close as possible to the antenna, and to operate on the input signal at a high IF.A bandpass ADC is effciently implemented using a delta-sigma modulator, which can provide high-resolution A/D (analog-to-digital) conversion over a relatively narrow band around an IF. In order to operate on high-IF signals, conventional bandpass delta-sigma modulators require high-frequency filters and high sampling rates, which can result in high sensitivity to circuit non-idealities and high power consumption. These disadvantages are addressed by the frequency-translating delta-sigma modulator, which uses downconversion mixing inside its delta-sigma loop to process high-IF signals using low sampling rates and primarily low-frequency filters.This thesis investigates frequency-translating delta-sigma modulators for direct A/D conversion of high-IF signals. It first analyses the system architecture and performance limitations of an existing type of frequency-translating delta-sigma modulator that is based on image-reject mixing. This analysis is supported by an initial study on the effect of timing errors in a conventional delta-sigma modulator. The thesis then introduces a novel frequency-translating delta-sigma modulator that is based on single-path mixing. The advantages of the presented single-path architecture are demonstrated using an experimental delta-sigma modulator.The experimental delta-sigma modulator is designed to digitize a 4 MHz input-signal band that is centred at an IF of 225 MHz. It uses a local oscillation signal with a frequency of 200 MHz to downconvert this input-signal band to an IF of 25 MHz inside its delta-sigma loop, and samples at 100 MHz. The experimental prototype was fabricated in a standard 65 nm CMOS process. It achieves a peak SNDR of 55 dB and a dynamic range of 57.5 dB, while consuming 13 mW from a 1-V power supply. It has a full-scale range of 700 mVp-p.Un recepteur heterodyne traditionnel transpose un signal en entree vers une ou plusieurs frequences intermediaires (FI) avant de le numeriser a la bande de base. Dans un recepteur numerique FI, le signal en entree est numerise directement a la frequence FI a l'aide d'un convertisseur analogique-numerique passe-bande. Par consequent, le recepteur numerique FI remplace les melangeurs de rejection d'image et les filtres a bande de base d'un recepteur heterodyne traditionnel par des fonctions numeriques precises et efficaces. De ce fait, le recepteur numerique FI offre plus de possibilites de reconfiguration. Afin de maximiser les avantages d'un recepteur numerique FI, un objectif de conception frequent consiste a placer le convertisseur analogique-numerique passe-bande aussi pres que possible de l'antenne et de numeriser le signal en entree a une frequence FI elevee.Un convertisseur analogique-numerique passe-bande peut etre realise efficacement en utilisant un modulateur delta-sigma. En effet, ce dernier procure une conversion A/N (analogique-numerique) a haute resolution sur une bande relativement restreinte centree autour d'une frequence FI. Afin de fonctionner sur des signaux a frequences FI elevees, les modulateurs delta-sigma passe-bande classiques requierent des filtres hautes-frequences et des frequences d'echantillonnage elevees, ce qui peut les rendre tres sensibles aux non-idealites du circuit et mener a une consommation electrique importante. Il est possible de remedier a ces inconvenients en utilisant un modulateur delta-sigma a transposition de frequence. En effet, ce dernier utilise des melangeurs dans sa boucle delta-sigma pour traiter des signaux a frequence FI elevee a des frequences d'echantillonnage faibles avec principalement des filtres basses-frequences.Cette these etudie l'utilisation de modulateurs delta-sigma a transposition de frequence pour une conversion A/N directe de signaux a frequence FI elevee. Elle analyse d'abord l'architecture et les limitations de performance d'un modulateur delta-sigma a transposition de frequence base sur un melangeur de rejection d'image. Cette analyse est appuyee par une etude initiale effectuee sur l'effet d'erreurs d'horloge sur un modulateur delta-sigma classique. Cette these introduit ensuite un nouveau modulateur delta-sigma a transposition de frequence base sur un melangeur de mono-trajet. Les avantages de cette architecture sont demontres a l'aide d'un prototype de modulateur delta-sigma.Le prototype de modulateur delta-sigma est concu afin de numeriser une bande de signaux en entree de 4 MHz centree autour d'une FI de 225 MHz. Il utilise un signal a oscillation locale d'une frequence de 200 MHz pour transposer cette bande de signaux en entree vers 25 MHz a l'interieur de sa boucle delta-sigma et effectue l'echantillonnage a 100 MHz. Ce prototype a ete realise en utilisant un procede CMOS standard de 65 nm. Il a un SNDR de 55 dB et une gamme dynamique de 57.5 dB tout en consommant 13 mW pour une alimentation de 1-V. Sa plage d'amplitude maximale est de 700 mVp-p.
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Geisinger, Nathan P. "Classification of digital modulation schemes using linear and nonlinear classifiers." Thesis, Monterey, California : Naval Postgraduate School, 2010. http://edocs.nps.edu/npspubs/scholarly/theses/2010/Mar/10Mar%5FGeisinger.pdf.
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Thesis (Electrical Engineer and M.S. in Electrical Engineering)--Naval Postgraduate School, March 2010.Thesis Advisor(s): Fargues, Monique P. ; Cristi, Roberto ; Robertson, Ralph C. "March 2010." Description based on title screen as viewed on .April 27, 2010. Author(s) subject terms: Blind Modulation Classification, Cumulants, Principal Component Analysis, Linear Discriminant Analysis, Kernel-based functions. Includes bibliographical references (p. 211-212). Also available in print.
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Tuthill, John D. "Frequency dependent digital compensation in DSP based FM modulators." Curtin University of Technology, Australian Telecommunications Research Institute, 2000. http://espace.library.curtin.edu.au:80/R/?func=dbin-jump-full&object_id=9787.
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This thesis reports original work on digital compensation for frequency dependent transfer characteristics and errors in digital PAM/CPFSK (Pulse Amplitude Modulation/Continuous Phase Frequency Shift Keying) quadrature modulators.A particularly flexible and cost effective approach to the implementation of the base-band section of a radio transmitter is to synthesise base-band signals digitally using a DSP (Digital Signal Processor). This approach is limited, however, by the transfer characteristics and errors in the implementation of practical analogue sub-systems. These practical limitations result in undesirable in-band frequency-dependent shaping of the transmitted signals. In the case of FM (Frequency Modulation) signals, this leads to the generation of unwanted side-lobes in the transmitted RF signal spectrum that interfere with signals in adjacent frequency channels. This results in the transmitted signal failing to meet transmission standards requirements.The digital compensation techniques developed and presented in this thesis allow the reduction of undesirable in-band frequency-dependent signal shaping. It is shown that this enables strict requirements on the spectral emissions from the FM transmitter to be met using a flexible and cost effective DSP based modulator system.The contributions of the thesis are in three primary areas:(i) The development of a structure for frequency dependent digital compensation.(ii) The formulation and solution of an optimisation problem that allows the free parameters within the structure to be determined such that effective reduction of unwanted in-band frequency-dependent signal shaping is achieved.(iii) The development of techniques that allow the digital compensation procedure to be successfully implemented on a practical DSP platform.The new digital compensation structure that is proposed uses two digital FIR (Finite ++Impulse Response) filters in the digital base-band section of the quadrature modulator: one in the in-phase (I) channel and one in the quadrature (Q) channel. The tap-weights of the FIR filters are determined by solving two optimisation problems: one for each channel. The optimisation problems are formulated using a new approach that ensures that the degrees of freedom in the optimisation i.e., the FIR filter tap-weights, are used effectively to meet the objective of reducing in-band frequency-dependent signal shaping in analogue sub-systems further down the transmission path.A characterisation of the solutions to the optimisation problems enables the identification of techniques that need to be adopted to successfully implement the proposed digital compensation on a practical DSP-based system.The digital compensation technique is demonstrated by implementing and testing the technique on a DSP platform. The results of experimental studies are presented which clearly demonstrate that the digital compensation technique leads to substantial reductions in adjacent channel interference.
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Franco, Marcelo Jorge Herczfeld Peter R. "Wideband digital predistortion linearization of radio frequency power amplifiers with memory /." Philadelphia, Pa. : Drexel University, 2005. http://dspace.library.drexel.edu/handle/1860/485.
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Oder, Stephen, Gelais Robert St, Peter Caron, and Douglas Bajgot. "Development of a Digital Potentiometer Circuit for Digital Compensation of Frequency and Temperature Variations of Kvco to Provide Reprogramming of the Transmitter RF Center Frequency in the Field." International Foundation for Telemetering, 2013. http://hdl.handle.net/10150/579704.
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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NVCobham Electronic Systems, Inc. has developed a digital potentiometer circuit to allow for digital compensation of frequency and temperature variations in the VCO/PLL frequency control loop of a telemetry transmitter. The ability to reprogram the RF center frequency of a telemetry transmitter is a useful feature and is required on many telemetry programs. When setting the frequency modulation deviation (FM Modulation Index) of a telemetry transmitter, the exact setting will change with RF center frequency due to the variation of the transfer function of the VCO (Kvco). Typically, a resistor divider is used to set the frequency modulation deviation level by setting the output data signal amplitude. However, since Kvco varies with respect to RF center frequency, a method of adjusting frequency modulation deviation for each frequency setting is required. The shunt resistor in the resistor divider is replaced with a digital potentiometer to provide the necessary adjustment, using the on-board microprocessor to store a look-up table of settings versus frequency. A key feature of the digital potentiometer circuit is a method to increase the frequency bandwidth of the potentiometer. Digital potentiometers typically have frequency bandwidths measured in kiloHertz to MegaHertz, which limits their use in setting the frequency modulation deviation of high data rate telemetry transmitters. The circuit consists of a 256 position digital potentiometer and several resistors that are used to adjust the slope of the resistance vs. digital code curve and to translate the curve up and down along the Y-Axis. Adding external resistors to the digital potentiometer helps to increase the frequency bandwidth of the digital potentiometer. The selection of the maximum resistance range of the digital potentiometer is also important, as the potentiometer bandwidth is greater when a small portion of the total resistance is used. This paper will explore various methods of increasing the effective bandwidth of a digital potentiometer, with the goal of making them suitable for use in dynamically setting the frequency modulation deviation via digital control.
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Rosenthal, Glenn K. "A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM." International Foundation for Telemetering, 1991. http://hdl.handle.net/10150/613103.
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International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, NevadaRecent advancements in high-speed Digital Signal Processing (DSP) concepts and devices permit digital hardware implementation of relatively high-frequency signal processing, which formerly required analog circuitry. Systems utilizing this technology can provide a high degree of software programmability; improved reproducibility, reliability, and maintainability; immunity to temperature induced drift errors; and compare favorably in cost to their analog counterparts. This paper describes the DSP implementation of a software programmable, digital frequency multiplexed FM system providing up to 4 output multiplexes, containing up to 36 subcarrier channels extending up to 4 MHZ, and accommodating modulating frequencies up to 64 kHz. System overall design goals and the implementation of these goals are presented.
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Heath, Mark Richard. "Investigation of envelope-shaped digital frequency modulation and its application to personal radio systems." Thesis, University of Leeds, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.277193.
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Hordeski, Theodore J. Jr. "TUNABLE FSK/AM SIGNAL DETECTOR ON A 6U-VME CARD." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609677.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaThe telemetry and aerospace communities require communications equipment providing various modulation and demodulation formats. One format, with application in Space Ground Link Subsystems (SGLS), utilizes a Ternary (tri-tone) Frequency Shift-Keyed (FSK) signal Amplitude Modulated (AM) by a triangle waveform. Historically, SGLS equipment has operated with a fixed tri-tone frequency set (e.g., 65 kHz, 76 kHz and 95 kHz). The need for additional transmission channels and increased bandwidth efficiency creates the requirement for equipment with the flexibility to generate and receive varied and higher frequency tone sets. Combining analog and digital techniques, GDP Space Systems has developed the FDT001. It is an FSK/AM detector which recovers a bit rate clock at one of four selectable bit rates and reproduces ternary FSK modulation data over a widely tunable range of tone frequencies. The tuning range is expanded by using two methods of digital frequency discrimination. The following paper describes the design of the FDT001.
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Wicomb, Lindsay Paul. "OFDM modulation techniques for domestic power line communication." Thesis, Cape Peninsula University of Technology, 2005. http://hdl.handle.net/20.500.11838/1083.
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Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2005With the growth of the personal computer industry, a number of households now contain two or more personal computers. The need to share resources such as printers, scanners and other PC peripherals has become evident. Communication between personal computers and other smart devices in the home is also required. This brings the emergence of home networking together with home automation. Home networking is the collection of elements to enable the connection and integration of multiple computing, control and communication devices. There are various options at this stage for home networking. One of the broadband options is indoor power line communication. The aim of the project was to evaluate a communication system capable of performing efficiently in South African Home Power line environment. In designing a communication system capable of performing in the harsh conditions which are presented in the home environment (noise, attenuation, phase distortion, etc.), a mathematical model that is representative of a typical suburban South African home power line is required. To aid the modeling process, an experimental network was constructed so measurements could be taken in a controlled environment. In conjunction with simulation, the model of the home power line network has aided the design of the data communication system. The project has involved: • Determining optimal specifications for the communication system. • Development of a home power line model representative of a typical South African suburban home environment. • Construction and measurement of an experimental power grid • Development of methods, algorithms and programs for the design of an OFDM PLC modem (in software) to optimal specifications. • Simulation development in MA1LAB of the OFDM Modem. • Comparison of different OFDM sub-modulation schemes for enhancing the communication system performance, In conclusion, the simulation model of the PLC modem correlates well with typical practical systems. Optimising throughput of the communication system and hardware development of the modem will form the basis for further research.
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Gray, Andrew, Meera Srinivasan, Marvin Simon, and Tsun-Yee Yan. "FLEXIBLE ALL-DIGITAL RECEIVER FOR BANDWIDTH EFFICIENT MODULATIONS." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608745.
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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, NevadaAn all-digital high data rate parallel receiver architecture developed jointly by Goddard Space Flight Center and the Jet Propulsion Laboratory is pre- sented. This receiver utilizes only a small number of high speed components along with a majority of lower speed components operating in a parallel fre- quency domain structure implementable in CMOS, and can process over 600 Mbps with numerous varieties of QPSK modulation, including those incorpo- rating precise pulse shaping for bandwidth eÆcient modulation. Performance results for this receiver for bandwidth eÆcient QPSK modulation schemes such as square-root raised cosine pulse shaped QPSK and Feher’s patented QPSK are presented, demonstrating the great degree of exibility and high performance of the receiver architecture.
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Marzolini, Remo G. A. "Demodulator techniques in satellite communications systems for direct broadcast systems." n.p, 1995. http://ethos.bl.uk/.
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Borkowski, M. (Maciej). "Digital Δ-Σ Modulation:variable modulus and tonal behaviour in a fixed-point digital environment." Doctoral thesis, University of Oulu, 2008. http://urn.fi/urn:isbn:9789514289101.
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Abstract
Digital delta-sigma modulators are used in a broad range of modern electronic sub-systems, including oversampled digital-to-analogue converters, class-D amplifiers and fractional-N frequency synthesizers.
This work addresses a well known problem of unwanted spurious tones in the modulator’s output spectrum. When a delta-sigma modulator works with a constant input, the output signal can be periodic, where short periods lead to strong deterministic tones. In this work we propose means for guaranteeing that the output period will never be shorter than a prescribed minimum value for all constant inputs. This allows a relationship to be formulated between the modulator’s bus width and the spurious-free range, thereby making it possible to trade output spectrum quality for hardware consumption.
The second problem addressed in this thesis is related to the finite accuracy of frequencies generated in delta-sigma fractional-N frequency synthesis. The synthesized frequencies are usually approximated with an accuracy that is dependent on the modulator’s bus width. We propose a solution which allows frequencies to be generated exactly and removes the problem of a constant phase drift. This solution, which is applicable to a broad range of digital delta-sigma modulator architectures, replaces the traditionally used truncation quantizer with a variable modulus quantizer. The modulus, provided by a separate input, defines the denominator of the rational output mean.
The thesis concludes with a practical example of a delta-sigma modulator used in a fractional-N frequency synthesizer designed to meet the strict accuracy requirements of a GSM base station transceiver. Here we optimize and compare a traditional modulator and a variable modulus design in order to minimize hardware consumption. The example illustrates the use made of the relationship between the spurious-free range and the modulator’s bus width, and the practical use of the variable modulus functionality.
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Boström, Henrik. "An FPGA implementation of a digital FM modulator." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70241.
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The increase in speed and density of programmable logic devices such as Field Programmable Gate Arrays (FPGA) enables ever more complex designs to be constructed within a short time frame. The flexibility of a programmable device eases the integration of a design with a wide variety of components on a single chip. Since Frequency Modulation (FM) is an analog modulation scheme, performing it in the digital domain introduces new challenges. The details of these challenges and how to deal with them are also explained. This thesis presents the design of a digital stereo FM modulator including necessary signal processing, such as filtering, waveform generation, stereo multiplexing etc. The solution is comprised of code written in Very high speed integrated circuit Hardware Description Language (VHDL) and a selection of free Intellectual Property (IP)-blocks and is intended for implementation on a Xilinx FPGA. The focus of the thesis lies on area efficiency and a number of suggestions are given to maximize the number of channels that can be modulated using a single FPGA chip. An estimation of how many channels that can be modulated usingthe provided FPGA, Xilinx XC6SXL100T, is also presented.
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Wisniewski, John W. "Implementation of multi-frequency modulation with trellis encoding and Viterbi decoding using a digital signal processing board." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/30967.
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Approved for public release, distribution unlimitedMulti-Frequency Modulation has been the topic of several papers at NPS. In past systems the majority of time required for the generation of the MFM signal was due to the software routine used to implement the FFT. In this report a Digital Signal Processor was used to reduce the time needed to generate the FFT. The use of Trellis coding and Viterbi decoding on a Digital Signal Processor was also investigated. Assembly language programs for three encoder/ decoder systems were developed. The first uses a 16 QAM signal, the second uses a 2/3 rate convolutional encoder and Viterbi decoder and the third uses the V.32 convolutional encoder and a Viterbi decoder.
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M, M. Galib Asadullah. "Robust wireless communications under co-channel interference and jamming." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22571.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Gordon L. Stuber; Committee Member: Alfred D. Andrew; Committee Member: John A. Buck; Committee Member: Steven W. McLaughlin; Committee Member: Ye (Geoffrey) Li.
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Franklin, Daniel Robert. "Enhancements to channel models, DMT modulation and coding for channels subject to impulsive noise." School of Electrical, Computer & Telecommunications Engineering - Faculty of Informatics, 2007. http://ro.uow.edu.au/theses/18.
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DMT modulation is an OFDM-based modulation scheme used in ADSL and proposed for various other high-speed broadband access systems. Existing mathematical models for transmission lines make a number of simplistic assumptions about the distribution of noise, in particular, the assumption that impulsive noise originates at either end of the transmission line. It is therefore desirable to improve the accuracy of the transmission-line model to allow better prediction of broadband modem performance, and to further improve the bit-allocation algorithms and equaliser designs used in DMT-based modems. This Thesis presents a new channel model particularly well-suited for simulation of high-speed digital subscriber line systems. The model extends a commonly-used physical channel model by distributing the points of noise ingress along the physical length of the transmission line. Simulation results are presented for a highspeed multicarrier modem operating on channels modelled with both the conventional and new models. Comparison with the same modem operating over a real channel demonstrates that the new model provides a better estimate of the bit error rates and temporal error distribution expected on actual telephone lines than is possible with the conventional model. A number of improvements to modulation and coding schemes for DMT modems are also presented in this Thesis, including a robust frequency-domain decision feedback equaliser, a new algorithm for allocating bits to sub-carriers based on a measurement of per-carrier BER, and a technique for encoding data with fractional numbers of bits ii Abstract iii per symbol, thereby providing additional channel capacity.
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Rim, Geun-hie. "Variable speed constant frequency power conversion with permanent magnet synchronous and switched reluctance generators." Diss., Virginia Tech, 1992. http://hdl.handle.net/10919/40015.
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Laha, Soumyasanta. "Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.
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Kothakapa, Vijayvardhan Reddy. "Investigation on the use of time-modulation technique for an ultra-wideband reader." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14982/.
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Ultra-wideband Technology is a trusted key for future generation radio frequency identification systems to conquer them as high as the limitations of the ongoing narrow bandwidth radio frequency identification technology like decreasing the space coverage, insufficient ranging resolution for accurate localization, sensitivity to interference, and multiple access capabilities.
The idea in practice is to apply the Time Modulation technique which means the presence of switches at the antenna ports, which is a new procedure, but typically adopted for narrowband antennas arrays. So, for the arrays working at a single frequency.
Here we are trying to see if it is possible to apply this excitation technique also to ultra-wideband antennas. So, in this case, instead of having two monopoles for instance as well as our application, we have used two Ultra-wideband antennas working in the lower European UWB band [3.1 – 4.8]GHz.
For single narrow band antennas, we see what it happens only at single band frequency. In this case, having UWB antennas, we must split our 2GHz band from 3 to 5GHz into windows of 500MHz.
This dissertation mainly focuses on the two important characteristics. They are: localization and power transmission both realized by the time modulated antenna array and evaluates their application in the communication system. The first step of experiment localization is carried out on a computer by using the software tool called Computer Simulation Technology (CST) in the range from 3GHz to 5GHz and then merging the results with a MATLAB programming to extract the far-field results and by using Nonlin software which was developed by the researchers of DEI: with this procedure we are able to evaluate the simulation results of far-field by taking into account all the possible phenomena, both linear and non-linear, taking place in the radiating system under test.
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Lee, Moonhyun. "Digital-Based Zero-Current Switching (ZCS) Control Schemes for Three-Level Boost Power-Factor Correction (PFC) Converter." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/99694.
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With the increasing demands on electronic loads (e.g. desktop, laptop, monitor, LED lighting and server) in modern technology-driven lives, performance of switched-mode power supply (SMPS) for electronics have been growing to prominence. As front-end converters in typical SMPS structure, ac-dc power-factor correction (PFC) circuits play a key role in regulations of input power factor, harmonics and dc output voltage, which has a decisive effect on entire power-supply performances. Universal ac-line and low-power system (90–264 Vrms, up to 300–400 W) is one of the most common power-supply specifications and boost-derived PFC topologies have been widely used for the purpose. In order to concurrently achieve high efficiency and low-cost system in the PFC stage, zero-current switching (ZCS) control schemes are highly employed in control principles. Representative schemes are discontinuous conduction mode (DCM) and critical conduction mode (CRM). Both modes can realize ZCS turn-on without diode reverse recovery so that low switching losses and low-cost diode utilizations are obtainable.
Among various boost-family PFC topologies, three-level boost (TLB) converter has generated considerable research interest in high-voltage high-power applications. It is mainly due to the fact that the topology can have halved component voltage stresses, improved waveform qualities and electromagnetic interference (EMI) from phase interleaved continuous conduction mode (CCM) operations, compared to other two-level boost PFC converters. On the other hand, in the field of universal-line low-power applications, TLB PFC has been thoroughly out of focus since doubled component counts and increased control complexity than two-level topologies are practical burden for the low-cost systems. However, recent researches on TLB PFC with ZCS control schemes have found that cost-competitiveness of the topology is actually comparable to two-level boost PFC converters because the halved component voltage stresses enable usage of low voltage-rating components of which unit prices are cheaper than higher-rating ones. Based on the justification, researches on ZCS control schemes for TLB PFC have been conducted to get enhanced waveform qualities and performance factors.
Following the research stream, a three-level current modulation scheme that can be adopted in both DCM and CRM is proposed in Chapter 2 of this dissertation. Main concept of the proposed current modulation is additional degree-of-freedom in current-slope shaping by differentiating on-times of two active switches, which cannot be found from any other single-phase boost-derived PFC topologies. Using the multilevel feature, proposed operations in one switching period consist of three steps: common-switch on-time, single-switch on-time and common-switch off-time. The single-switch on-time step is key design factor of the proposed modulation that can be utilized either in fixed or adjustable form depending on control purpose. Based on the basic modulation concept, three-level CRM control scheme, adjustable three-level DCM control scheme, and spread-spectrum frequency modulation (SSFM) with adjustable three-level DCM scheme are proposed in Chapter 3–5, respectively.
In each chapter, implemented control scheme aims to improve different performance factors. In Chapter 3, the proposed three-level CRM scheme uses increased single-switch on-time period to reduce peak inductor current and magnitude of variable switching frequency. It is generally accepted fact that CRM operations suffer from high switching losses and poor efficiency at light load due to considerable increment of switching frequency. Thus, efficiency improvement effect by the proposed CRM scheme becomes remarkable as load condition goes lighter. In experimental verifications, maximum improvement is measured by 1.2% at light load (20%) and overall efficiency is increased by at least 0.4% all over the load range. In Chapter 4, three-level DCM control scheme adopts adjustable single-switch on-time period in fixed switching-frequency framework. The purpose of adjustable control scheme is to widen the length of non-zero inductor current period as much as possible so that discontinued current period and high peak current of DCM operations can be minimized. Experiment results show that, compared to conventional two-level DCM control, full-load peak inductor currents are reduced by 20.2% and 17.1% at 110 and 220 Vrms input voltage conditions, respectively. Moreover, due to turn-off switching energy decrements by the turn-off current reductions, efficiency is also improved by at least 0.4% regardless of input voltage and load conditions. In Chapter 5, a downward SSFM technique is developed first for DCM operations of boosting PFC converters including two-level topologies. This chapter aims to achieve significant reduction of high differential-mode (DM) EMI amplitudes from DCM operations, which is major drawback of DCM control. By using the simple linearized frequency modulation, peak DM EMI noise at full load condition is reduced by 12.7 dBμV than conventional fixed-frequency DCM control. On top of the proposed SSFM, the adjustable three-level DCM control scheme in Chapter 4 is adopted to get further reductions of EMI noises. Experimental results prove that the collaborations of SSFM and adjustable DCM scheme reduce the EMI amplitudes further by 2.5 dBμV than the result of SSFM itself. The reduced EMI amplitudes are helpful to design input EMI filter with higher cut-off frequency and smaller size.
Different from two-level boosting PFC converters, TLB PFC topology has two output capacitors in series and inherently suffers from voltage unbalancing issue, which can be noted as topological trade-off. In Chapter 6, two simple but effective voltage balancing schemes are introduced. The balancing schemes can be easily built into the proposed ZCS control schemes in Chapter 3–5 and experimental results validate the effectiveness of the proposed balancing principles.
For all the proposed control schemes in this dissertation, detailed operation principles, derivation process of key equations, comparative analyses, implementation method with digital controller and experimental verifications with TLB PFC prototype are provided.Doctor of Philosophy
Electronic-based devices and loads have been essential parts of modern society founded on rapid advancements of information technologies. Along with the progress, power supplying and charging of electronic products become routinized in daily lives, but still remain critical requisites for reliable operations. In many power-electronics-based supplying systems, ac-dc power-factor correction (PFC) circuits are generally located at front-end to feed back-end loads from universal ac-line sources. Since PFC stages have a key role in regulating ac-side current quality and dc-side voltage control, the importance of PFC performances cannot be emphasized enough from entire system point of view. Thus, advanced control schemes for PFC converters have been developed in quantity to achieve efficient operations and competent power qualities such as high power factor, low harmonic distortions and low electromagnetic interferences (EMI) noises. In this dissertation, a sort of PFC topologies named three-level boost (TLB) converter is chosen for target topology. Based on inherent three-level waveform capability of the topology, multiple zero-current switching (ZCS) control schemes are proposed. Compared to many conventional two-level PFC topologies, TLB PFC can provide additional degree-of-freedom to current modulation. The increased control flexibility can realize improvements of various waveform qualities including peak current stress, switching frequency range, harmonics and EMI amplitude. From the experimental results in this dissertation, improvements of waveform qualities in TLB PFC with the proposed schemes are verified with comparison to two-level current control schemes; in terms of efficiency, the results show that TLB PFC with the proposed schemes can have similar converter efficiency with conventional two-level boost converter in spite of increased component counts in the topology. Further, the proposed three-level control schemes can be utilized in adjustable forms to accomplish different control objectives depending on system characteristics and applications. In each chapter of this dissertation, a novel control scheme is proposed and explained with details of operation principle, key equations and digital implementation method. All the effectiveness of proposals and analyses are validated by a proper set of experimental results with a TLB PFC prototype.
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Shaddock, Daniel Anthony, and Daniel Shaddock@jpl nasa gov. "Advanced Interferometry for Gravitational Wave Detection." The Australian National University. Faculty of Science, 2001. http://thesis.anu.edu.au./public/adt-ANU20020227.171850.
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In this thesis we investigate advanced techniques for the readout and control of various interferometers. In particular, we present experimental investigations of interferometer configurations and control techniques to be used in second generation interferometric gravitational wave detectors. We also present a new technique, tilt locking, for the readout and control of optical interferometers.
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We report the first experimental demonstration of a Sagnac interferometer with resonant sideband extraction (RSE). We measure the frequency response to modulation of the length of the arms and demonstrate an increase in signal bandwidth of by a factor of 6.5 compared to the Sagnac with arm cavities only. We compare Sagnac interferometers based on optical cavities with cavity-based Michelson interferometers and find that the Sagnac configuration has little overall advantage in a cavity-based system.
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A system for the control and signal extraction of a power recycled Michelson interferometer with RSE is presented. This control system employs a frontal modulation scheme requiring a phase modulated carrier field and a phase modulated subcarrier field. The system is capable of locking all 5 length degrees of freedom and allows the signal cavity to be detuned over the entire range of possibilities, in principle, whilst maintaining lock. We analytically investigate the modulation/demodulation techniques used to obtain these error signals, presenting an introductory explanation of single sideband modulation/demodulation and double demodulation.
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This control system is implemented on a benchtop prototype interferometer. We discuss technical problems associated with production of the input beam modulation components and present several solutions. Operation of the interferometer is demonstrated for a wide range of detunings. The frequency response of the interferometer is measured for various detuned points and we observe good agreement with theoretical predictions. The ability of the control system to maintain lock as the interferometer is detuned is experimentally demonstrated.
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Tilt locking, a new technique to obtain an error signal to lock a laser to an optical cavity, is presented. This technique produces an error signal by efficient measurement of the interference between the TEM00 and TEM10 modes. We perform experimental and theoretical comparisons with the widely used Pound-Drever-Hall (PDH) technique. We derive the quantum noise limit to the sensitivity of a measurement of the beam position, and using this result calculate the shot noise limited sensitivity of tilt locking. We show that tilt locking has a quantum efficiency of 80%, compared to 82% for the PDH technique.
We present experimental demonstrations of tilt locking in several applications including frequency stabilisation, continuous-wave second harmonic generation, and injection locking of a Nd:YAG slab laser. In each of these cases, we demonstrate that the performance of tilt locking is not the limiting factor of the lock stability, and show that it achieves similar performance to the PDH based system.
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Finally, we discuss how tilt locking can be effectively applied to two beam interferometers. We show experimentally how a two beam interferometer typically gives excellent isolation against errors arising from changes in the photodetector position, and experimentally demonstrate the use of tilt locking as a signal readout system for a Sagnac interferometer.
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Lahouli, Rihab. "Etude et conception de convertisseur analogique numérique large bande basé sur la modulation sigma delta." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0074/document.
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Les travaux de recherche de cette thèse de doctorat s’inscrivent dans le cadre de la conception d’unconvertisseur analogique-numérique (ADC, Analog-to-Digital Converter) large bande et à haute résolution afinde numériser plusieurs standards de communications sans fil. Il répond ainsi au concept de la radio logiciellerestreinte (SDR, Software Defined Radio). L’objectif visé est la reconfigurabilité par logiciel et l’intégrabilité envue d’un système radio multistandard. Les ADCs à sur-échantillonnage de type sigma-delta () s’avèrent debons candidats dans ce contexte de réception SDR multistandard en raison de leur précision accrue. Bien queleur bande passante soit réduite, il est possible de les utiliser dans une architecture en parallèle permettantd’élargir la bande passante. Nous nous proposons alors dans cette thèse de dimensionner et d’implanter unADC parallèle à décomposition fréquentielle (FBD) basé sur des modulateurs à temps-discret pour unrécepteur SDR supportant les standards E-GSM, UMTS et IEEE802.11a. La nouveauté dans l’architectureproposée est qu’il est programmable, la numérisation d’un signal issu d’un standard donné se réalise enactivant seulement les branches concernées de l’architecture parallèle avec des sous-bandes defonctionnement et une fréquence d’échantillonnage spécifiée. De plus, le partage fréquentiel des sous-bandesest non uniforme. Après validation du dimensionnement théorique par simulation, l’étage en bande de base aété dimensionné. Cette étude conduit à la définition d’un filtre anti-repliement passif unique d’ordre 6 et detype Butterworth, permettant l’élimination du circuit de contrôle de gain automatique (AGC). L’architectureFBD requière un traitement numérique permettant de combiner les signaux à la sortie des branches enparallèle pour reconstruire le signal de sortie finale. Un dimensionnement optimisé de cet étage numérique àbase de démodulation a été proposé. La synthèse de l’étage en bande de base a montré des problèmes destabilité des modulateurs . Pour y remédier, une solution basée sur la modification de la fonction detransfert du signal (STF) afin de filtrer les signaux hors bande d’intérêt par branche a été élaborée. Unediscontinuité de phase a été également constatée dans le signal de sortie reconstruit. Une solution deraccordement de phase a été proposée. L’étude analytique et la conception niveau système ont étécomplétées par une implantation de la reconstruction numérique de l’ADC parallèle. Deux flots de conceptionont été considérés, un associé au FPGA et l’autre indépendant de la cible choisie (VHDL standard).L’architecture proposée a été validée sur un FPGA Xilinx de type VIRTEX6. Une dynamique de 74 dB a étémesurée pour le cas d’étude UMTS, ce qui est compatible avec celle requise du standard UMTSThe work presented in this Ph.D. dissertation deals with the design of a wideband and accurate Analog-to-Digital Converter (ADC) able to digitize signals of different wireless communications standards. Thereby, itresponds to the Software Defined Radio concept (SDR). The purpose is reconfigurability by software andintegrability of the multistandard radio terminal. Oversampling (Sigma Delta) ADCs have been interestingcandidates in this context of multistandard SDR reception thanks to their high accuracy. Although they presentlimited operating bandwidth, it is possible to use them in a parallel architecture thus the bandwidth isextended. Therefore, we propose in this work the design and implementation of a parallel frequency banddecomposition ADC based on Discrete-time modulators in an SDR receiver handling E-GSM, UMTS andIEEE802.11a standard signals. The novelty of this proposed architecture is its programmability. Where,according to the selected standard digitization is made by activating only required branches are activated withspecified sub-bandwidths and sampling frequency. In addition the frequency division plan is non-uniform.After validation of the theoretical design by simulation, the overall baseband stage has been designed. Resultsof this study have led to a single passive 6th order Butterworth anti-aliasing filter (AAF) permitting theelimination of the automatic gain control circuit (AGC) which is an analog component. FBD architecturerequires digital processing able to recombine parallel branches outputs signals in order to reconstruct the finaloutput signal. An optimized design of this digital reconstruction signal stage has been proposed. Synthesis ofthe baseband stage has revealed modulators stability problems. To deal with this problem, a solution basedon non-unitary STF has been elaborated. Indeed, phase mismatches have been shown in the recombinedoutput signal and they have been corrected in the digital stage. Analytic study and system level design havebeen completed by an implementation of the parallel ADC digital reconstruction stage. Two design flows havebeen considered, one associated to the FPGA and another independent of the chosen target (standard VHDL).Proposed architecture has been validated using a VIRTEX6 FPGA Xilinx target. A dynamic range over 74 dB hasbeen measured for UMTS use case, which responds to the dynamic range required by this standard
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Thiebaut, Matthieu Jacques Andre. "Receptor super-regenetativo (900 MHz) implementado em tecnologia CMOS 0,35 'mu'm." [s.n.], 2006. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262030.
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Orientador: Carlos Alberto dos Reis FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-12T22:43:50Z (GMT). No. of bitstreams: 1 Thiebaut_MatthieuJacquesAndre_M.pdf: 11116037 bytes, checksum: 353c725fb0cc60a33445209f0ec29a81 (MD5) Previous issue date: 2006
Resumo: O objetivo deste trabalho é propor uma topologia de receptor adequada para atender as exigências de uma rede de sensores sem fio, onde baixo consumo e baixo custo de fabricação são fundamentais.A topologia escolhida foi a do receptor super-regenerativo realizado em tecnologia CMOS 0,35Km e operando em 900 MHz. O chip foi montado e testado numa placa de alumina junto com alguns componentes passivos externos (circuito tanque e adaptação de impedância) necessários para seu funcionamento. Uma sensibilidade de -82 dBm para uma taxa de erro binário (BER) inferior a 0,1% foi obtida com um sinal modulado tudo-ou-nada (On-Off keying, OOK) de 64 kbits/s. O consumo deste receptor foi de 2,5 mW para uma tensão de alimentação de 2V.
Abstract: The purpose of this work is to develop a radio receiver, which is suitable for application in wireless sensor networks. Among the essential requirements for one such radio are included low power, low cost and high sensitivity. The topology of a super-regenerative receiver to operate in 900MHz was chosen, since it complies with all these requirements in addition to being appropriate for integration. Samples of the developed radio receiver were fabricated in 0,35Km CMOS technology. Prototypes were assembled on alumina plate using a few additional external components as an alternative to evaluate the performance of the radio without being affected by the low quality of the passives L and C used in the tuning block (tank and matching circuit). Test results have shown that the developed receiver features sensitivity of -82 dBm for a bit error rate (BER) lower than 0,1% with an On-Off Keying modulated signal of 64 kbit/s. Measure power consumption has been 2,5 mW for a supply voltage of 2 V.
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Spáčil, Jan. "Komunikační systémy s digitálními modulacemi." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217453.
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The purpose of this semestral project is to explain the basic issues of simple digital modulations through the creation of simple digital modulations using direct digital synthesis. It begins with a short review of digital modulation theory and the theory about direct digital synthesis. All the technical documentation is attached, including schematics and boards of functional modulator.
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Kroupa, Martin. "Analýza změny zátěže asynchronního motoru z měření statorových proudů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221189.
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This thesis is focused on the evaluation of rotor dynamics of the induction machine, which can be used as a basis for online diagnosis of driven load in the future. It describes the problem of time varying loading torque at its impact to electromagnetic variables in induction machine. Followed by the possible ways of monitoring and diagnostic of loading torque using Fourier analysis on supply current.
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Richter, Raik. "Ein Beitrag zur Modellierung und Realisierung der direkten digitalen Frequenzsynthese." Doctoral thesis, [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=963112023.
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Richter, Raik. "Ein Beitrag zur Modellierung und Realisierung der direkten digitalen Frequenzsynthese." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2000. http://nbn-resolving.de/urn:nbn:de:swb:14-994337562500-99246.
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In der Dissertationsschrift wird ein neuartiges Konzept der Realisierung der Direkten Digitalen Frequenzsynthese (DDS) vorgestellt. Ausgehend von der analysierten Literatur werden das Wirkprinzip eines Standard-DDS-Synthesizer analysiert und Möglichkeiten zur Aufwandsreduktion untersucht. Ein neuartiger Ansatz zur Realisierung einer vollständig digitalen DDS ergibt sich in der Anwendung der Pulse-Output-DDS. Bei der Pulse-Output-DDS wird neben dem D/A-Wandler auch die Sinus-ROM-Tabelle aus dem prinzipiellen Aufbau der Standard-DDS entfernt. Ausgehend von einer derart modifizierten DDS-Struktur wird ein geeignetes DDS-Modell entwickelt, mit welchem alle auftretenden Synthesefehler systematisch erfaßt und bewertet werden können. Die gewonnenen Erkenntnisse über die prinzipbedingten Synthesefehler bilden die Grundlage für Erweiterungen der Pulse-Output-DDS mit deren Hilfe eine qualitative Verbesserung des synthetisierten Signals erreicht wird. Dabei steht vor allem die Anwendung von Verfahren der digitalen Signalverarbeitung im Vordergrund, die zu einer Verringerung bzw. Kompensation oder zu einer spektralen Veränderung des auftretenden DDS-Fehlersignals geeignet sind. Es werden die erreichbaren Verbesserungen, aber auch die theoretischen und praktischen Grenzen von folgenden Verfahren aufgezeigt: absolute Verringerung des DDS-Fehlersignals Dithering des DDS-Fehlersignals Rauschformung (Noise-Shaping) des Fehlersignalspektrums Insbesondere bei der Rauschformung werden unterschiedliche Ansätze untersucht und bewertet mit dem Ziel, ein optimales Verfahren für den Rauschformungsprozeß bei der Verwendung in einer Pulse-Output-DDS zu finden. Durch die echtzeitfähige Implementation eines erweiterten DDS-Systems in einem Standard-CMOS-Prozeß werden die gefundenen theoretischen Lösungen verifiziert.
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Thuries, Stéphane. "Conception et intégration d'un synthétiseur digital direct micro-onde en technologie silicium SiGe : C 0.25um." Toulouse 3, 2006. http://www.theses.fr/2006TOU30163.
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Cette thèse présente le travail effectué sur la conception d'un synthétiseur de fréquence entièrement numérique appelé Synthétiseur Digital Direct (DDS), dans la gamme micro-ondes, et en technologie BiCMOS SiGe. Ce DDS a pour objectif de se substituer aux synthèses de fréquences indirectes notamment basées sur des boucles à verrouillage de phase (PLL). Jusqu'à présent, le coût, la consommation, la surface d'intégration et la gamme de fréquences synthétisables des DDS étaient des facteurs limitants pour les applications du domaine micro-onde. Nous présentons dans cette thèse des techniques de conception en numérique hyperfréquence (logique ECL multi-niveaux, convertisseur numérique/analogique non-linéaire,. . . ) qui nous ont permis de repousser les limites évoquées et de concevoir les blocs élémentaires ainsi que le DDS complet, intégrés dans une technologie faible coût silicium et fonctionnant à haute fréquence tout en ayant une consommation réduite. Ainsi, la fréquence de fonctionnement du système final est de 6 GHz, sa résolution interne de 9-bits et sa consommation de seulement 308 mW. Ce travail démontre ainsi la faisabilité de DDS fonctionnant dans la gamme micro-onde compatibles avec les applications multimédias et télécommunications sans fil récentes (faible coût, agilité en fréquence, faible consommation, versatilité,. . . )Direct Digital Synthesizer (DDS) is a very versatile signal generation block, known to have many attractive characteristics among which: fast settling time, high frequency resolution, low phase noise, phase and frequency modulation capabilities, large bandwidth. . . All these features make DDS very attractive for modern microwave telecommunication systems. Although the principle of DDS has been known for many years, it did not get a dominant role in microwave communication systems due to its frequency limitation and high power consumption. A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. The DDS consists of a phase accumulator, a complementer, a digital-to-analog (D/A) converter and a bipolar differential pair. This paper discusses on the BiCMOS improvement design techniques used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop register. With this design, the power dissipation is reduced by 30 % over the usual four-levels series logic. The phase-to-amplitude conversion is completed through a bipolar differential pair instead of a ROM and/or complex computing circuit, providing significant saving in power consumption and die size. The circuit has been processed in a BiCMOS SiGe:C technology. The power consumption is 308 mW and it operates from a 2. 8 V supply
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Gunnam, Kiran Kumar. "A DSP embedded optical naviagtion system." Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969/13.
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Šrámek, Petr. "Implementace softwarového rádia do FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217786.
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The common objective of this project is implementation of software defined radio (SDR) into FPGA. The text contains review and comparison of several hardware concepts intended for SDRs implementation then the methods for digital implementation of various components of radios as the filters, mixers and others are mentioned. Part of the text introduces used hardware platform and describes software support for designing, simulations and implementation into hardware. Significant part of project describes complex of external hardware components as filter, amplifier and control panel designed and built within the project realization. But the main part of project demonstrates design of the software solution of radio receiver. There is specified architecture of radio for FM broadcast receiving, next the more complex systems with carrier recovery algorithm are presented. These systems are able to work with AM, BPSK and QPSK modulations. It is possible to implement all these receivers into hardware and verify their operation. The practical laboratory theme has been outlined within the project run.
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Kováč, Marek. "Digitální AM/FM vysílač." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-220601.
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This master thesis is focused on the theoretical description and practical implementation of software defined transmitter. The main aim of this thesis was made the prototype of software defined transmitter in FM band. Theoretical part is determined to description of basic parts of equipment and working principles to understand the basic principle of digital transmitters and define the appropriate component base for construction. Discussed are used types of A/D and D/A converters, blocks of digital signal processing and the roles, which these components performs. The second part is focused practical. Specified are suitable types of components and block diagram is proposed for following electrical connection and printed circuit board in Eagle program as a plug-in modul for developmental platform Arduino. The main point is program, which sets and controls the transmitter. Next important part is impedance match and antenna tuning, which is explain in practical part of thesis. The result is prototype of software defined transmitter compatible with Arduino Uno platform.
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Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.
Full textAbstract:
Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de forceAn atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system
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Chem, Pei-Hsiang, and 陳培祥. "Applying High Frequency Modulation to Reduce Crosstalk Between Multi-Sensors and Using FPGA to Perform Digital PGC Demodulation in Time-Division Multiplexing Interferometric Sensors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/52273952307042665244.
Full textAbstract:
碩士國立高雄師範大學
光電與通訊工程學系
102
If the extinction ratio of the optical pulse is low in the time division multiplexing of polarization insensitive fiber optic Michelson interferometric sensors, the sensor system will suffer the crosstalk and noise to degrade the performance. In addition to adjust the extinction ratio of the optical pulse, in this paper, we use a high-frequency current signal direct modulating the laser to generate high-frequency phase signals in the sensor system. As used herein, a laser, a high frequency modulation signal, time difference of the pulse wave and the interference of crosstalk will be moved to the high-frequency phase noise that can be reduced the phase noise caused by the sensor optical fiber arm and Rayleigh backscattering lead to reduce the phase noise of all the sensor system, but the main sensor signal is almost unaffected. In this paper, in order to verify this method can apply to the sensor systems, we add the third sensor to the system and compare to the previous two sensor systems as control, found that adding the third sensor can effectively reduce crosstalk between the number of sensors, the phase noise, total harmonic distortion, and effectively improve the PGC demodulation of the minimum phase detection sensitivity. In the part of this article, we use the FPGA digital signal processing for the technique of sensor PGC demodulation. We make the work of the original PGC demodulation by digital processing circuit instead of analog processing circuit with this technology. If interferometric fiber optic sensors use analog circuits for signal demodulation will be due to component aging and other factors lead to distortion , to do further sensor sensitivity normalization process and other signal processing are also more difficult and complicated.In the paper, PGC demodulation of digital system is mainly divided into digital signal conversion and signal processing. Through homemade circuit board (which includes analog to digital converter chip, digital to analog converter chip), we capture the analog signal into a digitized signal for digitizing signal processing. The demodulation signal processed by the digitization operation converts to an analog signal output through the chip. The mainly problem of PGC demodulation techniques in digital conversion circuitry is the signal definition between the state of the output signal ( "0" or "1" ) and the input signal ( "0" or "1" ) which associated with the judgment of logic. Digital signal consists of the FPGA-Xilinx processing program. The programming is composed of mathematical control components and logic control components and makes the MATLAB-Simulink program as Xilinx simulation tools. Finally, the integrated digital system must be given the clock of the ideal frequency separately for each chip according to job requirements, and deal with synchronization issues and inter- chip communication protocol to complete the digitization system.
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Yeh, Yu-Ching, and 葉又菁. "PSK Modulation/Demodulation Circuits and Frequency Synthesizer for mm-Wave Wireless Communication." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/71217059283073292684.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
99
In this thesis, four circuit systems which can be applied to mm-wave wireless communication are demonstrated. It includes a 5-Gb/s data rate and 5-GHz carrier rate differential binary phase-shift keying (DBPSK) modulator/demodulator set, a 40-GHz frequency synthesizer, and two W-band wireless transceivers. One of the transceivers utilizes binary phase-shift keying (BPSK) modulation and its carrier frequency is 84 GHz and the other extends to quadrature phase-shift keying (QPSK) modulation at 87 GHz. The 5-Gb/s data rate and 5-GHz carrier rate DBPSK modulator/demodulator set is implemented in 90-nm CMOS technology. It consists of a differential encoder, a BPSK modulator, and a demodulator which is realized with automatic delay-locked unit. It achieves bit error rate (BER) < 10^(-12) for 2^(31)-1 PRBS, and consumes 35 mW from 1.2-V supply. The chip area is 0.29 mm2. The 40-GHz frequency synthesizer is fabricated in 65-nm CMOS technology, providing the 20-GHz I/Q signals and 40-GHz local oscillator (LO) clock for 60-GHz wireless application. To coincide with the IEEE 802.15.3c standard, this frequency synthesizer is required to offer a wideband output (38.88 GHz ~ 43.20 GHz), so an 8-band voltage-controlled oscillator (VCO) with adaptive digital-controlled unit is applied. It achieves a locking range of 4.58 GHz, and the phase noise is 90.0 dBc/Hz at 1-MHz offset. The power consumption is 92 mW from 1.2-V supply (VCO from 1.6-V), and the chip area is 0.44 mm2. Finally, two fully-integrated BPSK and QPSK transceivers operating at W-band [carrier frequency = 84 GHz (BPSK), and 87 GHz (QPSK)] are presented. Including RF front-end, Costas-loop-based carrier and data recovery, and antenna assembly technique. The BPSK transceiver prototype achieves 4.5-Gb/s data link with BER < 10^(−9) while consuming 202 mW (Tx) and 125 mW (Rx) from a 1.2-V supply. For QPSK TRx, on the other hand, it achieves 3.5-Gb/s data link with BER < 10^(−11) while consuming 212 mW (Tx) and 166 mW (Rx) from a 1.2-V supply.
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Kandukuri, Ajay. "Non-data aided parametric based carrier frequency estimators for bursty GMSK communication systems." Thesis, 2003. http://hdl.handle.net/1957/29876.
Full textAbstract:
Estimating the carrier frequency from a modulated waveform is one of the most
important functions of a coherent signal receiver. Good performance and low bit
error rates are obtained by coherent demodulation. Therefore, exact knowledge of the
received signal carrier frequency is critical for communication systems. Also due to
the spectral crowding, a high probability of channel interference can be observed.
Under moderate carrier frequency offsets, data-aided estimators have been developed
which have a high accuracy of estimation. However, for high frequency offsets the
frequency estimator does not have the information of data or timing. In this thesis we
propose a parametric based carrier frequency estimation of GMSK, which has
improved performance over ad-hoc methods (delay and multiply) and has high
resolution capability.
In this thesis three methods are implemented over GMSK data to improve the
performance and their results compared with the standard delay and multiply
method. Two of these methods are parametric based estimators and one is a fast
frequency estimator. Parametric based estimators were chosen partly due to their
high resolution capabilities and mainly for their proven performance. Parametric
based estimators were seen to have high computational load, and hence an alternate
fast frequency estimator was implemented. The tradeoffs involved with respect to
computational load and performance were shown.
The contributions of this thesis include the verification of the validity of
applying a parametric based approach on GMSK data, and compare the
performances of parametric methods and fast frequency estimator. It is showii that
such an approach has a better performance compared to non-data aided ad-hoc delay.
and multiply methods. A closed loop configuration of the open loop parametric
methods is suggested in the end.Graduation date: 2004
Best scan available. Figures are light on the original.