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Relevant bibliographies by topics / Digital integrated circuit design / Dissertations / Theses

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Dissertations / Theses on the topic 'Digital integrated circuit design'

Author: Grafiati

Published: 4 June 2021

Last updated: 29 January 2023

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1

Baqueta, Jeferson José. "Evaluation of using MIGFET devices in digital integrated circuit design." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/164044.

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A diminuição das dimensões do transistor MOS tem sido a principal estratégia adotada para alcançar otimizações de desempenho na fabricação de circuitos integrados. Contudo, reduzir as dimensões dos transistores tem se tornado uma tarefa cada vez mais difícil de ser alcançada. Nesse contexto, vários esforços estão sendo feitos para encontrar dispositivos alternativos que permitam futuros avanços em relação à capacidade computacional. Entre as mais promissoras tecnologias emergentes estão os transistores de efeito de campo com múltiplos e independentes gates (MIGFETs). MIGFETs são dispositivos c

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2

Varelas, Theodoros Carleton University Dissertation Engineering Electrical. "A monolithic BiCMOS power amplifier for low power digital radio transmitter." Ottawa, 1992.

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3

Burns, Francis P. "Transformational reasoning applied to the high-level synthesis of digital systems." Thesis, University of Newcastle Upon Tyne, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316217.

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4

Matoglu, Erdem. "Statistical design, analysis, and diagnosis of digital systems and embedded RF circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-06072004-131249/unrestricted/matoglu%5Ferdem%5F200405%5Fphd.pdf.

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5

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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6

Haddadin, Baker. "Time domain space mapping optimization of digital interconnect circuits." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=116004.

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Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approxim

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7

Wemple, Ivan L. "Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/5944.

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8

Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuito

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9

Cho, Minki. "Design methodology to characterize and compensate for process and temperature variation in digital systems." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50148.

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The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migra

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10

Welbourn, Anthony David. "Design and implementation of gallium arsenide digital integrated circuits." Thesis, University of Edinburgh, 1988. http://hdl.handle.net/1842/11533.

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11

Sarmiento, Leon Mayra Susana. "Testing platform implementation and system integration for an active/passive imager system including readout circuit design." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 5.32 Mb., 170 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3220740.

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12

Garagate, C. "Simulation backplane : an integrated environment for mixed-mode simulation of multiple analogue, digital and behavioural circuit simulators." Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241981.

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13

Benavides, John A. (John Anthony). "Improving Digital Circuit Simulation: A Knowledge-Based Approach." Thesis, University of North Texas, 1989. https://digital.library.unt.edu/ark:/67531/metadc500480/.

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This project focuses on a prototype system architecture which integrates features of an event-driven gate-level simulator and features of the multiple expert system architecture, HEARSAY-II. Combining artificial intelligence and simulation techniques, a knowledge-based simulator was designed and constructed to model non-standard circuit behavior. This non-standard circuit behavior is amplified by advances in integrated circuit technology. Currently available digital circuit simulators can not simulate this behavior. Circuit designer expertise on behavioral phenomena is used in the expert syste

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14

Herbert, J. M. J. "Application of formal methods to digital system design." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.

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15

Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filter." Ohio University / OhioLINK, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183749814.

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16

Rahagude, Nikhil Prakash. "Integrated Enhancement of Testability and Diagnosability for Digital Circuits." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/35609.

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While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metr

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17

Kleeberger, Veit [Verfasser]. "Resilient Cross-Layer Design of Digital Integrated Circuits / Veit Kleeberger." München : Verlag Dr. Hut, 2015. http://d-nb.info/1067708855/34.

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18

Gazor, Mehdi (Seyed Mehdi). "Design for manufacturability with regular fabrics in digital integrated circuits." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34108.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 113-115).<br>Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. T

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19

Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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20

Kešner, Filip. "Design of Digital Circuits at Transistor Level." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236048.

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This work aims to design process of integrated circuits on the transistor level, specially using evolutionary algorithm. For this purpose it is necessary to choose reasonable level of abstraction during simulation, which is used for evaluation candidate solutions by fitness function. This simulation has to be fast enough to evaluate thousands of candidate solutions within seconds. This work discusses already used techniques for transistor level circuit design and it chooses useful parts for new design of faster and more reliable automated design process, which would be able to design complex l

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21

Pant, Pankaj. "Automated diagnosis of path delay faults in digital integrated circuits." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13556.

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22

Hilton, Clint Richard. "A Flexible Circuit-Switched Communication Network for FPGA-Based SOC Design." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd799.pdf.

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23

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expen

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24

Aktaran-Kalayci, Tüba. "Steady-state analyses variance estimation in simulations and dynamic pricing in service systems /." Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-08042006-130840/.

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Thesis (Ph. D.)--Industrial and Systems Engineering, Georgia Institute of Technology, 2007.<br>Dr. David M. Goldsman, Committee Co-Chair ; Dr. James R. Wilson, Committee Co-Chair ; Dr. Hayriye Ayhan, Committee Co-Chair ; Dr. Christos Alexopoulos, Committee Member ; Dr. Kwok Tsui, Committee Member.

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25

Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.

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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinati

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26

Palakurthi, Praveen Kumar. "Design of a low voltage analog to digital converter." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

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27

Lee, Hyung-Jin. "Digital CMOS Design for Ultra Wideband Communication Systems: from Circuit-Level Low Noise Amplifier Implementation to a System-Level Architecture." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26195.

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CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range

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28

Savaria, Yvon 1958. "The design of digital machines tolerant of soft errors /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=72058.

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This thesis deals primarily with the problem of soft-error tolerance in digital machines. The possible sources of soft errors are reviewed. It is shown that the significance of ionizing radiation increases with the scaling down of MOS technologies. The characteristics of electromagnetic interference sources are also discussed. After presenting the conventional methods of dealing with soft errors, a new approach to this problem is suggested. The new approach, called Soft-Error Filtering (SEF), consists of filtering every output of the logic before latching it, in such a way that a transient inj

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29

Egidos, Plaja Núria. "On the digital design and verification of pixel detector ASICs for fast timing applications and other fields of science." Doctoral thesis, Universitat de Barcelona, 2021. http://hdl.handle.net/10803/671794.

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La contribución principal de esta tesis consiste en el diseño, implementación y verificación, mediante el uso de herramientas digitales, de una red de distribución de reloj para FastICpix, un detector píxel híbrido capaz de procesar fotones individualmente. Esta red distribuye una referencia temporal de baja frecuencia (decenas de MHz) a la matriz de píxeles, un reloj para el mecanismo de etiquetado temporal de la llegada de fotones. FastICpix se adapta en área y tamaño de píxel para optimizar la captura de carga eléctrica según la aplicación, y proporciona una fina resolución temporal (10 psR

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30

Butzen, Paulo Francisco. "Aging aware design techniques and CMOS gate degradation estimative." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/61868.

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O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o cons

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31

Marble, William Joel. "Design and Analysis of Charge-Transfer Amplifiers for Low-Power Analog-to-Digital Converter Applications." BYU ScholarsArchive, 2004. https://scholarsarchive.byu.edu/etd/35.

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The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic model of the voltage

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32

Bavaresco, Simone. "On-silicon testbench for validation of soft logic cell libraries." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/14907.

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Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de map

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33

Espinosa, de los Monteros J. Ignacio G. T. "Design for manufacturing : performance characterization of digital VLSI systems using a statistical analysis/inference methodology /." Online version of thesis, 1993. http://hdl.handle.net/1850/11741.

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34

Jett, David B. "Selection of flip-flops for partial scan paths by use of a statistical testability measure." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-12302008-063234/.

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35

Chan, Hin-Tat. "VLSI design and implementation of UHF RFID reader digital baseband with mixed-signal channel select filtering receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHAN.

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36

Benites, Luis Alberto Contreras. "Automated design flow for applying triple modular redundancy in complex semi-custom digital integrated circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/181177.

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Os efeitos de radiação têm sido um dos problemas mais sérios em aplicações militares e espaciais. Mas eles também são uma preocupação crescente em tecnologias modernas, mesmo para aplicações comerciais no nível do solo. A proteção dos circuitos integrados contra os efeitos da radiação podem ser obtidos através do uso de processos de fabricação aprimorados e de estratégias em diferentes estágios do projeto do circuito. A técnica de TMR é bem conhecida e amplamente empregada para mascarar falhas únicas sem detectálas. No entanto, o projeto de circuitos TMR não é automatizado por ferramentas EDA

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37

Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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38

Brady, Philomena C. "Offset correction in flash ADCs using floating-gate circuits." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14832.

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39

Amar, Ahmed Abdel Hady [Verfasser], and Wolfram [Akademischer Betreuer] Glauert. "Design Methodology for Digital Integrated Circuits in OFET Technology / Ahmed Abdel Hady Amar. Betreuer: Wolfram Glauert." Erlangen : Universitätsbibliothek der Universität Erlangen-Nürnberg, 2012. http://d-nb.info/1023597594/34.

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40

Rachamadugu, Arun. "Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26603.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Laskar, Joy; Committee Member: Anderson, David; Committee Member: Cressler, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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41

Barazi, Yazan. "Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology." Thesis, Toulouse, INPT, 2020. http://www.theses.fr/2020INPT0091.

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Les transistors de puissance grands gaps tels que les MOSFETs SiC et HEMT GaN repoussent les compromis classiques en électronique de puissance. Brièvement, des gains significatifs ont été démontrés par les transistors SiC et GaN: meilleurs rendements, couplés à une augmentation des densités de puissance offertes par la montée en fréquence de découpage. Les MOSFET SiC à haute tension présentent des spécificités telles qu'une faible tenue en court-circuit (SC) par rapport aux IGBT Si et un oxyde de grille aminci, et une tension de commande rapprochée grillesource élevée. La polarisation négative

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42

al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.

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43

Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.

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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distri

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44

Zhao, Xin. "Reliable clock and power delivery network design for three-dimensional integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45881.

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The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-

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45

Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.

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46

Liu, Shaolong. "SAR ADCs Design and Calibration in Nano-scaled Technologies." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1073.

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The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Amon

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47

Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.

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48

Goshi, Sudheer. "Digital Fabric." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/115.

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Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links t

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49

Tang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.

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Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including s

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50

Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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