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Journal articles on the topic 'Digital integrated circuit design'

Author: Grafiati

Published: 4 June 2021

Last updated: 29 January 2023

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1

Jones, Simon. "Digital BiCMOS Integrated Circuit Design." Microprocessors and Microsystems 18, no. 1 (1994): 55. http://dx.doi.org/10.1016/0141-9331(94)90024-8.

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Zhang, Xiao Feng, Fo Chang Xie, Guo Wei Yang, and Wei Zhang. "The Transceiver Circuit Design of Digital Ultrasonic System." Advanced Materials Research 834-836 (October 2013): 968–73. http://dx.doi.org/10.4028/www.scientific.net/amr.834-836.968.

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This paper introduces the design process of the digital ultrasonic transmission circuit: echo receiving circuit and the echo signal regulate circuit. Among them, outside 500 V DC - DC module for high voltage power input, use non-tuned type circuit design ultrasonic transmission circuit ; Select high voltage fast recovery diode FR107 design echo receiving limiter circuit; Using ultra-high speed, low noise, low distortion of the integrated operational amplifier MAX4104ESA design preamplifier circuits and the band-pass filter circuits; Using linear decibels, low noise, wide bandwidth, high gain a

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Hatfield, John. "Book Review: Digital BiCMOS Integrated Circuit Design:." International Journal of Electrical Engineering & Education 32, no. 1 (1995): 86. http://dx.doi.org/10.1177/002072099503200112.

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more

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5

Chen, Xin. "Undergraduate Curriculum Development for Digital Integrated Circuit Design." Creative Education 03, no. 06 (2012): 856–58. http://dx.doi.org/10.4236/ce.2012.326128.

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Takai, Nobukazu. "Realization of a design-less system for analog integrated circuits." Impact 2020, no. 1 (2020): 9–11. http://dx.doi.org/10.21820/23987073.2020.1.9.

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The 21st century has given rise to a digital world which has significantly impacted on the ways in which humans go about their everyday lives. From being able to speak with whomever you want, whenever you want, wherever you are on your smartphone, to tapping away on your laptop, through to spending hours each day on the internet, the world we live in is firmly digital and it now shapes the way we experience life. When it comes to circuits, analog still has a hugely important role to play. Circuit designer Associate Professor Nobukazu Takai is leading a team of researchers who are applying mach

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Richelli, Anna. "Low-Voltage Integrated Circuits Design and Application." Electronics 10, no. 1 (2021): 89. http://dx.doi.org/10.3390/electronics10010089.

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One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]

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Huynh, Hai Au, Jeong-Min Jo, Wansoo Nah, and SoYoung Kim. "EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design." IEEE Transactions on Electromagnetic Compatibility 58, no. 5 (2016): 1629–41. http://dx.doi.org/10.1109/temc.2016.2561978.

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Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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Wu, Yi Fei, Zhi Hong Wang, and Qing Wei Chen. "A Novel Integrated Angle Measurement System." Applied Mechanics and Materials 373-375 (August 2013): 838–43. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.838.

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A novel integrated angle measurement system is proposed, which is based on CAN bus and can solve the problem that the traditional shaft angle measurement device is sensitive to disturbances and lack of network interface. The hardware circuits are designed based on the digital signal processor (DSP) TMS320F2812 and the resolver-to-digital converter (RDC) AD2S83. In addition, an adjustable frequency circuit based on Direct Digital Synthesizer (DDS) is designed to provide a precise reference signal. The software design is also introduced. The experimental results show that the angle measurement s

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Zheng, Yong Hong, Shi Liu Peng, and Hong Wei Wang. "Integrated Design of Detecting Circuit in Convection-Based Tilt Sensor." Applied Mechanics and Materials 602-605 (August 2014): 2752–55. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2752.

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Detecting circuit consists of both a sensing circuit and a compensating circuit. Using digital amplification and filtration, detected signals were input to SCM with high-accuracy data acquisition. SMC substituted for a sensing circuit and a compensating circuit, an integration of design of structure was achieved. Volume of sensor is diminished obviously. Simultaneously, zero drift is decreased under ensuring high sensitivity and resolution ratio. Integrated design also enlarges the range of work temperature, and reduces cost of products.

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Musa, Wahab, Sri Wahyuni Dali, and Ade Irawaty Tolago. "Design of Digital Parity Generator Layout Using 0.7 micron Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3550. http://dx.doi.org/10.11591/ijece.v8i5.pp3550-3559.

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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of

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Goswami, Neelaksha, and Satendra Singh. "Learning on Proposal and Optimization of Stumpy Influence CMOS Transconductance Operational Amplifier." RESEARCH REVIEW International Journal of Multidisciplinary 6, no. 12 (2021): 184–90. http://dx.doi.org/10.31305/rrijm.2021.v06.i12.028.

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Portable systems, such as wireless communication systems, laptops, smart phones, consumer electronics, and implanted medical devices, are in high demand in the rapidly expanding consumer market. When it comes to extending the running duration of these portable devices, low-power and low-voltage integrated circuits are used almost universally to achieve this. The design of an analogue integrated circuit with somewhat excellent processing characteristics, when compared to its digital equivalent, is a difficult undertaking, especially when it comes to applications requiring low voltage and low po

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Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades,

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Dosluoglu, Taner, and Martin MacDonald. "Circuit Design for Predictive Maintenance." Advances in Artificial Intelligence and Machine Learning 02, no. 04 (2022): 533–39. http://dx.doi.org/10.54364/aaiml.2022.1136.

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Industry 4.0 has become a driver for the entire manufacturing industry. Smart systems have enabled 30% productivity increases and predictive maintenance has been demonstrated to provide a 50% reduction in machine downtime. So far, the solution has been based on data analytics which has resulted in a proliferation of sensing technologies and infrastructure for data acquisition, transmission and processing. At the core of factory operation and automation are circuits that control and power factory equipment, innovative circuit design has the potential to address many system integration challenge

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Zhang, Chenhao, Yiming Zhang, Junxia Gao, and ZhongZheng Li. "High-temperature digital circuit design for fluxgate sensor." Journal of Physics: Conference Series 2196, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2196/1/012015.

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Abstract With the continuous development of integrated electronics and the increasing demand for downhole resource exploration, it has become important to develop a small size, high temperature resistant, high-performance digital fluxgate sensor. Due to the strict size limitation of downhole exploration equipment, some high-temperature devices are generally large in size and have a different performance of the same type of devices, so it is necessary to select the devices that meet the temperature requirements through high-temperature experiments. In this paper, by simplifying the circuit stru

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Feng, Chang Jiang, Bing Xue, and Ze Jian Zhang. "A Method for Analog Integrated Circuit Embedded Self-Test." Advanced Materials Research 816-817 (September 2013): 1069–72. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.1069.

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Aimed at the embedded analog integrated circuit chip, a research for the analog integrated circuit self-test is presented in this paper. As an embedded test system, one of the key factors is to minimize the resources occupation rate besides completing the test task. The principle of this study is to simplify the scale of the test circuit, in order to reduce the hardware cost of the analog integrated circuit performance test as much as possible. The idea is like this: sending the impulse signal as the excitation to the under test circuit and transforming its response signals into digital. Thus,

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Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

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Zhou, Duo. "Research on the Design Method of Self-Repairing Digital Integrated Circuit Based on Embryonic Cellular Array." Applied Mechanics and Materials 624 (August 2014): 401–4. http://dx.doi.org/10.4028/www.scientific.net/amm.624.401.

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A digital circuit with self-repairing characteristic based on embryonic cellular array, which attempts to draw inspiration from the biological process of ontogeny, to implement novel digital computing machines endowed with better hardware fault-tolerant capabilities is researched in this paper. The Self-repairing Digital Circuit (SDC) consists of the two-dimensional electronic cellular array, the SDC's structure and the self-repairing mechanism are expounded, and the design of the cellular circuit based on LUT (look-up table) is proposed. Then, a multiplication circuit is presented as an examp

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NICODIMUS, R. A. "Active Shield Circuit for Digital Noise Suppression in Mixed-Signal Integrated Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 2 (2005): 438–43. http://dx.doi.org/10.1093/ietfec/e88-a.2.438.

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21

Di, Xinpeng, Weiping Chen, and Xiaowei Liu. "A digital interface integration circuit design for high precision quartz-gyro." Modern Physics Letters B 33, no. 19 (2019): 1950222. http://dx.doi.org/10.1142/s0217984919502221.

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A design of digital application specific integrated circuit (ASIC) of quartz-gyro is proposed in this paper. The digital drive circuit with fast-start oscillation and digital detection circuit with low noise are adopted to implement the digital output of the main circuit node and high precision angular velocity detection. The interface circuit is fabricated in a standard 0.35 [Formula: see text]m CMOS technology and test result shows the angular random walk and zero stability are [Formula: see text]/[Formula: see text] and [Formula: see text]/h ([Formula: see text]), respectively. The bias-ins

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BAHL, INDER J. "MONOLITHIC MICROWAVE INTEGRATED CIRCUITS BASED ON GaAs MESFET TECHNOLOGY." International Journal of High Speed Electronics and Systems 06, no. 01 (1995): 91–124. http://dx.doi.org/10.1142/s0129156495000031.

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Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multi-function integrated circuits that advance the MMIC technology are described, including inte

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23

Qiao, Shi Quan, Xiu Qing Zhang, Meng Yang, and Shu Wang Chen. "Design of Digital Clock Based on SCM." Applied Mechanics and Materials 668-669 (October 2014): 822–25. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.822.

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The digital clock is the timing device by using of the digital circuit to implement the digital display for hours, minutes and seconds. Due to the development of the digital integrated circuit and the wide application of the quartz crystal oscillator, the accuracy of the digital clock is far more than the old clocks’. The control part of the design is SCM AT89C51, and the compiler environment is Keil. The software is developed with C language, and the simulation debugging is used Proteus. The digital clock is convenient to people’s production and life, and it expands the original time function

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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Kalambe, Jayu P., and Rajendra M. Patrikar. "Design of Microcantilever-Based Biosensor with Digital Feedback Control Circuit." Journal of Sensors 2012 (2012): 1–9. http://dx.doi.org/10.1155/2012/586429.

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This paper present the design of cantilever-based biosensors with new readout, which hold promises as fast and cheap “point of care” device as well as interesting research tools. The fabrication process and related issues of the cantilever based bio-sensor are discussed. Coventorware simulation is carried out to analyze the device behavior. A fully integrated control circuit has been designed to solve manufacturing challenge which will take care of positioning of the cantilever instead of creating nanometer gap between the electrodes. The control circuit will solve the manufacturing challenge

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Alexandru, Mihaela, Viorel Banu, Miguel Vellvehi, Philippe Godignon, and José Millán. "Design of Digital Electronics for High Temperature Using Basic Logic Gates Made of 4H-SiC MESFETs." Materials Science Forum 711 (January 2012): 104–8. http://dx.doi.org/10.4028/www.scientific.net/msf.711.104.

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– 4H-SiC MESFET transistors are very attractive devices for high temperature application and communications. The JFET and MESFET transistors have a promising potential for integrated circuits able to operate at high temperature and harsh radiation environments, due to the superior electrical, mechanical and chemical proprieties of 4H-SiC. Progresses in the manufacturing of high quality SiC substrates open the possibility to new circuit applications.

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Zhong Shengyou, 钟昇佑, 姚立斌 Yao Libin, 范明国 Fan Mingguo та 李正芬 Li Zhengfen. "1280 × 1024，10 μm数字红外焦平面读出电路设计（特邀）". Infrared and Laser Engineering 51, № 4 (2022): 20211113. http://dx.doi.org/10.3788/irla20211113.

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Trost, Andrej, Andrej Zemva, and Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design." International Journal of Electrical Engineering & Education 38, no. 4 (2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student project

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Yuan, J. S., and W. Kuang. "Teaching Asynchronous Design in Digital Integrated Circuits." IEEE Transactions on Education 47, no. 3 (2004): 397–404. http://dx.doi.org/10.1109/te.2004.825923.

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YEO, KIAT-SENG, ZHI-HUI KONG, NUKALA NISHANT, HAITAO FU, and WEI ZENG. "INTEGRATED CIRCUIT DESIGN RESEARCH RANKING FOR WORLDWIDE UNIVERSITIES." Journal of Circuits, Systems and Computers 17, no. 01 (2008): 141–67. http://dx.doi.org/10.1142/s0218126608004204.

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The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at

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Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the paral

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Makihata, Mitsutoshi, Masanori Muroyama, Shuji Tanaka, Takahiro Nakayama, Yutaka Nonomura, and Masayoshi Esashi. "Design and Fabrication Technology of Low Profile Tactile Sensor with Digital Interface for Whole Body Robot Skin." Sensors 18, no. 7 (2018): 2374. http://dx.doi.org/10.3390/s18072374.

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Covering a whole surface of a robot with tiny sensors which can measure local pressure and transmit the data through a network is an ideal solution to give an artificial skin to robots to improve a capability of action and safety. The crucial technological barrier is to package force sensor and communication function in a small volume. In this paper, we propose the novel device structure based on a wafer bonding technology to integrate and package capacitive force sensor using silicon diaphragm and an integrated circuit separately manufactured. Unique fabrication processes are developed, such

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Chu, Kai-Chun, Kuo-Chi Chang, Hsiao-Chuan Wang, Yuh-Chung Lin, and Tsui-Lien Hsu. "Field-Programmable Gate Array-Based Hardware Design of Optical Fiber Transducer Integrated Platform." Journal of Nanoelectronics and Optoelectronics 15, no. 5 (2020): 663–71. http://dx.doi.org/10.1166/jno.2020.2835.

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This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of s

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Dong, Xinhang, Boyuan Jing, and Xiang Yang. "Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder." Journal of Physics: Conference Series 2113, no. 1 (2021): 012043. http://dx.doi.org/10.1088/1742-6596/2113/1/012043.

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Abstract 4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain

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Zolotorevich, L. A., and V. A. Ilyinkov. "Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures." Informatics 18, no. 3 (2021): 7–17. http://dx.doi.org/10.37661/1816-0301-2021-18-3-7-17.

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Integrated circuits, systems on a chip are the key links in various industrial systems and state defense systems. The emergence of counterfeit integrated circuits, problems of piracy, overproduction, unauthorized interference in the design of microcircuit, hardware Trojans require the development of methods and means of their timely detection. Trojans can be introduced into the integrated circuits structure both on the development stage and during the production process, including the stages of specification, design, verification and manufacturing. The inclusion of additional elements in the i

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Fasig, Jonathan, Gregory Rash, Barbara Randall, et al. "Interconnect Analysis for 80-Gbps Serial Link Design." Journal of Microelectronics and Electronic Packaging 5, no. 3 (2008): 135–39. http://dx.doi.org/10.4071/1551-4897-5.3.135.

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This paper presents a case study of the modeling and simulation methods used to design the signal path for a proposed 80-Gbps serial data link between digital systems. This design includes flip-chip transitions from custom IBM 8HP integrated circuits to multilayer organic substrates, with coaxial-cable connections between substrates. Discussion topics include interconnect material selection, detailed 3-D electromagnetic modeling of the conductor transitions and signal paths, time-domain circuit simulation of the complete data path including the driver and receiver, and bit-error rate analysis

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Parandin, Fariborz, Saeed Olyaee, Reza Kamarian, and Mohamadreza Jomour. "Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals." Photonics 9, no. 7 (2022): 459. http://dx.doi.org/10.3390/photonics9070459.

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An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits, and they are structures with alternating refractive indices. In this paper, an optical comparator is designed and simulated based on a square lattice photonic crystal. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a high difference between logical values “0” and “1”, which are defined based on the optical power level. Due to t

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Vahabi, Mohsen, Ali Newaz Bahar, Akira Otsuki, and Khan A. Wahid. "Ultra-Low-Cost Design of Ripple Carry Adder to Design Nanoelectronics in QCA Nanotechnology." Electronics 11, no. 15 (2022): 2320. http://dx.doi.org/10.3390/electronics11152320.

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Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA

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Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.

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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical

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Shang, Xin Juan, and Quan Jing Wang. "The Design of New-Type Digital Readout Device by Inductosyn." Advanced Materials Research 909 (March 2014): 439–43. http://dx.doi.org/10.4028/www.scientific.net/amr.909.439.

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The paper introduces the operation principle and system structure of intelligence digital readout system by inductosyn. The system adopts integrated subdivision circuit on the basis of AD2S90 and QA740210 and is controlled by MCU. It adopts phase demodulation mode, with functions of multipoint preset, power-fail protect, absolute origin setting, software error compensation, LCD display and so on, except simple PLC function and standard RS485 communication interface.

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Floros, George, and Athanasios Tziouvaras. "Special Issue “Smart IC Design and Sensing Technologies”." Chips 1, no. 3 (2022): 172–74. http://dx.doi.org/10.3390/chips1030011.

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Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, from IoT applications to complicated medical devices. Moreover, circuit implementation, which could be based on a full analog or digital approach or, in most cases, on a mixed-signal approach, possesses a fundamental role in exploiting the full capabilities of sensing technol

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Hao, Yilong, Yongchun Lou, Wenguo Hou, Xiaolong Chen, and Lu Niu. "Design of BLDCM servo controller based on TMS320F28377D." Journal of Physics: Conference Series 2359, no. 1 (2022): 012002. http://dx.doi.org/10.1088/1742-6596/2359/1/012002.

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Abstract To meet the application requirements of high-precision and fast-response thrust vector control from a solid rocket motor, a digital and integrated servo controller for four brushless direct current motors was designed and implemented. The controller hardware system proposed in this paper includes control circuit module and drive circuit module. The former mainly includes power conversion circuit, DSP system circuit, A/D circuit, SPI communication interface circuit, and SCI communication interface circuit. The later mainly includes three-phase full-bridge six-arm drive circuit and opto

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Kim, TaeWoong, and SoYoung Kim. "Electronic design automation requirements for R2R printing foundry." Flexible and Printed Electronics 7, no. 1 (2022): 013001. http://dx.doi.org/10.1088/2058-8585/ac4d3d.

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Abstract Roll-to-roll (R2R) printed electronic devices have been in the spotlight over the decades as a potential replacement for Si-based semiconductors, research into this technology is still being actively conducted over the world. These printed electronic devices can be used in a variety of applications, so the demand for them is expected to reach over USD 20.7 billion in 2025 given a compound annual growth rate (CAGR) of 21.5%. As the new ink materials and printing technologies being researched are commercialized, foundry companies that produce printed electronics need to provide appropri

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Chen, Shih-Lun, Yu-Kuen Lai, Wei-Chih Hu, and Wen-Yaw Chung. "Case-Based Instruction in Digital Integrated Circuit Design Courses for Non-Major Students." International Journal of Electrical Engineering & Education 51, no. 3 (2014): 232–44. http://dx.doi.org/10.7227/ijeee.51.3.5.

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AL-KARAWY, SALEH M., TARIK AL-BALDAWI, and D. S. CHITORE. "Design and implemenation of a tester for digital and linear integrated-circuit chips." International Journal of Electronics 66, no. 6 (1989): 921–28. http://dx.doi.org/10.1080/00207218908925448.

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Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.

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Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce th

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Beniwal, Ruby, and Shruti Kalra. "ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design." Journal of Integrated Circuits and Systems 16, no. 3 (2022): 1–10. http://dx.doi.org/10.29292/jics.v16i3.507.

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In this paper, the use of the Adaptive Neuro Fuzzy Inference System (ANFIS) to model the CMOS inverter is discussed as a tool for developing and simulating CMOS logic circuits at the ultradeep submicron technology node of 22nm. The ANFIS structures are built and trained using MATLAB software. The ANFIS network was trained using data obtained from the analytical model (at 298.15K and 398.15K). For training, two methodologies are used: a hybrid learning method based on back-propagation and least-squares estimation, and back-propagation. The effect of the ANFIS model's structure on the accuracy a

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Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (2000): 107–13. http://dx.doi.org/10.1155/2000/52658.

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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of suppl

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Ammes, Gabriel, Paulo Francisco Butzen, André Inácio Reis, and Renato Ribas. "Two-Level and Multilevel Approximate Logic Synthesis." Journal of Integrated Circuits and Systems 17, no. 3 (2023): 1–14. http://dx.doi.org/10.29292/jics.v17i3.661.

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Approximate computing represents a modern design paradigm that allows systems to have imprecise or inexact execution, aiming to optimize circuit area, performance, and power dissipation. The automatic construction of approximate integrated circuits (IC) is performed through computer-aided design (CAD) tools available in electronic design automation (EDA) frameworks. Approximate logic synthesis (ALS), in particular, treats two-level and multilevel topologies of combinational blocks in the development of digital IC design. This work provides a survey of ALS methods presented in the literature, f

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Tiri, K., and I. Verbauwhede. "A digital design flow for secure integrated circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 7 (2006): 1197–208. http://dx.doi.org/10.1109/tcad.2005.855939.

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