Dissertations / Theses on the topic 'Digital Receiver Design'

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada
In this paper, we propose a receiver design for satellite ground station use which can demodulate a waveform without specific knowledge of the data rate, convolutional code rate, or line code used. Several assumptions, consistent with the Space Network operating environment, are made including only certain data rates, convolutional code rates and generator polynomials, and types of line encoders. Despite the assumptions, a wide class of digital signaling (covering most of what might be seen at a ground station receiver) is captured. The approach uses standard signal processing techniques to identify data rate and line encoder class and a look up table with coded sync words (a standard feature of telemetry data frame header) in order to identify the key parameters. As our research has shown, the leading bits of the received coded frame can be used to uniquely identify the parameters. With proper identification, a basic receiver autoconfiguration sequence (date rate, line decoder, convolutional decoder) may be constructed.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada
High dynamic and multi-channel digital GPS receiver can handle the signals with high dynamic range, low S/N ratio and refresh data quickly. A hardware design of high dynamic GPS digital receiver is given. Based on analysis of the effect that high dynamic movement makes on the receiving signals, a scheme of fast-acquisition high dynamic GPS receiver is presented. Exact reckoning of the orbit parameters and the satellite clock parameters are integrated with appropriate algorithms. A DDLL is used to precisely estimate the C/A code delay, a CPAFC loop and a Costas loop to precisely estimate the carrier frequency and phase. The DDLL is assisted with carrier phase. The experimental results show that the receiver meets the design request.

Media extenders or digital media receivers are network devices that are used to retrieve digital media files (such as music, pictures, or video) from a media server and play or show them on a TV or home theater system. A technology that is often associated with these devices is the Universal Plug and Play (UPnP) technology. This technology enables network devices to be used without requiring the user to do network configuration on it. This thesis demonstrates how a device that is normally used for receiving digital television broadcasts can be enhanced to support media extender functionality. The thesis describes the design and implementation of the technologies that are needed to accomplish this functionality. The main topics are centered around on how UPnP awareness and media rendering (decoding) are incorporated into the device.

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.

The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).

The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.

A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.

When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.

The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

Thesis (Ph. D.)--University of Missouri-Columbia, 2005.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (July 19, 2006) Vita. Includes bibliographical references.

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

In cellular and personal communications services (PCS) systems based on code division multiple access (CDMA), a pilot signal is used on the forward link for synchronization, coherent detection, soft handoff, maintaining orthogonality between base stations, and, in the future, position location. It is critical that the percentage of power allocated to the pilot signal transmitted by each base station be fixed properly to ensure the ability of the CDMA network to support subscriber demand.

This thesis reports on the design and implementation of a prototype receiver for measuring pilot signals in CDMA PCS systems. Since the pseudonoise (PN) signal of the pilot channel is a priori information, the receiver searches for pilot signals by digitally correlating the received signal with this known, locally generated pilot signal. By systematically changing the phase of this locally generated pilot signal, the receiver scans the received signal to identify all possible signs of pilot signal activity. Large values of correlation indicate the presence of a pilot signal at the particular phase of the locally generated pilot signal. The receiver can also detect multipath components of the pilot signal transmitted from a given base station.

One issue associated with this receiver is its ability to keep the signal power within the dynamic range of the analog-to-digital (A/D) converter at its input. This necessitated the design of an automatic gain control (AGC) mechanism, which is digitally implemented in this receiver.

Simulation studies were undertaken to assist in the design and implementation of the pilot signal scanning receiver. These simulations were used to quantify how various non-idealities related to the radio frequency (RF) front-end and A/D converter adversely affect the ability of the digital signal processing algorithms to detect and measure pilot signals.

Because the period of the pilot signal is relatively long, methods were developed to keep the receiver's update period as small as possible without compromising its detection ability. Furthermore, the high sampling rate required strains the ability of the digital logic to produce outputs at a rate commensurate with real-time operation. This thesis presents techniques that allow the pilot signal scanning receiver to achieve real-time operation. These techniques involve the judicious use of partial correlations and windowing the received signal to decrease the transfer rate from the A/D converter to the digital signal processor. This thesis provides a comprehensive discussion of these and other issues associated with the actual hardware implementation of the pilot signal scanning receiver.
Master of Science

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992.
1 ill. in back pocket. Vita. Abstract. Includes bibliographical references (leaves 224-228). Also available via the Internet.

Global Navigation Satellite Systems (GNSS) have been in the center stage of the recent technological upheaval that has been initiated by the rise of smartphones in the last decade. This is clearly reflected in the development of many applications based on GNSS technology as well as the emergence of multi-constellation GNSS with the launch of the first Galileo satellites at the end of the year 2011. GNSS does not only guarantee global positioning, navigation and timing services but also extends to applications in banking, agriculture, mapping, surveying, archaeology, seismology, commerce, ionosphere scintillation monitoring, remote sensing (soil moisture, ocean salinity, type of surface), wind speed monitoring, ocean surface monitoring, altimetry and many others. In the last decade, Location Based Services (LBS) have increased significant market demand where GNSS has been coupled with technologies based on terrestrial communication links in order to meet strict positioning accuracy requirements. In these conditions, relying on GNSS technology alone, raises a few challenges for signal synchronization even before positioning attempts and are mainly due to a considerable signal attenuation as it propagates through construction material and into indoor environments. Ionosphere scintillation induces a similar challenge where in addition to amplitude fading, the carrier phase and frequency suffer from indeterministic fluctuations. This research activity is devoted to explore and design the elements constituting pilot channel scalar tracking loop systems, specifically tailored to Galileo signals. It is expected that running such systems with extended integration intervals offers robust synchronization of the incoming signal which is heavily affected by external indeterministic fluctuations. In some conditions, it is desired to follow these fluctuations as in ionosphere scintillation monitoring while in other instances it is mainly desired to filter them out as noise to guarantee positioning capabilities. This is the objective of this research study which applies for both indoor environments and ionosphere scintillation affected signals. Towards this endeavor, a comprehensive theoretical study of the carrier and code tracking loops elements is undertaken, and particular attention is directed to the following aspects: • carrier frequency and phase discriminators and the relative optimum integration time • Galileo specific code discriminators and code tracking architecture especially tailored to Composite Binary Offset Carrier (CBOC) modulated signals. • optimum loop filters designed in the digital domain for different types of phase input signals • local signal generation using a numerically controlled oscillator and loop filter estimates • front-end filter bandlimiting effects on the tracking performance. This design is further tested with simulated Galileo signals with and without ionosphere scintillation as well as raw Galileo signals in an equatorial region during March 2013. Tracking performance comparison is carried out between the customized Galileo receiver developed in this research activity and an ionosphere scintillation dedicated professional GNSS receiver, the Septentrio PolaRxS PRO R receiver.

Due to the current research needs and the lack of commercial multi-channel, multi-constellation GNSS receivers, a two-board solution has been developed so it can be mated with and take advantage of the processing power of the FPGA board branded as MicroZed. In order to achieve the proposed goals, an initial phase for assessing and updating the older design, building, and testing of SiGe modules (including both the electronics and casings) has been carried out. The results included demonstrate performances at logging GPS-L1 data with similar C/N0 and AGC values as the previous versions of the modules and offering navigation solutions with accuracies of a few meters. Secondly, a first iteration and design proposal for the new generation receiver has been proposed for GPS and GLONASS L1 and L2, which has been manufactured and tested. Partial tests have been performed due to the flaws of the current revision of the MicroZed Board in regards to its communication peripherals, and the results have validated the receiver’s design provided certain modifications are considered for future iterations. Furthermore, voltage and frequency tests have provided results with an error of less than 7%, and signal tests have provided C/N0 values similar to those of the SiGe modules of around 47[dB-Hz] which will be a useful baseline for future iterations. Finally, a design proposal for an Interface Board used between the older NT1065_PMOD Board and other FPGA boards carrying the standardized FMC connectors has been added to the report and negotiations with manufacturers have been engaged.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Ma, Xiaoli; Committee Member: Anderson, David; Committee Member: Barry, John; Committee Member: Chen, Xu-Yan; Committee Member: Kornegay, Kevin. Part of the SMARTech Electronic Thesis and Dissertation Collection.

CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range of 3 GHz to 10 GHz, which is not feasible for existing CMOS analog-to-digital converters. In this dissertation, we investigate the two technical challenges at the circuit level and the system level. We propose a systematic approach at the circuit level for optimal transistor sizing and biasing conditions that result in optimal noise and power matching over a wide bandwidth. We also propose a general scheme for wideband matching. To verify our methods, we design two single-stage low noise amplifiers (LNAs) in TSMC 0.18µm CMOS technology. Measurement results from fabricated chips indicate that the proposed LNAs could achieve as high as 16 dB power gain and as low as 2.2 dB noise figure with only 6.4 mA current dissipation under a supply voltage of 1.2 V. At the system level, we propose a unique frequency domain receiver architecture. The receiver samples frequency components of a received signal rather than the traditional approach of sampling a received signal at discrete instances in time. The frequency domain sampling leads to a simple RF front-end architecture that directly samples an RF signal without the need to downconvert it into a baseband signal. Further, our approach significantly reduces the sampling rate to the pulse repetition rate. We investigate a simple, low-power implementation of the frequency domain sampler with 1-bit ADCs. Simulation results show that the proposed frequency-domain UWB receiver significantly outperforms a conventional analog correlator. A digital UWB receiver can be implemented efficiently in CMOS with the proposed LNA as an RF front-end, followed by the frequency domain sampler.
Ph. D.

The large demand for high-bandwidth communication systems has brought down the cost of optical system components. To be competitive in a crowded market, implementation of the different systems of an optical transceiver on a single chip has become mandatory.
CMOS technologies, especially state-of-the-art processes like the 0.18mum CMOS, permit integration of huge amounts of transistors per millimeter square. Furthermore, deep-submicron CMOS processes have similar RF performances to their traditional bipolar equivalent. It is therefore a small footstep to go to congregate high-speed analog circuits with digital cores on a single die.
This thesis addresses two of the building blocks found in an optical communication receiver, namely the analog front-end receiver and a digital frequency-acquisition based clock-and-data recovery circuit. The latter reduces the headcount of bulky passive components needed in the implementation of the loop filter by porting the analog loop to the digital domain. This circuit has been successfully fabricated and tested.
Finally, an optical front-end, comprising a transimpedance amplifier and a limiting amplifier is proposed and fabricated using a standard 0.18mum CMOS process. The speed of this circuit has been pushed up to 5Gb/s. Different techniques have been employed to increase the effective bandwidth of the input amplifier, namely the use of a constant-k filter.

The inherent broadcast nature of satellites, their global coverage and direct access to a large number of subscribers give satellites unrivalled advantages in supporting IP multicast applications. A new generation of satellite systems that support regenerative on-board processors and multiple spot beam technology have opened new possibilities of implementing IP multicast communication over satellites. These new features enable satellites to make efficient use of their allocated bandwidth resources and provide cost effective network services but equally, create new challenges for mobile satellite terminals. IP mobility support in general and IP mobile multicast support in particular on mobile satellite terminals like the ones mounted on continental flights, maritime vessels, etc., still remain big challenges that have received very little attention from the research community. Up till now, there are no proposed mechanisms to support IP multicast for mobile receivers/sources in multi-beam satellite networks in open literature. This study explores the suitability of IP multicast mobility support schemes defined for terrestrial networks in a satellite environment and proposes novel schemes based on the concepts of Home and Remote subscription-based approaches, multiple interface and PMIPv6 protocol. Detailed analysis and comparison of results obtained from the proposed schemes, Mobile IP (MIP) Home and Remote subscription-based approaches (for terrestrial networks) when implemented on a reference multi-beam satellite network are presented. From these results, the proposed schemes outperform the MIP Home and Remote subscription-based approaches in terms of gateway handover latency, number of multicast packets lost and signalling cost over the satellite air interface.

The inherent broadcast nature of satellites, their global coverage and direct access to a large number of subscribers give satellites unrivalled advantages in supporting IP multicast applications. A new generation of satellite systems that support regenerative on-board processors and multiple spot beam technology have opened new possibilities of implementing IP multicast communication over satellites. These new features enable satellites to make efficient use of their allocated bandwidth resources and provide cost effective network services but equally, create new challenges for mobile satellite terminals. IP mobility support in general and IP mobile multicast support in particular on mobile satellite terminals like the ones mounted on continental flights, maritime vessels, etc., still remain big challenges that have received very little attention from the research community. Up till now, there are no proposed mechanisms to support IP multicast for mobile receivers/sources in multi-beam satellite networks in open literature. This study explores the suitability of IP multicast mobility support schemes defined for terrestrial networks in a satellite environment and proposes novel schemes based on the concepts of Home and Remote subscription-based approaches, multiple interface and PMIPv6 protocol. Detailed analysis and comparison of results obtained from the proposed schemes, Mobile IP (MIP) Home and Remote subscription-based approaches (for terrestrial networks) when implemented on a reference multi-beam satellite network are presented. From these results, the proposed schemes outperform the MIP Home and Remote subscription-based approaches in terms of gateway handover latency, number of multicast packets lost and signalling cost over the satellite air interface.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2006.
Thesis Advisor(s): David Jenn, Clark Robertson, Richard Adler. "September 2006." Includes bibliographical references (p. 103-107). Also available in print.

This master thesis report details the process of developing a simulation platform for radio transceivers with a focus on analog receiver front end system design. The platform was implemented in the National Instruments VSS environment for the company Ericsson AB.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California
Radar echo sounders provide a safe, inexpensive and effective means of obtaining ice sheet thickness. As the roughness of ice surface/subsurface depends on the radio wavelength, wideband radar sensors can provide flexibility for ice thickness measurement under areas with various surface conditions. This paper presents the design of a digitally controllable wideband microwave receiver for a potential radar sounding system. Its radio frequency (RF) frequency ranges from 50 to 500 MHz, while the intermediate frequency (IF) bandwidth is 20 MHz. The receiver provides eight channels for different RF band choices, as well as a number of convenient gain settings. Testing measurements have also been conducted to verify the design requirements.

The wirelessly networked opportunistic digital array radar (WNODAR) system combines opportunistic phased array and aperstructure concepts. The array elements contain standâ alone transmitâ receive (T/R) modules with no hardwire connections other than prime power and are wirelessly networked to a central controller and processor unit. A fullâ scale WNODAR operating in the VHF/UHF frequency bands (300 MHz) exhibits many favorable properties, which make the system suitable for ballistic missile defense (BMD) early warning radar (EWR) applications. In order to validate the WNODAR concepts, demonstration arrays consisting of T/R modules realized using field programmable gate array (FPGA) technology are developed. The demonstration units are frequency scaled from the projected VHF/UHF frequency range to S-band (2.4 GHz) to make use of the abundance of commercial off the shelf (COTS) wireless communication components. This research primarily relates to the development of a demonstration T/R module and the evaluation and characterization of component devices. Design, analysis and simulation of an eightâ element demonstration array using MATLAB and CST Microwave Studio were conducted to examine expected array beam patterns.

The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.

Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply.

Thesis (Ph. D.) -- University of Maryland, College Park, 2008.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

Doctor en Ingeniería Eléctrica
Este trabajo presenta un prototipo de un receptor de separación de banda lateral (2SB) para el Telescopio Austral de Ondas Milimétricas (SMWT) de 1.2 m de diámetro en el marco de su modernización. Ésta consiste en cambiar la configuración del receptor desde una configuración de doble banda lateral (DSB) a una 2SB con el fin de obtener un receptor competitivo para las observaciones astronómicas. También se presenta el rendimiento de este receptor en combinación con una plataforma digital que integra un híbrido de frecuencia intermedia (IF) y un espectrómetro en un receptor astronómico. De esta manera, se logran razones de rechazo de banda mejores que el actual estado del arte . En primer lugar, hemos caracterizado el receptor 2SB totalmente analógico y sus componentes usando dos importantes figuras de mérito: rechazo de banda y temperatura de ruido. La razón de rechazo de banda fue mayor que 7 dB en toda el ancho de banda de trabajo, mostrando que los componentes fabricados (Híbrido RF, Bifurcación de LO y Carga RF) cumplieron de buena forma las especificaciones. La temperatura de ruido del receptor estuvo bajo los 1500 K, atribuible principalmente al bajo rendimiento de los mezcladores comerciales, y más recientemente 300 K, después de cambiar el amplificador de bajo ruido y los mezcladores. Segundo, hemos medido también la razón de rechazo de banda para diferentes configuraciones del receptor 2SB usando un espectrómetro e híbrido RF digital como back-end. En todos los casos, una razón de rechazo de banda superior a 35 dB fue obtenida. Además, hemos comparado el rechazo de banda de un receptor completamente análogo 2SB de Banda-9 de ALMA con uno usando el esquema de back-end digital. Obtuvimos razones de rechazo de banda sobre 35 dB in toda la banda RF para el versión digital. Ésto esta sobre el rendimiento de cualquier receptor 2SB completamente análogo en la actualidad.

Thesis (M.S.)--Worcester Polytechnic Institute.
Keywords: precision personnel locator; digital systems; embedded systems; waveform generation; data communication. Includes bibliographical references (leaves 108-110).

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.
[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re
[CAT] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor I
Rodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967
TESIS

La Propagation d'Espérance (Expectation Propagation, EP) est une technique puissante utilisée en inférence statistique pour approximer des distributions de probabilités complexes par des distributions plus simples de la famille exponentielle, grâce à un appariement des moments. Des travaux récents ont démontré que son application à la conception de récepteurs numériques offre un compromis intéressant entre complexité et performance. En affinant de manière itérative les estimations de signal via une approche de passage de messages, l'EP fournit un cadre robuste pour relever des défis dans les systèmes de communication numérique, tels que l'interférence inter-symboles (ISI) dans les canaux à large bande. Dans cette thèse, un égaliseur linéaire auto-itératif en domaine fréquentiel basé sur l'EP (Frequency Domain Self-Iterated Linear Equalizer, FD-SILE) est étudié. Il est composé d'un égaliseur, d'un démappeur souple et d'un mappeur souple. Ces composantes exploitent le retour d'information de l'EP dans un processus d'auto-itération. Bien que le FD-SILE basé sur l'EP présente un compromis complexité-performance favorable, sa complexité computationnelle reste prohibitive pour des implémentations matérielles, notamment pour des constellations d'ordre élevé. Afin de réduire cette complexité, des simplifications analytiques sont introduites pour les processus de mappage et de démappage souples. Ces simplifications permettent une réduction significative de la complexité tout en préservant les performances en termes de taux d'erreurs binaires (Bit Error Rate, BER). Dans le cadre de cette thèse, des versions en virgule fixe des mappeurs et démappeurs souples simplifiés sont développées pour permettre la conception d'architectures. Différentes architectures sont conçues pour les schémas de modulation BPSK, QPSK, 8-PSK et 16-QAM. Ces architectures sont ensuite optimisées par pipeline, ce qui réduit considérablement le nombre de cycles d'horloge par trame. Une architecture flexible et pipelinée, capable de changer dynamiquement de constellation à chaque trame, est ensuite conçue et implémentée sur un dispositif FPGA. La validation est effectuée à l'aide d'une configuration hardware-in-the-loop (HIL), qui intègre un environnement de simulation sur ordinateur avec l'architecture implémentée sur FPGA, déployée sur une plateforme Zynq MPSoC
Expectation Propagation (EP) is a powerful technique used in statistical inference to approximate complex probability distributions with simpler ones from the exponential family through moment matching. Recent works have demonstrated that its application in digital receiver design offers an attractive complexity-performance trade-off. By iteratively refining signal estimates via a message-passing approach, EP provides a robust framework for addressing challenges in digital communication systems, such as inter-symbol interference (ISI) in wideband channels. In this thesis, an EP-based Frequency Domain Self-Iterated Linear Equalizer (FD-SILE) is considered, comprising an equalizer, a soft demapper and a soft mapper. These components take advantage of EP for feedback within a self-iterating process. While the EP-based FD-SILE demonstrates favorable complexity-performance, its computational complexity remains prohibitive for hardware implementations, particularly for high-order constellations. In order to decrease this computational complexity, analytical simplifications are introduced for the soft mapping and demapping processes. These simplifications achieve substantial reductions in computational complexity while preserving bit error rate (BER) performance.As part of this thesis work, fixed-point versions of the simplified soft mapper and demapper are carried out to enable architecture design. Different architectures are designed for the modulation schemes of BPSK, QPSK, 8-PSK, and 16-QAM. These architectures are then optimized through pipelining, significantly reducing the number of clock cycles per frame. A flexible pipelined architecture, capable of dynamically switching constellations on a per-frame basis, is subsequently designed and implemented onto an FPGA device. Validation is conducted using a hardware-in-the-loop (HIL) configuration, which integrates a simulation environment on a computer with the FPGA-implemented architecture on a Zynq MPSoC platform

碩士
大同大學
通訊工程研究所
90
Many kinds of mobile communication standards have grown up with the popularity of mobile communication. For recent different standards, they are different in coding, modulation, signal bandwidth, and data transmission rates. Therefore, the concept of software defined radio was generated. The thesis introduces the software defined radio system firstly. Then, we explore the practical structure of software defined radio receiver. Software defined radio provides more flexibility in RF, IF and base band. The signal is not only modulated/demodulated in base band, but also up/down converted in IF. In receiver, we downconvert the signal and demodulate it. In the thesis, we will use cascaded integrator-comb filter for decimation and compensation filter to design the digital IF programmable downconverter. For the FPGA hardware architecture, we will use the polyphase and non-recursive architecture to decrease the complexity of hardware. Finally, we will accomplish the gate-level design of programmable downconverter with Altera MAX+PLUS II 9.01 and download the programs to the ALTERA EPF10K50RC240-3 demoboard to realize the design.

碩士
國立臺灣科技大學
電機工程系
101
First, two inverted-F antenna design for digital broadcasting services and in-car entertainment applications which can operate in digital audio broadcasting (DAB) Band III (170-240 MHz) are presented. Then, an inverted-F antenna and a monopole antenna design for in-car DVB-T Taiwan band (530-602 MHz) applications are presented. Also, a monopole antenna design for in-car DVB-T U band (470-860 MHz) applications is presented. All antennas have simple structure and proper size, which can reduce blockages to driver’s visions. Those antennas are appropriate to be fabricated in a thin-film type and attached on the front windshield of a car along the edges of the A-pillars. Through joint efforts with the collaborating company, Asuka Semiconductor Inc., those antennas can be installed easily and also function well. Measurements in an anechoic chamber at Taiwan Tech together with a car model have been performed. Good agreements between simulation and measurements are obtained. Required performances in reflection coefficient, radiation pattern, and radiation efficiency are achieved for practical applications. Some of the designs are in mass production now.

碩士
國立交通大學
電信工程系
91
The currently used air-ground communication system is the Aircraft Communication Addressing and Reporting System (ACARS). Due to its low data transmission rate and small communication capacity, ACARS cannot cope with the need for the high throughput aeronautical communication. Thus, ICAO embarked on definition of a new standard for aeronautical communication. This is the VHF digital link (VDL); it has higher transmission rate and large capacity. The VDL will gradually replace the ACARS and become the key VHF data link system for the next generation air-ground data communication. This thesis is aimed to design a VDL mode2 basedband receiver and analyze its performance. First, we establish an aeronautical model, which can effectively model the air-ground channel. Based on the channel characteristics, we design key receiver modules including the matched filter, the timing recovery circuit, the frequency offset estimator, and the decision feedback equalizer. We then build a receiver model and use MATLAB to simulate its performance. The simulation results show that the designed receiver can meet the VDL requirement even in a harsh channel condition. Finally, we design a low-complexity receiver architecture and implement the receiver using FPGA. The result of this thesis can be further enhanced to build a complete VDL mode2 transceiver and be used to establish the key technology for the next-generation air-ground communications.

碩士
銘傳大學
資訊工程學系碩士班
97
The objective of the paper is to design and develop a digital TV player which conforms to the ETSI-302-304 DVB-H and ISO-13818 MPEG-2 standards. The receiver uses the European DVB-H-compatible video capture box as the main facility to capture multimedia DTV streams. The paper implements including a Core Stream module, a Session Description Protocol (SDP) Parser, a Multimedia Renderer and a System Database. First, through VideoLAN Client (VLC) SDK builds Core Stream module and implements DVB-H multimedia transport stream dissection, de-multiplex, decoding and rendering. Second, builds a SDP Parser follow RFC 2327 and obtain DVB-H stream information. Third, via Simple Direct Layer (SDL) builds a Multimedia Renderer, render video and audio. Finally, create a System Database based on parsed DVB-SI and PSI program parameter.

碩士
國立交通大學
電信工程系
90
The currently used air-ground communication system is the Aircraft Communication Addressing and Reporting System (ACARS). Due to its low data transmission rate and small communication capacity, ACARS cannot cope with the need for the high throughput aeronautical communication. Thus, ICAO embarked on definition of a new standard for aeronautical communication. This is the VHF digital link (VDL); it has higher transmission rate and large capacity. The VDL will gradually replace the ACARS and become the key VHF data link system for the next generation air-ground data communication. This thesis is aimed to design a VDL mode2 basedband receiver and analyze its performance. First, we establish an aeronautical model, which can effectively model the air-ground channel. Based on the channel characteristics, we design several key receiver modules including the matched filter, the timing recovery circuit, the frequency offset estimator, and the decision feedback equalizer. We then build a receiver architecture and use MATLAB to evaluate its performance. The simulation results show that the designed receiver can meet the VDL requirement even in a harsh channel condition. Finally, we focus on the implementation of the frequency estimator. Using VHDL, we design a low complexity frequency estimator. The result of this thesis can be further enhanced to build a complete VDL mode2 transceiver and be used to establish the key technology for the next-generation air-ground communications.

碩士
國立臺灣大學
電信工程學研究所
88
Aircraft communications have remained fundamentally unchanged for nearly a century. Air to ground communication currently uses simple Amplitude Modulation (AM) voice in the VHF band. The steady increase in air traffic volume has now resulted in the allocated VHF spectrum reaching near saturation in Europe and the USA. To cope with this challenge, ICAO, RCTA and others have embarked on the definition of a new standard for aeronautical VHF digital communication. That is " GNSS Based Precision Approach Local Area Augmentation System (LAAS) " [1]. This standard defines a new modulation technique that allows the transmission of data by phase coding known as D8PSK (Differential Eight Phase Shift Keying). Voice signals are digitized and multiplexed together with the Data Link information in a technique known as Time Division Multiple Access (TDMA). This thesis will focus on the design of a all digital LAAS receiver. As a result of the advancement of ADC device and lower carrier frequency (VHF band), one of the fundamental ideas of this LAAS receiver is the expansion of digital signal processing toward the antenna, and thus to regions where analog signal processing has been dominant so far. The input to the radio frequency stage of a LAAS receiver is a wide band signal, which is converted into a digital signal by subsampling. The purpose of DSP at this stage is to select the signal of interest, which is a narrow-band signal, from a wide-band input, and to translate the signal down to baseband. The most important key component at the stage is to design an efficient filter, because the input sampling rate of the filter is usually rather high, and its passband and transition bandwidths are extreme narrow. Here we adopt CIC filter and halfband filter structure. This structure can efficiently down the input signal to the rate that baseband processing stage can handle. At the baseband processing stage, we will adopt a standard general-purpose DSP processor to implement all baseband demodulation operations. The techniques of the baseband demodulation include matched filters, timing recovery, frequency recovery, and AGC. All algorithms are simulated in the Matlab Simulink [2] environment, and we have compared the result with idea case value. And we also implement this system in TI TMS320C54 DSP [3] to demonstrate that our LAAS receiver can really be implemented in a real hardware environment.