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Journal articles on the topic 'Digital Receiver Design'

Author: Grafiati
Published: 29 March 2025

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1

Bakhru, Kesh. "Communications receiver design using digital processing." Digital Signal Processing 2, no. 1 (January 1992): 2–13. http://dx.doi.org/10.1016/1051-2004(92)90018-t.

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2

Liu, Yu Peng, Chao Du, and Dong Lin Liu. "Design and Implementation of Multi-Frequency Digital Receiver Based on FPGA." Applied Mechanics and Materials 643 (September 2014): 117–23. http://dx.doi.org/10.4028/www.scientific.net/amm.643.117.

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Recently, the concept of software radar has been proposed. The wide application of the digital technology has become a trend. With the development of modern radar system, the system requires higher and higher performance to the radar receiver. The technology of digital receiver has become an effective implementation method for high-accuracy and wide-band radar receiving systems. However, most of the digital receiver can only receive one wide-band signal with one center frequency. A multi-frequency digital receiver which can receive several center frequencies of signal simultaneously [1] is discussed in this paper. We also describe the theory and the design about digital receiver, introduce digital downconversion (DDC), FIR and decimation, digital beam forming and channel calibration. Based on the research, a realization of multi-frequency digital receiver based on FPGA is put forward. The analysis and simulation is made and the result shows the design of great performance.
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3

Zhang, Lin, Yi Wen Liu, and Yi Cao. "Design of Digital Receiver Based on FPGA." Applied Mechanics and Materials 419 (October 2013): 528–32. http://dx.doi.org/10.4028/www.scientific.net/amm.419.528.

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This article is intended to introduce electronic reconnaissance digital channelized receiver design ideas based on FPGA implementation structure. It takes the use of polyphase filter implementation of Achieved using the polyphase filter bank channelized receiver as the focus, and makes use of multiple parallel receiving channels to get the results of the simulation. The channelizing is realized in the FPGA device of xc4vsx55 which belongs to Virtex4 group in Xilinx family. During the process of design, highly effective polyphase and the parallel assembly line structure's FFT flexibility are fully considered, which reduce the operand enormously and raise the operating speed.
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4

Revathi, V., P. Parvati, and G. Hemachandra. "Design and Simulation of Digital Beacon Receiver." i-manager’s Journal on Wireless Communication Networks 5, no. 4 (2017): 20. http://dx.doi.org/10.26634/jwcn.5.4.13555.

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5

Shazly, Khadija, Mohamed E. .., and Sunil Kumar. "Design and FPGA Implementation of Digital Frequency Modulation Receiver." International Journal of Wireless and Ad Hoc Communication 4, no. 2 (2022): 107–66. http://dx.doi.org/10.54216/ijwac.040206.

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In this paper, we introduce the design of a digital frequency modulation receiver using FPGA. The main component in the design is digital phase locked loop (DPLL) which compensate any changes between the frequency and phase of the input modulated signal and the frequency and phase of numerically controlled oscillator. The input to the receiver is 8-bit represents the sampled discrete time signal from the analog modulated received frequency modulation signal. The receiver is designed using Xilinx system generator and implemented on the FPGA board (Xilinx Vitrex-7 XC7VX550t board), works with 350 MHz and consumes 120 mW.
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Sakr, Ahmed, Aziza I. Hussein, Ghazal Fahmy, and Mahmoud A. Abdelghany. "Design of PWM-Based Digital Receiver for 5G." Procedia Computer Science 182 (2021): 159–65. http://dx.doi.org/10.1016/j.procs.2021.02.021.

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7

Kim, Seung-Geun, Chang-Ho Yun, Sea-Moon Kim, and Yong-Kon Lim. "Baseband Receiver Design for Maritime VHF Digital Communications." Journal of Korea Information and Communications Society 36, no. 8B (August 31, 2011): 1012–20. http://dx.doi.org/10.7840/kics.2011.36b.8.1012.

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8

Lim, Eun-Jae, Hee-Geun Hwang, and Young-Chul Rhee. "A Study on RF Receiver Design and Analysis of Digital Radar Receiver." Journal of Korean Institute of Electromagnetic Engineering and Science 25, no. 3 (March 31, 2014): 282–88. http://dx.doi.org/10.5515/kjkiees.2014.25.3.282.

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9

Podstrigaev, Alexey S. "UWB digital receiver design methodology with sub-Nyquist sampling." T-Comm 15, no. 10 (2021): 11–17. http://dx.doi.org/10.36724/2072-8735-2021-15-10-11-17.

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UWB digital receiver design methodology with sub-Nyquist sampling in radio monitoring and cognitive radio tasks, processing of overlapped signals in an ultra-wide frequency band without gaps is required. A digital receiver with sub-Nyquist sampling allows solving this problem. However, in practice, we have some issues. There are various kinds of ambiguity in determining the frequency. The nonlinear elements of the path generate parasitic harmonics of the input signal. In the multi-signal mode, the discrimination of signals deteriorates. All this significantly reduces the efficiency of signal analysis. Therefore, a receiver circuit with software implemented means of eliminating the listed disadvantages is proposed. Such a receiver has features characteristic of sub-Nyquist sampling and selectable parameters. A special technique has been developed to systematize the design process of the receiver. The design methodology takes into account the use of the receiver in single-signal and multi-signal modes. The result of the design is the receiver block diagram with a justification of the parameters of its main elements. The proposed methodology makes it possible to evaluate system characteristics such as sensitivity, the number of processing channels and the throughput by the number of superimposed signals. Automation of checking the conditions given in the methodology can significantly increase the speed and convenience of design. It is shown that for the Gigabit Ethernet interface, the through put of the receiver is about eight superimposed pulse or continuous signals. In this case, due to parasitic components arising in the nonlinear elements of the path, it can be reduced to 4 superimposed signals. The actual number of processed signals is also determined by the probability of their overlap, and when receiving pulsed signals, it can be much higher.
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10

Zhang, Chengchang, and Lihong Zhang. "Intermediate Frequency Digital Receiver Based on Multi-FPGA System." Journal of Electrical and Computer Engineering 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/6123832.

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Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC) system, we have proposed a new intermediate frequency (IF) digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF) is realized by coordinated rotation digital computer (CORDIC) algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.
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11

Zhang, Zengmao, Qingchen Xu, Xiong Hu, Bing Cai, Yongkun Wu, Junfeng Yang, and Mingliang Zhao. "Dual-Frequency, Dual-Mode Reconfigurable Digital Atmospheric Radar Receiver Design." Electronics 13, no. 10 (May 11, 2024): 1879. http://dx.doi.org/10.3390/electronics13101879.

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A new dual-frequency, dual-mode reconfigurable digital receiver based on Field-Programmable Gate Array (FPGA) dynamic reconfiguration is proposed, which is based on a common hardware platform of high-bandwidth RF front-end, high-speed data acquisition, and real-time signal processing. The receiver adopts the design of dynamically reconfigurable down-conversion, filter extraction, and matched filtering in the digital domain. In this study, we completed the design and development of the digital receiver, experimental platform construction, and field detection test with hardware and software cooperation. The experimental results show that the receiver achieves full digital reception and signal processing for 53.8 MHz stratosphere–troposphere (ST) detection and 35.0 MHz meteor detection and successfully acquired the number of meteors versus time, the meteor trail, and low-altitude atmospheric radial winds. This dual-frequency, dual-mode reconfigurable digital receiver can be applied to new-generation multifunction integrated radar systems such as dual-frequency ST/meteor radars.
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Wang, Rui. "Hardware Circuit Design and Implementation of Digital IF Receiver." Journal of Physics: Conference Series 2031, no. 1 (September 1, 2021): 012044. http://dx.doi.org/10.1088/1742-6596/2031/1/012044.

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Abstract At present, most of the digital IF receivers have bottlenecks in the acquisition and analysis of ultra-high frequency bandwidth signals. At the same time, they have the disadvantages of low resolution and low input bandwidth, which cannot meet the needs of ultra-high frequency signal measurement. In this paper, a high-resolution, high-bandwidth digital IF receiver hardware system is designed based on ADC + FPGA architecture. The front-end analog signal is discretized by two high-speed ADC chips and sent to FPGA to decode the sampling data, and the FFT IP core is called to calculate the power spectrum of the signal. The spectrum data are sent to the host computer through RS485 module and Ethernet chip to display the spectrum image of the original signal in real time, so as to analyze the temperature profile of the target atmosphere.
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13

Ji-Sung Oh, Yong-Duk Chang, Hyun-Soo Shin, Myeong-Hwan Lee, and Ki-Burn Kim. "A design of VSB receiver IC for digital television." IEEE Transactions on Consumer Electronics 45, no. 3 (1999): 943–49. http://dx.doi.org/10.1109/30.793652.

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14

Денисов, А. Е., and Д. П. Данилаев. "Использование радиофотонного аналого-цифрового преобразователя в структуре цифрового радиоприёмного устройства." Vestnik of Volga State University of Technology. Series Radio Engineering and Infocommunication Systems, no. 3(59) (November 20, 2023): 33–44. https://doi.org/10.25686/2306-2819.2023.3.33.

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В статье рассмотрены характеристики, структура и отличительные особенности фотонных аналого-цифровых преобразователей (ФАЦП). Определено преимущество достигаемой ФАЦП частоты дискретизации, позволяющей обрабатывать сигналы СВЧ-диапазона без использования переноса частоты и предварительной фильтрации. Исследована возможность увеличения отношения несущей к шуму и эффективного числа бит за счёт усиления принимаемого сигнала. Определены требования и представлено структурное решение, позволяющее использовать преимущества ФАЦП для достижения лучших параметров приёмника. Introduction Designing digital radio receivers poses challenges primarily related to the selection of ADCs and the constraints they introduce. These challenges include high intrinsic noise levels with varying sources, limited sampling rates, and more. Consequently, the architecture of digital radio receivers incorporates an initial analog component responsible for receiving and processing signals before digitization. The integration of microwave photonics offers a means to move the radio receiver's design closer to the optimal configuration for digital signal processing while enhancing certain receiver parameters. Photonic ADCs hold promise as a key element in achieving these goals. The aim of the work is to assess how photonic ADCs (PADC) impact the parameters and configuration of a digital radio receiver. Evaluation of the parameters of the PADC/ To evaluate the impact of the ADC on the design and parameters of the digital radio receiver, we need to examine the characteristics of the converter. The following advantages are worth noting: 1. The high sampling frequency of 100 GHz has two significant benefits. Firstly, it enables the processing of signals up to 50 GHz, eliminating the need for a mixer to downconvert the signal to a lower frequency. This, in turn, removes an element with a high inherent noise level. Secondly, the PADC's sampling frequency allows for the avoidance of an anti-aliasing filter due to its wide Nyquist zone. The absence of noise from other zones can be achieved by employing antennas tuned to the specific frequency range of the received signals. 2. Incorporating optical elements in the PADC structure enhances the carrier-to-noise ratio (CNR). This is achieved by increasing the average optical power on the photodiode, particularly when the effective noise from the relative intensity of the optical source is negligible. Furthermore, raising the received radio signal level allows for an increase in the optical modulation index. 3. The effective number of bits (ENOB) is directly linked to the carrier-to-noise ratio. Therefore, increasing the average optical power on the photodiode or enhancing the received radio signal also leads to an increase in ENOB. The design of a digital receiver with a PADC. To harness the advantages offered by the PADC, the design of the preliminary section must adhere to specific requirements. It should amplify the received signal in a manner where the most substantial gain is applied to the weakest signal while the strongest signal receives the lowest gain. To fulfill these requirements, a system with channel switching is suggested. This system is configured such that all amplifiers possess different gain levels and are situated in separate branches. At the output of each amplifier, a PADC is employed. Consequently, the selection of the channel in which the signal performs optimally is determined within the software environment. Conclusion. The paper delves into the impact of the PADC on the parameters and structure of a digital radio receiver. An evaluation of the potential advantages of employing the PADC is conducted. Furthermore, a structural approach is presented, offering a means to fully realize the benefits of the PADC.
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15

Salam, Abdul. "Subsurface MIMO: A Beamforming Design in Internet of Underground Things for Digital Agriculture Applications." Journal of Sensor and Actuator Networks 8, no. 3 (August 10, 2019): 41. http://dx.doi.org/10.3390/jsan8030041.

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In underground (UG) multiple-input and multiple-output (MIMO), transmit beamforming is used to focus energy in the desired direction. There are three different paths in the underground soil medium through which the waves propagate to reach the receiver. When the UG receiver receives a desired data stream only from the desired path, then the UG MIMO channel becomes a three-path (lateral, direct, and reflected) interference channel. Accordingly, the capacity region of the UG MIMO three-path interference channel, and the degrees of freedom (multiplexing gain of this MIMO channel) requires careful modeling. Therefore, expressions are required for the degrees of freedom of the UG MIMO interference channel. The underground receiver needs to perfectly cancel the interference from the three different components of the EM waves propagating in the soil medium. This concept is based upon reducing the interference of the undesired components to a minimum level at the UG receiver using the receive beamforming. In this paper, underground environment-aware MIMO using transmit and receive beamforming has been developed. The optimal transmit and receive beamforming, combining vectors under minimal intercomponent interference constraints, are derived. It is shown that UG MIMO performs best when all three components of the wireless UG channel are leveraged for beamforming. The environment-aware UG MIMO technique leads to three-fold performance improvements and paves the way for design and development of next-generation sensor-guided irrigation systems in the field of digital agriculture. Based on the analysis of underground radio-wave propagation in subsurface radio channels, a phased-array antenna design is presented that uses water content information and beam-steering mechanisms to improve efficiency and communication range of wireless underground communications. It is shown that the subsurface beamforming using phased-array antennas improves wireless underground communications by using the array element optimization and soil–air interface refraction adjustment schemes. This design is useful for subsurface communication system where sophisticated sensors and software systems are used as data collection tools that measure, record, and manage spatial and temporal data in the field of digital agriculture.
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16

Singh, Ashutosh Kumar. "Universal Asyncronous Receiver Transmitter." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (March 31, 2024): 1054–56. http://dx.doi.org/10.22214/ijraset.2024.58997.

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Abstract: This project focuses on the Verilog-based design and implementation of a Universal Asynchronous ReceiverTransmitter (UART) communication module. The UART is a fundamental component in digital systems, facilitating serial data transmission between devices. Our objective is to develop a robust and efficient Verilog description of the UART module, emphasizing simplicity, modularity, and ease of integration. The baud rate generator allows for flexible communication speeds, accommodating diverse applications. The module ensures accurate framing of transmitted and received data through the proper generation of start and stop bits. Error-detection mechanisms are implemented to enhance data integrity. The project enhances the digital design field by delivering a Verilog implementation of a UART communication module that is both dependable and efficient.
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17

Lei, Neng Fang. "The Design of Digital Communication System Based on FPGA." Applied Mechanics and Materials 687-691 (November 2014): 3093–96. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3093.

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The paper investigates the Multi-FPGA systems structure, including interconnect and configuration structure of the systems. After analyzing several common FPGA systems interconnection structure, we present its features. The paper analyses the feasibility and technical advantages for FPGA systems to use in digital array radar receiver design, and discusses their specific implementation, and designs a set of IF receiver with twenty reception elements.
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18

Wang, Zongbo, Oleg A. Krasnov, Galina P. Babur, Leo P. Ligthart, and Fred van der Zwan. "Reconfigurable digital receiver design and application for instantaneous polarimetric measurement." International Journal of Microwave and Wireless Technologies 3, no. 3 (April 6, 2011): 355–64. http://dx.doi.org/10.1017/s175907871100033x.

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This paper presents the development of a reconfigurable receiver to undertake challenging signal processing tasks for a novel polarimetric radar system. The field-programmable gate arrays (FPGAs)-based digital receiver samples incoming signals at intermediate frequency (IF) and processes signals digitally instead of using conventional analog approaches. It offers more robust system stability and avoids unnecessary multichannel calibrations of analog circuits for a full polarimetric radar. Two kinds of dual-orthogonal signals together with corresponding processing algorithms have been investigated; the digital implementation architectures for all algorithms are then presented. Processing algorithms implemented in FPGA chips can be reconfigured adaptively regarding to different transmitted waveforms without modification of hardware. The successful development of such reconfigurable receiver extends our radar capacity and thus yields tremendous experimental flexibility for atmospheric remote sensing and polarimetric studies of ground-based targets.
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Liu, Xiao Peng, Yan Han, Dong Dong Zhong, and Ming Yu Wang. "The Design and Implement of a Receiver for FSK Signal." Applied Mechanics and Materials 190-191 (July 2012): 739–41. http://dx.doi.org/10.4028/www.scientific.net/amm.190-191.739.

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A novel frequency shift keying (FSK) receiver is presented, including receiving antennas, a low noise amplifier (LNA), band-pass filters (BPF) and a novel all-digital 2-level FSK demodulator. The Matlab simulation results of the all-digital FSK demodulator show that it can improve bit error ratio (BER) performance compared with pseudo-coherent FSK demodulation (PCFSK). The novel FSK demodulator defined using Verilog HDL is easy to be implemented on Field Programmable Gate Array (FPGA) and in CMOS integrated circuit. The whole FSK receiver designed and implemented on a PCB board can receive FSK signal and send the recovered data to computer through RS-232 interface.
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20

Ding, You Hua, Peng Zhang, and Han Ao Xia. "The Design of Radar Intermediate Frequency Echo Simulator." Applied Mechanics and Materials 687-691 (November 2014): 4084–88. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.4084.

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This paper has introduced a kind of method which can simulate the echo signal of radar receiver by the use of the Digital Radio Frequency Memory (DRFM) and Programable Logic Device (PLD).With the realization of actual circuit,the echo simulator can produce intermediate frequency and video signals.Therefore,with the help of the echo simulator, we can raise the detection ability of radar receiver system considerably. The structure of the simulator is simple but its function is great.The echo simulator can simulate intermediate frequency signals of radar receiver system for the first time.So the simulator can locate where isn’t work well of the radar receive system.
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21

Chen, Zi Yu, and Xin Wei Zhang. "Design of Parametric Loudspeaker and Receiver System." Advanced Materials Research 909 (March 2014): 222–27. http://dx.doi.org/10.4028/www.scientific.net/amr.909.222.

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Parametric loudspeaker systems have been widely used for projecting highly directional audible sound to a specified area. However, the demodulated signal from parametric loudspeaker suffers from high distortion since the nonlinear interaction among primary waves also generate harmonics. In order to reduce distortion, signal acquisition and digital signal processing techniques can be applied at the receiver. In this paper, a parametric loudspeaker and receiver system is designed to reduce distortion using median filtering and mean filtering at the receiver. Compared to conventional systems, the demodulated signal using proposed techniques exhibits lower distortion.
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Kim, Tae-Hwan, Sung-Ju Lee, Dong-Hwi Lee, Yun-Seok Hong, and Choon-Sik Cho. "Design and Measurement of Active Phased Array Radar Digital Receiver." Journal of Korean Institute of Electromagnetic Engineering and Science 22, no. 3 (March 31, 2011): 371–79. http://dx.doi.org/10.5515/kjkiees.2011.22.3.371.

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23

Nguyen, Minh Tien, Chadi Jabbour, Seyed Majid Homayouni, David Duperray, Pascal Triaire, and Van Tam Nguyen. "System Design for Direct RF-to-Digital $\Delta\Sigma$ Receiver." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 10 (October 2016): 1758–70. http://dx.doi.org/10.1109/tcsi.2016.2589542.

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24

Coy, R. J., C. N. Smith, and P. R. Smith. "HF-band radio receiver design based on digital signal processing." Electronics & Communications Engineering Journal 4, no. 2 (1992): 83. http://dx.doi.org/10.1049/ecej:19920016.

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25

Chen, C. I. H., K. George, W. McCormick, J. B. Y. Tsui, S. L. Hary, and K. M. Graves. "Design and Performance Evaluation of a 2.5-GSPS Digital Receiver." IEEE Transactions on Instrumentation and Measurement 54, no. 3 (June 2005): 1089–99. http://dx.doi.org/10.1109/tim.2005.847206.

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Joeressen, O., M. Oerder, R. Serra, and H. Meyr. "DIRECS: system design of a 100 Mbit/s digital receiver." IEE Proceedings G Circuits, Devices and Systems 139, no. 2 (1992): 222. http://dx.doi.org/10.1049/ip-g-2.1992.0037.

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Wang, Hong-mei, Jae-hyung Kim, Fa-guang Wang, Sang-hyuk Lee, and Xue-song Wang. "Design of BPS digital frontend for software defined radio receiver." Journal of Central South University 22, no. 12 (December 2015): 4709–16. http://dx.doi.org/10.1007/s11771-015-3022-8.

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Belov, E. V., and E. A. Brusin. "DIGITAL SATELLITE MODEM RECEIVER DESIGNED WITH RUSSIAN-MADE ELECTRONIC COMPONENTS." Electronic engineering Series 2 Semiconductor devices 258, no. 3 (2020): 60–64. http://dx.doi.org/10.36845/2073-8250-2020-258-3-60-64.

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In this paper we propose the design of the receiving path of an advanced satellite modem. The receiver comprises only the components produced by Russian domestic companies. The parameters of the receiver are discussed in the paper. 3D model of the receiver board obtained using the Altium Designer integrated computer-aided design (CAD) system is also presented.
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Ira Mae Caray, King Paulo Ditchon, and Edwin Romeroso Arboleda. "Enhancing television broadcasting: Exploring the Gray-Hoverman Antenna Design." World Journal of Advanced Research and Reviews 23, no. 1 (July 30, 2024): 811–15. http://dx.doi.org/10.30574/wjarr.2024.23.1.2064.

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This study examines the design and performance of an own made Gray-Hoverman Antenna, an affordable alternative to commercial antennas optimized for UHF and VHF digital TV signal reception. Constructed with copper wire as the receiver and mesh galvanized steel as the reflector, the antenna demonstrated significant gain and directivity. Testing results showed the antenna's capability to receive 54 channels, including 38 digital TV channels. The findings indicate the effectiveness of Gray-Hoverman Antenna for HDTV viewing experiences.
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PNEVMATIKAKIS, ARISTODEMOS, LAMPROS DERMENTZOGLOU, and AGGELIKI ARAPOYANNI. "ANALOG-TO-DIGITAL INTERFACE FOR HETERODYNE RECEIVERS." Journal of Circuits, Systems and Computers 11, no. 01 (February 2002): 57–72. http://dx.doi.org/10.1142/s021812660200029x.

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The analysis of the Intermediate Frequency (IF) section of a heterodyne receiver employing IF sampling, based on its Carrier-to-Interference ratio (C/I), yields various options on filtering, amplification, conversion to digital and interfacing to base-band. These options are considered using Bit Error Rate (BER) simulations, leading to an optimized design for the IF section and the interface to base-band of the heterodyne receiver.
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Zhao, An, Yihua Yan, Wei Wang, Linjie Chen, Jian Zhang, and Fei Liu. "Five-element Digital Corrector Receiver for the Chinese Spectral Radioheliograph." Proceedings of the International Astronomical Union 8, S294 (August 2012): 497–98. http://dx.doi.org/10.1017/s1743921313003025.

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AbstractThe design of five-element digital receiver system is decribed. At first, we analyzed the process of data processing in the receiver system. Then we wrote programs to implement the FIR parallel filter and showed its simulation results. Finally the testing result of the correlation receiver system is demonstrated.
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Golubičić, Zoran, Slobodan Simić, and Aleksa J. Zejak. "Design and EPGA Implementation of Digital Pulse Compression for Band–Pass Radar Signals." Journal of Electrical Engineering 64, no. 3 (May 1, 2013): 191–95. http://dx.doi.org/10.2478/jee-2013-0028.

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The paper presents fully digitized approach for band-pass discrete coded radar signals. The emphasis is to use one generalized reconfigurable compressor for several different types of signals and different types of receivers. It fits for direct radio frequency receiver (RF) as well as for intermediate frequency (IF) receiver. The system implementation on field programmable gate area (FPGA) let us eliminate special chips previously needed. From the experimental results it is known that this approach appears to work well for matched and mismatched pulse compression and it outstands when timebandwidth product (TB) is of order 1000. A precision of 14 bits has been considered in the input signal and 16 bits in the filter coefficients. It gives the dynamic range of 78 dB and the quantification error less than 0.012%.
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Raju, Kota Solomon. "Digital Multichannel GPS Receiver Baseband Modules using Model Based Design Tools." International Journal of Mobile Network Communications & Telematics 2, no. 4 (August 31, 2012): 9–18. http://dx.doi.org/10.5121/ijmnct.2012.2402.

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Zhang, Liming. "Design and implementation of high performance digital receiver based on FPGA." JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT 27, no. 5 (February 28, 2014): 479–83. http://dx.doi.org/10.3724/sp.j.1187.2013.00479.

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Lee, Kyung-Soon, and Kyung-Heon Koo. "Design of the Satellite Beacon Receiver Using Array Based Digital Filter." Journal of Korean Institute of Electromagnetic Engineering and Science 27, no. 10 (October 31, 2016): 909–16. http://dx.doi.org/10.5515/kjkiees.2016.27.10.909.

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REVATHI, V., P. PARVATHI, G. HEMACHANDRA***, and KUMAR CH V. M. S. N.PAVAN. "DESIGN, SIMULATION AND TESTING OF DIGITAL BEACON RECEIVER USING ADS SOFTWARE." i-manager's Journal on Communication Engineering and Systems 7, no. 3 (2018): 16. http://dx.doi.org/10.26634/jcs.7.3.14310.

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George, Kiran, and Chien-In Henry Chen. "A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement." IEEE Transactions on Instrumentation and Measurement 60, no. 12 (December 2011): 3956–58. http://dx.doi.org/10.1109/tim.2011.2152590.

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38

Jae Seung Choi, Joo Won Kim, Dong Seog Han, Jae Yeal Nam, and Yeong Ho Ha. "Design and implementation of DVB-T receiver system for digital TV." IEEE Transactions on Consumer Electronics 50, no. 4 (November 2004): 991–98. http://dx.doi.org/10.1109/tce.2004.1362489.

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39

Ke, Lei, Huarui Yin, Weilin Gong, and Zhengdao Wang. "Finite-resolution digital receiver design for impulse radio ultra-wideband communication." IEEE Transactions on Wireless Communications 7, no. 12 (December 2008): 5108–17. http://dx.doi.org/10.1109/t-wc.2008.071223.

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40

White, B. A., and M. I. Elmasry. "Low-power design of decimation filters for a digital IF receiver." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 3 (June 2000): 339–45. http://dx.doi.org/10.1109/92.845900.

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41

Dolecek, Gordana Jovanovic, and fred harris. "Design of wideband CIC compensator filter for a digital IF receiver." Digital Signal Processing 19, no. 5 (September 2009): 827–37. http://dx.doi.org/10.1016/j.dsp.2009.03.013.

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42

Jiang, Hai Qing, Guang Liang Zou, and Ying Liu. "The Automatic Gain Control of the Digital Reconnaissance Receiver." Applied Mechanics and Materials 713-715 (January 2015): 820–24. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.820.

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On the basis of a brief introduction of how the automatic gain control (AGC) of the digital reconnaissance receiver works,this article proposed a digital AGC design method based on the digital processor parts, which provide a guarantee for the digital reconnaissance receiver to work in the complex external electromagnetic signal environment. The engineering implementation of AGC is introduced with specific projects. Both simulation and engineering practice verify the feasibility of this program.
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43

Funderburk, D. M., and S. Park. "A digital receiver design for AM stereo signals using a general purpose digital signal processor." IEEE Transactions on Consumer Electronics 40, no. 1 (1994): 64–74. http://dx.doi.org/10.1109/30.273649.

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44

Dai, Lan, Xin Hui, and Tao Sun. "Design of 3780 Points FFT Processor for DTMB Receiver." Applied Mechanics and Materials 239-240 (December 2012): 853–56. http://dx.doi.org/10.4028/www.scientific.net/amm.239-240.853.

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In this paper, a design of FFT processor for Digital terrestrial multimedia/television broadcasting (DTMB) receiver is presented. This processor is based on mixed-radix algorithms, prime factor algorithms and Winograd Fourier Transform algorithm (WFTA). Due to the adopted in-place algorithm in this design, the area consumption of the processor is reduced, and the simulation shows that SQNR of the processor is 60.5dB on the condition that the input and output data are both 13 bits.
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45

Waluyo, Waluyo, Koesmarijanto Koesmarijanto, and Lis Diana Mustafa. "Design and build a digital TV receiver double biquad antenna for the Greater Malang region and its surroundings." Jurnal Jartel Jurnal Jaringan Telekomunikasi 12, no. 4 (December 30, 2022): 281–86. http://dx.doi.org/10.33795/jartel.v12i4.523.

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Many types of antennas can be used for digital TV receivers; in this article we try to design a double biquad antenna. This is due to a simple form, easy to make, a wide beamwidth. In designing a digital TV receiver for the Malang area, an STB device is needed, so that analog TV can still receive digital TV broadcasts. In this study, the antenna is made of copper wire, each side length: ¼ ? , with a working frequency: 650 MHz. In order to match the impedance of the 75? coaxial cable with the antenna, a balun 4:1 is required. The research place is in the Polinema Telecommunications laboratory. The test results show that the lowest return loss (RL) occurs at a frequency of F=605 MHz, namely RL: -17.8 dB, for a frequency of F=650 MHz, the magnitude of RL: -11.3 dB. The large VSWR antenna at the working frequency F: 650 MHz is 1.46. So that it can be said that it has fulfilled the antenna parameters, namely VSWR < 2. It means that there is a power loss of less than 10%. The largest antenna gain occurs at a frequency: 400 MHz namely: 14.85 dB,. While the average gain of the antenna is 2.21 dB. The antenna radiation pattern is omni directional. The double biquad antenna is very good for use as a digital TV receiver for the Greater Malang area, either without using a reflector or with a reflector.
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Wang, Dong, Xiao Mei Hu, Yu Bin Wang, and Tao Yu. "Data Management Research of Digital Workshop Monitoring System." Advanced Materials Research 1039 (October 2014): 637–41. http://dx.doi.org/10.4028/www.scientific.net/amr.1039.637.

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With the development of the digital workshop technology, the digital workshop monitoring system is becoming more and more demanding. Data management is a key technology in the design of digital workshop monitoring system. The simulation model of the workshop is established based on virtual reality platform software Visual Components in the paper. The data in the production field are sent by Labview software, and the receiver is programmed by C# and the received data are stored in database created by SQL Server2008. TCP/IP protocol is used to realize the transfer between sender and receiver. Three fault libraries are established to achieve fault warning in digital workshop monitoring system. An example of digital workshop monitoring system is shown to prove the feasibility.
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Telagathoti, Pitchaiah, Moparthi Aparna, and P. V. Sridevi. "Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver." International Journal of Engineering & Technology 7, no. 2-1 (March 23, 2018): 421. http://dx.doi.org/10.14419/ijet.v7i2.9242.

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Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.
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Wu, Xiang Yu, Jin Rui Liu, Hang Gong, and Gang Ou. "Software Simulation Method for Digital if GNSS Signal." Advanced Materials Research 756-759 (September 2013): 2655–59. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.2655.

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Data simulation is an important auxiliary method for baseband signal processing algorithm design of digital IF GNSS receiver. Especially when the high sensitivity and high dynamic receivers are developed, or multipath and cross correlation mitigation techniques are considered, exact and complete tests under all kinds of necessary scenes can be carried out with the IF signal data which is generated by software simulation method. With this method, the developing efficiency can be improved and the cost can be cut down. In this paper, precise model of the IF signal is given firstly through analyzing GNSS receivers RF processing flow. Then, considering the discrete characteristic of software processing, the IF signal simulation flow and block of the simulation software are designed. Finally, the specific design process is given through a design example. When the IF signal simulation software is used for testing baseband signal processing algorithms, GNSS receivers IF signal data under every necessary test scene can be generated just by parameter adjustment.
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LAU, FRANCIS C. M., and CHI K. TSE. "OPTIMUM CORRELATOR-TYPE RECEIVER DESIGN FOR CSK COMMUNICATION SYSTEMS." International Journal of Bifurcation and Chaos 12, no. 05 (May 2002): 1029–38. http://dx.doi.org/10.1142/s0218127402004863.

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In a chaos-shift-keying (CSK) digital communication system, correlators followed by a comparator are typically used for coherent detection of the signal. Such a detection method, however, does not take the temporal variation of the bit energy into consideration. In this paper, an optimum detection for a binary CSK system is derived, taking into account the temporal variation of the bit energy for minimizing the error rates. Simulations are carried out to compare the performance between the optimum receiver and a typical receiver. The results provide theoretical performance benchmarks of coherent CSK systems for future references.
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Aka CC, Onah TO, and Egwuagu OM. "Design modification of elliptical vessel solar receiver by response surface methodology." Global Journal of Engineering and Technology Advances 19, no. 1 (April 30, 2024): 129–42. http://dx.doi.org/10.30574/gjeta.2024.19.1.0064.

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Design modification of elliptical vessel solar receiver system by response surface methodology has been carried out. The materials used in this study were locally sourced from Kenyeta Market Enugu, Onitsha Bridge Head Market, and Idumota Market Lagos. These materials were sourced based on categories of components element: support mechanisms made of mild steel plates, bolts, nuts, clamps, and water as heat transfer fluid. The reflector is made of aluminum foil tape while the vessel has a glass cover fitted with bolts and nuts, the receiver is made of copper pipe, aluminum pipe, galvanized iron pipes, and stainless steel pipes. The pipes were fitted into the vessel with chlorinated polyvinyl chloride 3⁄4 joint pipes, and journal-bearing mechanisms. Other features include the tracking system made of light dependent resistance sensors, a direct current motor, a pulley, a belt, an Arduino controller, and a thermal energy storage tank. The lagging material was an expanded Polyethylene sheet. Experimental data were measured with thermocouples, a digital panel, a Uni-T digital anemometer (UT363), and a digital solar power meter (SM206-SOLAR). Matrix Experimental design was used to develop an experimental model for the system. The developed system was tested to investigate the effect of various heat collectors with and without coating on its performance. It was established from the response optimization that the intercept factor was improved by 32.2%. Similarly, the theoretical efficiency was improved by 8.19% while the experimental thermal efficiency was improved by 6.99%.
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