Relevant bibliographies by topics / Digital synchronous circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Digital synchronous circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "Digital synchronous circuits"

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Shang, Zeyi, Sergey Verlan, Ion Petre, and Gexiang Zhang. "Reaction Systems and Synchronous Digital Circuits." Molecules 24, no. 10 (2019): 1961. http://dx.doi.org/10.3390/molecules24101961.

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A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause–effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation bet
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Gammie, Peter. "Synchronous digital circuits as functional programs." ACM Computing Surveys 46, no. 2 (2013): 1–27. http://dx.doi.org/10.1145/2543581.2543588.

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Friedman, E. G. "Clock distribution networks in synchronous digital integrated circuits." Proceedings of the IEEE 89, no. 5 (2001): 665–92. http://dx.doi.org/10.1109/5.929649.

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Sakallah, K. A., T. N. Mudge, and O. A. Olukotun. "Analysis and design of latch-controlled synchronous digital circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 3 (1992): 322–33. http://dx.doi.org/10.1109/43.124419.

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SWARTZ, ROBERT G. "ULTRA-HIGH SPEED MULTIPLEXER/DEMULTIPLEXER ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (1990): 73–99. http://dx.doi.org/10.1142/s0129156490000058.

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This paper describes two circuit architectures for ultra-high speed digital multiplexers and demultiplexers. The first, Type-I, is fully synchronous and uses a system clock that matches the maximum data rate. Circuits of this type can operate at a data rate equal to the maximum operating speed of a simple digital divider. A simpler and much more powerful architecture is proposed, Type-II, that operates using a half-frequency system clock at data rates up to twice the maximum clock speed of a simple digital divider. Basic building blocks and high speed design techniques are reviewed.
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Плеханов, Л. П., А. Н. Денисов, Ю. Г. Дьяченко, Ю. А. Степченков, Д. И. Мамонов та Д. Ю. Степченков. "СИНТЕЗ САМОСИНХРОННЫХ СХЕМ В БАЗИСЕ БМК". NANOINDUSTRY Russia 96, № 3s (2020): 460–70. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.460.470.

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Данный доклад посвящен разработке средств автоматизированного синтеза самосинхронных (CC) схем. Рассматриваются особенности реализации СС-схем. Предложен маршрут проектирования цифровых СС СБИС. Описана интеграция разрабатываемых средств в стандартную САПР синхронных СБИС («Ковчег»), обеспечивающая эффективное проектирование действительно СС-схем. This report is devoted to the development of software for automated synthesis of the self-timed (ST) circuits. Peculiarities of the ST circuit implementation have been discussed, and digital ST VLSI design flow has been offered. Besides, the report h
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Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades,
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Devadas, S., K. Keutzer, S. Malik, and A. Wang. "Event suppression: improving the efficiency of timing simulation for synchronous digital circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 6 (1994): 814–22. http://dx.doi.org/10.1109/43.285254.

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Bany Hamad, Ghaith, Syed Rafay Hasan, Otmane Ait Mohamed, and Yvon Savaria. "Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits." Microelectronics Reliability 55, no. 1 (2015): 238–50. http://dx.doi.org/10.1016/j.microrel.2014.09.025.

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Taskin, B., and I. S. Kourtev. "Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 1 (2004): 12–27. http://dx.doi.org/10.1109/tvlsi.2003.820525.

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Dissertations / Theses on the topic "Digital synchronous circuits"

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Silva, Thiago de Oliveira. "Elastic circuits in FPGA." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/174540.

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O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs
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Johnston, Robert Thomas. "A traffic generation algorithm for SDH digital cross-connects." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15723.

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Guatto, Adrien. "A synchronous functional language with integer clocks." Thesis, Paris Sciences et Lettres (ComUE), 2016. http://www.theses.fr/2016PSLEE020/document.

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Cette thèse traite de la conception et implémentationd’un langage de programmation pour les systèmes detraitement de flux en temps réel, comme l’encodagevidéo. Le modèle des réseaux de Kahn est bien adaptéà ce domaine et y est couramment utilisé. Dans cemodèle, un programme consiste en un ensemble deprocessus parallèles communicant à travers des filesmono-producteur, mono-consommateur. La force dumodèle réside en son déterminisme.Les langages synchrones fonctionnels comme Lustresont dédiés aux systèmes embarqués critiques. Un programmeLustre définit un réseau de Kahn synchronequi peut être exé
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Kessaci, Kamel. "Synthèse de circuits digitaux synchrones par transformations de programmes fonctionnels." Toulouse, ENSAE, 1992. http://www.theses.fr/1992ESAE0007.

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Avec la complexité croissante des circuits VLSI, la recherche de méthodes formelles de conception de circuits devient nécessaire pour atteindre l'objectif de circuits zéro-défaut dans les délais escomptés. Dans le cadre des circuits digitaux synchrones, nous proposons une méthodologie de conception de circuits descendante par transformations de programmes. La transformation de programmes consiste à dériver une réalisation à partir de sa spécification comportementale de haut niveau. La synthèse de circuits par transformations de programmes qualifie ce processus de réalisation. Pour cela, nous a
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Zianbetov, Eldar. "Horlogerie distribuée pour les SoCs synchrones." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2013. http://tel.archives-ouvertes.fr/tel-01053729.

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Cette thèse aborde le problème de génération d'horloge globale dans les SoCs complexes dans le contexte des technologies CMOS profondément submicroniques. Actuellement, afin de contourner les difficultés liées aux techniques classiques de distribution d'horloge (p.ex. arbre, grille) dans les systèmes synchrones, les concepteurs qui désirent de se rendre sur le paradigme Synchronisation Globale se tournent vers les techniques de synchronisation rompant avec les approches classiques (par exemple oscillateurs distribués, les ondes stationnaires , oscillateurs couplés, les retards programmables).
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Wu, Chen-Lung, and 伍振龍. "All-Digital Arbitrary Duty-Cycle Synchronous Mirror Delay Circuits." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/qp95uh.

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碩士<br>國立中央大學<br>電機工程研究所<br>94<br>In view of the current SOC systems, a great deal of circuits is integrated on a chip and the clock signal is entirely distributed. The clock synchronization, therefore, becomes truly an important issue on it. Phase-locked loop (PLLs) and delay-locked loop (DLLs) are often applied in many synchronization- dependent systems in order to suppress the clock skew. However, both PLLs and DLLs are the feedback systems and hence requiring a long locking time. During the lock-in frequency acquisition process, it results in a large standby current, which causes lots of po
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Martins, Celestino Virtudes Dias. "Adaptive error-prediction aging sensor for synchronous digital circuits." Master's thesis, 2012. http://hdl.handle.net/10400.1/3280.

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Dissertação de mest., Engenharia Eléctrica e Electrónica (Tecnologias da Informação e Telecomunicações), Instituto Superior de Engenharia, Univ. do Algarve, 2012<br>This paper presents a new approach on aging sensors for synchronous digital circuits. An Adaptive Error-Prediction Flip-Flop (AEP-FF) architecture with built-in aging sensor is proposed, to perform on-line monitoring of long-term performance degradation of CMOS digital systems, regardless of their origin. The main advantage is that the sensor’s performance degradation works in favor of the predictive error detection. Moreover,
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Chao-Kai, Chang, and 張兆凱. "Clock Skew Scheduling and Optimization for Large-Scale Digital Synchronous Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/31862676760789643015.

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碩士<br>長庚大學<br>電機工程研究所<br>93<br>This thesis will study the problem of an optimal clock skew scheduling for large-scale synchronous VLSI circuits. In the problem formulation phase, we formulate the clock skew scheduling problem as a constrained quadratic programming (QP) problem. From a reliability perspective, the ideal clock schedule corresponds to each clock skew within the circuit being at the center of the respective permissible range. The corresponding quadratic cost function is defined as the sum of the quadratic difference between the ideal schedule and the current design clock schedule
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Yeh, Yin-ping, and 葉蔭平. "An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/70360223391225308906.

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碩士<br>國立中央大學<br>電機工程研究所<br>100<br>The development and main stream of system-on-chip (SoC) are highly integration and higher operation speed. Therefore, in order to suppress the clock skew, the clock synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems. However, these circuits have to consider some problems in using. First, the PLL and DLL have issues of loop bandwidth because they are both closed loop systems. For this reason, they need to consider the loop stabil
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Lin, Yan-an, and 林沿安. "An 800 MHz ~ 1.6 GHz Fast Locking, All Digital Pulse-Width Control Synchronous Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93097360152932930280.

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碩士<br>國立中央大學<br>電機工程學系<br>101<br>With the raising of operation frequency in system-on-a-chip (SoC), clock skew becomes a more important issue needed to be solved. Phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay (SMD) are used to deskew clock skew in phase and frequency. Except phase alignment, duty cycle distortion is needed to calibrate for system reliability. And pulse-width control loop (PWCL) stands to suppress clock skew on duty cycle. This study proposes a 0.8 ~ 1.6 GHz all-digital synchronous pulse-width control loop in a 90-nm CMOS process. Forsaking the
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Books on the topic "Digital synchronous circuits"

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Synchronization of digital telecommunications networks. Wiley, 2002.

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Bronstein, Alexandre. String-functional semantics for formal verification of synchronous circuits. Dept. of Computer Science, Stanford University, 1988.

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Steven, Nowick, ed. Sequential optimization of asynchronous and synchronous finite-state machines: Algorithms and tools. Kluwer Academic Publishers, 2001.

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Fuhrer, Robert M. Sequential optimization of asynchronous and synchronous finite-state machines: Algorithms and tools. Kluwer Academic Publishers, 2001.

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Thalmann, Markus Andreas. A SDH add/drop multiplexer as "system-on-chip". Hartung-Gorre, 2000.

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Bregni, Stefano. Synchronization of Digital Telecommunications Networks. Wiley & Sons, Incorporated, John, 2003.

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Fuhrer, Robert M., and Steven M. Nowick. Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools. Springer, 2001.

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Book chapters on the topic "Digital synchronous circuits"

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Wirth, Niklaus. "Synchronous, Sequential Circuits." In Digital Circuit Design for Computer Science Students. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-642-57780-2_4.

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Wirth, Niklaus. "Formal Description of Synchronous Circuits." In Digital Circuit Design for Computer Science Students. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-642-57780-2_7.

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Vuillemin, Jean. "Finite Digital Synchronous Circuits Are Characterized by 2-Algebraic Truth Tables." In Advances in Computing Science — ASIAN 2000. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44464-5_1.

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Garda, Patrick, and Eric Belhaire. "An Analog Circuit with Digital I/O for Synchronous Boltzmann Machines." In VLSI for Artificial Intelligence and Neural Networks. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3752-6_24.

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Crowe, John, and Barrie Hayes-Gill. "Synchronous sequential circuits." In Introduction to Digital Electronics. Elsevier, 1998. http://dx.doi.org/10.1016/b978-034064570-3/50010-1.

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"Synchronous Sequential Circuits." In Foundations of Digital Logic Design. WORLD SCIENTIFIC, 1998. http://dx.doi.org/10.1142/9789812817044_0007.

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"Clocking of Synchronous Circuits." In Top-Down Digital VLSI Design. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800730-3.00007-1.

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"Testing of Synchronous Sequential Digital Circuits." In The Computer Engineering Handbook. CRC Press, 2001. http://dx.doi.org/10.1201/9781420041545-47.

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Hassine, Siwar Ben Haj, and Bouraoui Ouni. "Typical Design of Synchronous Controller to Minimize Response Time and Power." In Handbook of Research on Power and Energy System Optimization. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3935-3.ch009.

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As power dissipation and time constraint have become vital challenges during the creation of a digital circuit, researchers' and designers' efforts have increased to figure out new ways of preserving power through the study of its sources and its impacts as well as through the decrease of response time to obtain faster treatments. However, it is widely acknowledged that these two parameters are antagonistic in synchronous systems. In fact, current technologies have managed to further decrease the response time to have a faster circuit at the cost of a considerable simultaneous augmentation in its power or vice versa, which leaves no option for designers but to choose from these two important parameters. Hence, the main objective of this chapter is to propose a design method that simultaneously builds a low power design and provides a faster circuit. For the achievement of that purpose, a controller based on a finite state machine (FSM) has been chosen as an example of synchronous system to prove that the new proposed design can optimize both parameters: time and power.
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Datta, Debasish. "SONET/SDH, OTN, and RPR." In Optical Networks. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780198834229.003.0005.

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With the emergence of high-speed optical transmission, the pre-existing plesiochronous digital hierarchy (PDH) appeared unsuitable for achieving network synchronization, leading to the development of the synchronous optical network (SONET) and synchronous digital hierarchy (SDH) as the two equivalent standards for circuit-switched optical networks. Several bandwidth-efficient techniques were also developed to carry packet-switched data traffic over SONET/SDH networks, offering some useful data-over-SONET/SDH architectures. Subsequently, with the increasing transmission rates for SONET/SDH and Ethernet-based LANs, a convergent networking platform called optical transport network (OTN), was developed. With the ever-increasing volume of bursty data traffic, a standard for packet-switched ring networks, called resilient packet ring (RPR), was also developed for better bandwidth realization in optical fibers. In this chapter, we first present the SONET/SDH networks and the techniques for supporting the data traffic therein, followed by a description of the basic concepts and salient features of the OTN and RPR networks. (147 words)
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Conference papers on the topic "Digital synchronous circuits"

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Roubicek, Tomas, and Stanislav Dado. "Digital oscillator circuit using synchronous pulse driving." In 2008 15th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2008). IEEE, 2008. http://dx.doi.org/10.1109/icecs.2008.4674895.

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Sakallah, Karem A., Trevor N. Mudge, and Oyekunle A. Olukotun. "Analysis and design of latch-controlled synchronous digital circuits." In Conference proceedings. ACM Press, 1990. http://dx.doi.org/10.1145/123186.123237.

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Andrew, R. "On the power consumption of multiphase synchronous circuits." In IEE Colloquium on `Low Power Analogue and Digital VLSI: ASICS, Techniques and Applications'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950788.

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Martorell, Ferran, Marc Pons, Antonio Rubio, and Francesc Moll. "Error probability in synchronous digital circuits due to power supply noise." In 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era. IEEE, 2007. http://dx.doi.org/10.1109/dtis.2007.4449513.

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Watanabe, Takamoto, and Tomohito Terasawa. "All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection." In 2010 17th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2010). IEEE, 2010. http://dx.doi.org/10.1109/icecs.2010.5724630.

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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit
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Oliveira, Duarte L., Thiago Curtinhas, Diego Bompean, Luiz S. Ferreira, and Leonardo Romano. "Synthesis of synchronous digital systems operating in double-edge of clock." In 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS). IEEE, 2012. http://dx.doi.org/10.1109/lascas.2012.6180347.

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Ravanshad, Nassim, Hamidreza Rezaee-Dehsorkh, and Reza Lotfi. "A fully-synchronous offset-insensitive level-crossing analog-to-digital converter." In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2016. http://dx.doi.org/10.1109/mwscas.2016.7870108.

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Hanken, Christopher, Jim Le, Terri S. Fiez, and Kartikeya Mayaram. "Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits." In 2007 IEEE 29th Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405860.

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Gui, Ping, Fouad Kiamilev, Xiaoqing Wang, et al. "Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35202.

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Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers wit
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Reports on the topic "Digital synchronous circuits"

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Malis, A., P. Pate, and D. Zelig. Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) Circuit Emulation over Packet (CEP). Edited by R. Cohen. RFC Editor, 2007. http://dx.doi.org/10.17487/rfc4842.

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Malis, A., J. Brayley, J. Shirron, L. Martini, and S. Vogelsang. Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) Circuit Emulation Service over MPLS (CEM) Encapsulation. RFC Editor, 2008. http://dx.doi.org/10.17487/rfc5143.

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Zelig, D., R. Cohen, and T. Nadeau, eds. Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) Circuit Emulation over Packet (CEP) MIB Using SMIv2. RFC Editor, 2011. http://dx.doi.org/10.17487/rfc6240.

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