Log in

Relevant bibliographies by topics / DIGITAL SYSTEM DESIGN TEST AND VERIFICATION / Dissertations / Theses

To see the other types of publications on this topic, follow the link: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION.

Dissertations / Theses on the topic 'DIGITAL SYSTEM DESIGN TEST AND VERIFICATION'

Author: Grafiati

Published: 14 March 2023

Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 25 dissertations / theses for your research on the topic 'DIGITAL SYSTEM DESIGN TEST AND VERIFICATION.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

VALLERO, ALESSANDRO. "Cross layer reliability estimation for digital systems." Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2673865.

Full text

Abstract:

Forthcoming manufacturing technologies hold the promise to increase multifuctional computing systems performance and functionality thanks to a remarkable growth of the device integration density. Despite the benefits introduced by this technology improvements, reliability is becoming a key challenge for the semiconductor industry. With transistor size reaching the atomic dimensions, vulnerability to unavoidable fluctuations in the manufacturing process and environmental stress rise dramatically. Failing to meet a reliability requirement may add excessive re-design cost to recover and may have

APA, Harvard, Vancouver, ISO, and other styles

2

Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.

Full text

Abstract:

The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the fun

APA, Harvard, Vancouver, ISO, and other styles

3

Kim, Seokjin. "High-speed analog-to-digital converters for modern satellite receivers design verification test and sensitivity analysis /." College Park, Md.: University of Maryland, 2008. http://hdl.handle.net/1903/7864.

Full text

Abstract:

Thesis (Ph. D.) -- University of Maryland, College Park, 2008.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

APA, Harvard, Vancouver, ISO, and other styles

4

Bougan, Timothy B. "Flexible Intercom System Design for Telemetry Sites and Other Test Environments." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611449.

Full text

Abstract:

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Testing avionics and military equipment often requires extensive facilities and numerous operators working in concert. In many cases these facilities are mobile and can be set up at remote locations. In almost all situations the equipment is loud and makes communication between the operators difficult if not impossible. Furthermore, many sites must transmit, receive, relay, and record telemetry signals. To facilitate communication, most telemetry and

APA, Harvard, Vancouver, ISO, and other styles

5

Ruddy, Marcus A. "Pico-Satellite Integrated System Level Test Program." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/688.

Full text

Abstract:

Testing is an integral part of a satellite’s development, requirements verification and risk mitigation efforts. A robust test program serves to verify construction, integration and assembly workmanship, ensures component, subsystem and system level functionality and reduces risk of mission or capability loss on orbit. The objective of this thesis was to develop a detailed test program for pico-satellites with a focus on the Cal Poly CubeSat architecture. The test program established a testing baseline from which other programs or users could tailor to meet their needs. Inclusive of the tes

APA, Harvard, Vancouver, ISO, and other styles

6

Aalto, Alve, and Ali Jafari. "Automatic Probing System for PCB : Analysis of an automatic probing system for design verification of printed circuit boards." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174865.

Full text

Abstract:

The purpose of this thesis is to conduct an analysis of whether the printed circuit boards from Ericsson can be tested using an automatic probing system or what changes in the design are required, to be a viable solution. The main instrument used for analyzing the printed circuit board was an oscilloscope. The oscilloscope was used to get the raw data for plotting the difference between the theoretical and actual signals. Connected to the oscilloscope was a 600A-AT probe from LeCroy. The programs used for interpreting the raw data extracted from the oscilloscope included Python, Matlab and Exc

APA, Harvard, Vancouver, ISO, and other styles

7

Ioannides, Charalambos. "Investigating the potential of machine learning techniques for feedback-based coverage-directed test genreation in simulation-based digital design verification." Thesis, University of Bristol, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.618315.

Full text

Abstract:

A consistent trend in the semiconductor industry has been the increase of embedded functionality in new designs. As a result, the verification process today requires significant resources to cope with these increasingly complex designs. In order to alleviate the problem, industrialists and academics have proposed and improved on many formal, simulation-based and hybrid verification techniques. To dale, none of the approaches proposed have been ab le to present a convincing argument warranting their unconditional adoption by the industry. In an attempt to further automate design verification (D

APA, Harvard, Vancouver, ISO, and other styles

8

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

Full text

Abstract:

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expen

APA, Harvard, Vancouver, ISO, and other styles

9

Qiang, Qiang. "FORMAL a sequential ATPG-based bounded model checking system for VLSI circuits /." online version, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=case1144614543.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.

Full text

Abstract:

HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the te

APA, Harvard, Vancouver, ISO, and other styles

11

Norberg, Johan. "Verification techniques in the context of event-trigged soft real-time systems." Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-737.

Full text

Abstract:

<p>When exploring a verification approach for Komatsu Forest's control system regarding their forest machines (Valmet), the context of soft real-time systems is illuminated. Because of the nature of such context, the verification process is based on empirical corroboration of requirements fulfillment rather than being a formal proving process.</p><p>After analysis of the literature with respect to the software testing field, two paradigms have been defined in order to highlight important concepts for soft real-time systems. The paradigms are based on an abstract stimuli/response model, which c

APA, Harvard, Vancouver, ISO, and other styles

12

Cameron, Alan, Tony Cirineo, and Karl Eggertsen. "The Family of Interoperable Range System Transceivers (First)." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611408.

Full text

Abstract:

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>The objective of the FIRST project is to define a modern DoD Standard Datalink capability. This defined capability or standard is to provide a solution to wide variety of test and training range digital data radio communications problems with a common set of components, flexible to fit a broad range of applications, yet be affordable in all of them. This capability is to be specially designed to meet the expanding range distances and data transmission

APA, Harvard, Vancouver, ISO, and other styles

13

Cosgrove, S. J. "Expert system technology applied to the testing of complex digital electronic architectures : TEXAS; a synergistic test strategy planning and functional test pattern generation methodology applicable to the design, development and testing of complex digit." Thesis, Brunel University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234077.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Pellegrino, Gregory S. "Design of a Low-Cost Data Acquisition System for Rotordynamic Data Collection." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/1978.

Full text

Abstract:

A data acquisition system (DAQ) was designed based on the use of a STM32 microcontroller. Its purpose is to provide a transparent and low-cost alternative to commercially available DAQs, providing educators a means to teach students about the process through which data are collected as well as the uses of collected data. The DAQ was designed to collect data from rotating machinery spinning at a speed up to 10,000 RPM and send this data to a computer through a USB 2.0 full-speed connection. Multitasking code was written for the DAQ to allow for data to be simultaneously collected and transferre

APA, Harvard, Vancouver, ISO, and other styles

15

Garcia-Mardambek, Nouar. "Etude d'une stratégie de maintenance adaptative pour des systèmes logiques." Grenoble INPG, 1991. http://www.theses.fr/1991INPG0076.

Full text

Abstract:

La complexité des équipements numériques entraîne une difficulté croissante des tâches de vérification de ces équipements tout au long de leur vie: conception, production, industrialisation et maintenance. Chacune de ces étapes induit des modes de défaillances spécifiques et nécessite des méthodes de vérification adaptées. Alors que des méthodes et outils de génération de test ont été développés pour les étapes de conception et production, les vérifications en phase opérationnelle sont restées très empiriques, et font largement appel à l'expertise des ingénieurs de maintenance. C'est pourquoi

APA, Harvard, Vancouver, ISO, and other styles

16

Yang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.

Full text

Abstract:

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can fram

APA, Harvard, Vancouver, ISO, and other styles

17

TAI, YU-FENG, and 戴裕峰. "A Design of Digital Signature Based Application Verification System." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77f278.

Full text

Abstract:

碩士<br>國立高雄應用科技大學<br>資訊管理研究所碩士班<br>105<br>With the fast development of Internet and the widely adoptions of intelligent devices, APPs (Applications) have being playing a more and more role in our life. However, there may be hidden risks that threatens us when using APPs. Malicious applications may hide in third-party applications, especially in those applications with anonymous developers. Sometimes, malicious programs may be developed by using official Application Programming Interface (API). Malicious programs may also be developed by illegal way such as de-compiler. Taking information securi

APA, Harvard, Vancouver, ISO, and other styles

18

Peng, Chien-huan, and 彭健桓. "Design and Implementation of an FPGA-based Verification System for the Built-In Self-Test Circuits of Logic Arrays." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/yudbt8.

Full text

Abstract:

碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>This thesis is related to the design and implementation of an FPGA-based verification system for the BIST (Built-In Self-Test) circuits of logic arrays. The related research work includes four parts: The first part is to explore the architecture for the verification system of the BIST circuits. After analyzing the BIST system, circuit under test, and fault injection methods, a verification system for the BIST circuits of logic arrays has been developed. The second part is to design and implement the hardware for the BIST verification system of logic arrays. T

APA, Harvard, Vancouver, ISO, and other styles

19

Chien-HongLin and 林建宏. "Autonomous Hovering Controller Design Using Sliding Mode Control Theory and Its Flight Test Verification for Small-scaled Unmanned Helicopter System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/46054056125287266943.

Full text

Abstract:

博士<br>國立成功大學<br>航空太空工程學系碩博士班<br>99<br>Unmanned helicopter has been demanding for certain applications due to its unique flight capability. The unmanned helicopter can take off and land within a limited space and it can hover and cruise at a very low speed. The autonomous hovering is one of the most significant flight maneuvering conditions for an unmanned helicopter and offers an unmanned helicopter a wide variety of applications. Thus, an autonomous hovering controller design based on sliding mode control (SMC) theory and its flight test verification for a small-scaled unmanned helicopter

APA, Harvard, Vancouver, ISO, and other styles

20

Mahapatra, Ipsita Biswas. "A Novel Algorithm-Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/5291.

Full text

Abstract:

In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional verification has been pre-dominantly performed through simulation of a DUT. However, their execution speed rapidly degrades when DUT size reaches 100 million gates. To overcome this bottleneck, the EDA industry is increasingly adopting “hardware-accelerated simulation platforms”, which are classified as simulation-accelerators, emulators and FPGA prototypes. Thes

APA, Harvard, Vancouver, ISO, and other styles

21

Surendran, Sudhakar. "A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs." Thesis, 2006. https://etd.iisc.ac.in/handle/2005/397.

Full text

Abstract:

SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Veriﬁcation is one of the important stages in designing an SoC. Veriﬁcation is the process of checking if the transformation from architectural speciﬁcation to design implementation is correct. Veriﬁcation involves creating the following components: (i) a testplan that identiﬁes the conditions to be veriﬁed, (ii) a testcase that generates the stimuli to verify the conditions identiﬁed, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Veriﬁcatio

APA, Harvard, Vancouver, ISO, and other styles

22

Surendran, Sudhakar. "A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs." Thesis, 2006. http://hdl.handle.net/2005/397.

Full text

Abstract:

SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Veriﬁcation is one of the important stages in designing an SoC. Veriﬁcation is the process of checking if the transformation from architectural speciﬁcation to design implementation is correct. Veriﬁcation involves creating the following components: (i) a testplan that identiﬁes the conditions to be veriﬁed, (ii) a testcase that generates the stimuli to verify the conditions identiﬁed, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Veriﬁcation

APA, Harvard, Vancouver, ISO, and other styles

23

Pannell, Zachary William. "Design of a Highly Constrained Test System for a 12-bit, 16-channel Wilkinson ADC." 2009. http://trace.tennessee.edu/utk_gradthes/549.

Full text

Abstract:

Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed th

APA, Harvard, Vancouver, ISO, and other styles

24

Lata, Kusum. "Formal Verification Of Analog And Mixed Signal Designs Using Simulation Traces." Thesis, 2010. https://etd.iisc.ac.in/handle/2005/1271.

Full text

Abstract:

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal des

APA, Harvard, Vancouver, ISO, and other styles

25

Lata, Kusum. "Formal Verification Of Analog And Mixed Signal Designs Using Simulation Traces." Thesis, 2010. http://etd.iisc.ernet.in/handle/2005/1271.

Full text

Abstract:

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal des

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!