Dissertations / Theses on the topic 'Diode-clamped'

This thesis describes an investigation of three and five level diode clamped inverters for motor drive applications. The work was completed as a PhD project at the University of Nottingham with funding from EPSRC and Heenan Drives Ltd. The investigation of the three level converter describes the design, development, control and operation of an 11kW prototype. Included in the design is a review of typical switching strategies employed for control of the output voltage. New improvements to the sub-harmonic pulse width modulation method are presented which allow an improved output waveform to be obtained. The problem of DC link capacitor voltage balancing (Neutral Point Control) is addressed and a novel balancing control method is presented based on the addition of a DC offset to the modulation pattern. This method is verified through mathematical analysis and experimental operation. The operational limits of the control are analysed. Improvements to the technique are presented to expand its operating limits. The development of a prototype five level converter is then described. The design again features improvements to the sub-harmonic modulation strategy to provide enhanced output waveform generation, particularly for transient operation. The current demands on the DC link capacitors for the five level arrangement are analysed and it is concluded that the capacitors cannot be regulated by simple modifications to the output switching pattern. A novel circuit is presented to achieve capacitor balancing within the DC link. The circuit behaviour is described and analysed. Operation is confirmed through simulation and experimental implementation. High dynamic performance is demonstrated via the use of a vector controlled induction motor. Neutral point control is successfully achieved through a similar method to that used for the three level inverter. Having demonstrated the principle of operation of the three and five level inverters on low voltage prototypes, the thesis concludes with a review of the main considerations required to implement the configurations as medium voltage drives.

A constant frequency diode-clamped series resonant power converter (CFCSRC) is proposed as a solution to problems associated with frequency-controlled resonant converters. This converter has two resonant frequencies, and control is achieved by varying the relative time per switching cycle spent at each resonant frequency. Two zero-current-switching (ZCS) modes are examined and plotted in the output plane. Operating and mode boundaries are found and also plotted in the output plane. The output equation for the main mode is shown to be hyperbolic. Peak voltages are shown to be less than or equal to the input voltage, and peak currents are shown to be less than those of the frequency-controlled diode-clamped series resonant converter over a large operating range. A design procedure is given in the form of a design example. Data from a prototype converter is plotted with theoretical data in the output plane and good agreement with the theoretical model is obtained.

Las topologías de convertidores multinivel han recibido una atención especial durante las dos últimas décadas debido a sus notables ventajas en aplicaciones de alta potencia y media/alta tensión. En estas topologías, y comparadas con el convertidor tradicional de dos niveles, el voltaje que soporta cada dispositivo semiconductor es menor, evitando los problemas asociados con la interconexión serie de dispositivos. La distorsión armónica en la tensión de salida es también menor y la eficiencia mayor. Pero incorporan un número superior de dispositivos semiconductores y la estrategia de modulación resultante es, por tanto, más compleja.
Entre estas topologías, el convertidor cc-ca de tres niveles trifásico con conexión al punto neutro del bus de cc es probablemente el más popular. La aplicación a este convertidor de técnicas de modulación convencionales causa una oscilación de la tensión del punto neutro de baja frecuencia (tres veces la frecuencia fundamental de la tensión de salida). Esta oscilación, a su vez, supone un incremento del estrés de tensión de los dispositivos y provoca la aparición de armónicos de baja frecuencia en la tensión de salida.
Esta tesis presenta una nueva técnica de modulación del pulso de conducción de los dispositivos semiconductores para convertidores de tres niveles trifásicos con conexión a punto neutro, capaz de conseguir un control completo de la tensión del punto neutro con una distorsión armónica reducida en la tensión de salida alrededor de la frecuencia de conmutación. Esta nueva técnica de modulación, basada en la definición de unos vectores espaciales virtuales, garantiza el equilibrado de la tensión del punto neutro con cualquier carga (lineal o no, cualquier factor de potencia) y para todo el rango de tensión de salida, con el único requisito de que la suma de corrientes de fase sea nula.
Las características de la técnica de modulación propuesta y sus beneficios con respecto a otras modulaciones se han verificado a través de simulaciones y experimentos tanto en lazo abierto como en lazo cerrado.
Multilevel converter topologies have received special attention during the last two decades due to their significant advantages in high-power medium- and high-voltage applications. In these topologies, and compared to the previous two-level case, the voltage across each semiconductor is reduced, avoiding the problems of the series interconnection of devices. The harmonic distortion of the output voltage is also diminished and the converter efficiency increases. But a larger number of semiconductors is needed and the modulation strategy to control them becomes more complex.
Among these topologies, the three-level three-phase neutral-point-clamped voltage source inverter is probably the most popular. The application of traditional modulation techniques to this converter causes a low frequency (three times the fundamental frequency of the output voltage) oscillation of the neutral-point voltage. This, in turn, increases the voltage stress on the devices and generates low-order harmonics in the output voltage.
This thesis presents a novel pulsewidth modulation for the three-level three-phase neutral-point-clamped converter, able to achieve a complete control of the neutral-point voltage while also having a low output voltage distortion at around the switching frequency. The new modulation, based on a virtual space vector concept, guarantees the balancing of the neutral-point voltage for any load (linear or nonlinear, any load power factor) over the full range of converter output voltage, the only requirement being that the addition of the output three-phase currents equals zero.
The performance of this modulation approach and its benefits over other previously proposed solutions are verified through simulation and experiments in both open- and closed-loop converter configurations.

This thesis offers a novel topology for the implementation of a shunt STATCOM based on a grouping of four 3-level, diode-clamped converters, switching at line frequency and coupled to the ac system through wye/wye and wye/delta phase-shifting transformers.
The advantages include direct voltage control through the gating pattern and the reduced size of the do capacitor. The dominant harmonic on the ac side is the 11th and on the do side, the 12th. The proposed STATCOM can meet Total Harmonic Distortion (THD) requirements.
The operation principles of the proposed STATCOM are described. Harmonics management on both ac side and do side is explained. The concepts in this thesis have been proven by power system simulation software, PSCAD/EMTDC.

Switch mode auxiliary circuits have been used to balance the de-link capacitor voltages of a diode-clamped five-level inverter. The use of the smps has been extended to charge- lip and discharge the four de-link capacitors. Complete diode-clamped five-level inverter operation has been implemented from inverter start-up, to link charge-up, to balanced pwm operation, to de-link discharge, and shut-down. The diode-clamped smps is used to charge and boost the two lower de-link capacitors simultaneously. Auxiliary circuit and boost converter duty cycles are used to control the de-link charge-up and discharge times. Ramped start of a controlled rectifier is used 'to limit the lowest link capacitor inrush current. Matlab and PSpice models are developed for the proposed auxiliary circuit capacitor voltage balancing and de-link charge-up and discharge techniques. Effective practical techniques are presented to bring the diode-clamped multilevel inverter on-line, ensure de-link capacitor balanced voltage operation, and take the inverter off-line to a discharged state.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
This dissertation deals with modulation techniques for multilevel diode clamped converters. The major challenge to be overcome by modulation strategies to these converters is the balance of the dc-link voltage capacitors, whilst minimizing the THD of output voltages. Among the modulation strategies reported in literature for this purpose are the carrier-based and space vector modulation techniques. Generally the space vetor methods select the nearest three vector to implement the desired output voltage vector. However, it is not always possible to remove the low frequency ripple in the dc-link voltage capacitors using this diagram vector. This work proposes a new space vector diagram that allows the elimination of the low frequency ripple in the dc-link voltage capacitors and guarantees the balance to the entire converter linear operation region, operating with any power factor load. Further constrains are derived based on the sign and magnitude of the output currents to determine the transition between the space vector diagram N3V and NS3V, making a hybrid modulation. As a result is possible to minimize the total harmonic distortion of the output voltages and to ensure the control of the averaged neutral point current. In order to make it possible to extend the results for converters with any number of levels, a carrier based modulation was proposed in this work where the modulation signals are chosen to ensure maximum use of the dc-link of the linear range of operation of converter, and eliminate low-frequency oscillation in the voltage capacitors. Moreover, it is proposed a space vector modulation strategy to back-to-back three level diode clamped converters, with the purpose to connect the wind power generation to the grid. This technique combines the utilization of the N3V and NS3V space vector diagrams for both converters connected to the same dc-link. Thus it is possible to establish a trade off between oscillation in the voltage capacitors and THD of output voltages. Experimental results and benchmarks are presented and demonstrate the good performance of the proposed methods.
Esta dissertação de mestrado trata de estratégias de modulação para conversores multiníveis com diodos de grampeamento. O principal desafio a ser superado por técnicas de modulação aplicadas a estes conversores é o de equilibrar as tensões dos capacitores do barramento CC, enquanto que minimizando a penalização da THD das tensões de saída. Dentre as principais estratégias de modulação com esse propósito abordadas na literatura, são as estratégias baseadas na comparação com portadora e as estratégias vetoriais. Geralmente os métodos de modulação vetorial utilizam os três vetores de comutação mais próximos do vetor de tensão de referência, N3V. Entretanto nem sempre é possível eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores do barramento CC em toda faixa de operação do conversor utilizando essa divisão de setores. Este trabalho deriva um novo diagrama vetorial NS3V, que possibilita a eliminação das ondulações de baixa frequência das tensões dos capacitores do barramento CC na região linear do conversor, independente do fator de potência de operação. Além disso são obtidas restrições baseadas no sinal e nas magnitudes das correntes de saída para determinar a transição entre a modulação que utiliza o diagrama vetorial N3V e o diagrama vetorial NS3V, tornando a modulação híbrida. Com isto é possível minimizar a distorção harmônica das tensões de saída e assegurar o controle da corrente média sobre um período de comutação no ponto central do divisor capacitivo. Com objetivo de facilitar a extensão dos resultados para um número qualquer de níveis, a modulação baseada na comparação com portadora foi proposta nesse trabalho onde as tensões modulantes são escolhidas de forma a garantir a máxima utilização da tensão do barramento CC na faixa linear de operação do conversor, bem como eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores. Ainda, é proposta uma estratégia de modulação vetorial para conversores com diodos de grampeamento de três níveis em configuração back-toback com o propósito de conectar sistemas de geração eólica à rede. Nesta estratégia de modulação é combinada a utilização dos diagramas vetoriais N3V e NS3V para ambos os conversores conectados ao mesmo barramento CC. Dessa forma é possível estabelecer um compromisso entre ondulação das tensões dos capacitores do barramento CC e THD das tensões de saída. Resultados experimentais e análises comparativas são apresentadas e demonstram a boa performance dos métodos propostos.

This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.

碩士
國立臺北科技大學
機電整合研究所
94
The purpose of this thesis is to develop the control technique for three-level inverter. In this thesis a new pulse-width modulation technique is proposed which provides voltage balance between two DC-link capacitors while reducing the harmonic contents as compared to the existing method. The presented technique is to divide the reference voltage vector into six regions rather than four regions for conventional method. The presented method requires voltage sensor only and can be realized based upon space vector modulation. The presented technique is verified by both simulation and experimental results. The simulation results are derived from Matlab®/Simulink® software. And the experimental results are derived from an induction drive controlled by digital signal processor. It will be shown that the simulation results agree with experimental results very well and confirming the performance of the presented control technique for three-level inverter.

碩士
國立雲林科技大學
電機工程系碩士班
89
The widespread use of solid-state converters have resulted in many power quality issues such as harmonic distortion in the line current, low power factor, low efficiency and voltage flicker, etc. In this thesis, a multilevel pulse width modulation (PWM) converter which is suitable for high voltage / high power applications is proposed. With the advantages of low voltage harmonic distortion, low EMI, low voltage rating of the switching devices, power reversible, easy implementation and reduction in size and weight, the proposed neutral point diode clamped power converter was applied to the following applications: power factor correction, active power filter, voltage regulator and on line uninterruptible power supply. The simulation (based on Matlab/Simulink) and experimental results are presented. The author employed the TMS320C240 EVM board with some expanded peripheral circuit to realize the modular control circuit. The results revealed that the adopted multilevel technology has the characteristics of high power factor, and high efficiency, and can be used in the medium voltage and high power applications.

碩士
國立臺灣科技大學
電機工程系
107
In this thesis, a three-level diode clamped rectifier energized by non-ideal three-phase power source is studied to improve the line current quality. Both unbalance and harmonics consisted in the ac source are under considered. The ac voltage source is analyzed by Fast Fourier Transform (FFT) which is built in the proposed controller to achieve the on-line calculation of the magnitudes and phases of fundamental and harmonic composition. The three-phase fundamental components obtained from the FFT are used to generate the ideal line current command to achieve high quality line currents which will be evaluated by total harmonic distortion, power factor, and current unbalanced factor. A digital controller based on digital signal processor is adopted in the proposed three-level diode clamped rectifier to deal with the proposed controller which includes the following issues, the mentioned FFT, power factor controller, output dc voltage regulator controller, current controller, sinusoidal pulse width modulation(SPWM), and so on. The above-mentioned analysis results will through the current control loop to generate the three-phase input current compensatory command and control input current magnitude. Afterwards, adopting SPWM to generate switch signal, in this way, it can obtain the improved and modulated three-phase input current. Consequently, the proposed control scheme can solve the problems like non-ideal input current and increased capacitance voltage ripple caused by the input grid voltage under the non-ideal conditions. Hence, the performance of converter will finally evaluate in terms of near unity power factor, low input current unbalance factor and total harmonic distortion (THD) and reduced ripple factor of capacitance voltage. The control scheme of this thesis using MATLAB/SIMULINK simulation software to prove, the experiment establishes a 750VDC/2kW three-level NPC rectifier and employ DSP TMS320F28069 as central controller to implementation. Simulation and experiment results shows in this thesis.

碩士
國立臺灣科技大學
電機工程系
104
In this thesis, a stand-alone single-phase diode-clamped five-level inverter is studied and implemented. This prototype circuit makes the input voltage shared by series-connected switching devices. Besides, this topology needs clamped diodes to clamp the voltage on the MOSFETs. Although the output voltage harmonics of five-level inverter are much lower than those of three-level or square wave output inverters, a second-order low pass filter is still necessary to attenuate the switching harmonics. On the other hand, the control signals of the power devices are generated by sinusoidal pulse-width-modulation (SPWM). The desired output voltage can be modulated by the amplitude modulation index; while the frequency modulation index as well as the sampling period will influence the distortion factor of the output waveform. The circuit operation naturally causes the input capacitor voltages unbalance. Accordingly, a switched-capacitor charge equalization technique is implemented to solve the imbalance problem. A prototype circuit with the switched-capacitor equalizer has been built and tested successfully in this thesis. The circuit is with rated power of 630 W, 800 V input voltage, and 230 V output voltage. A digital-signal processor chip is used to realize the controller of this inverter. The measured efficiency is always higher than 90% within the overall range of load conditions.

碩士
國立臺灣科技大學
電機工程系
106
In response to the growing demand for medium and high power trends, multilevel voltage source converters (VSCs) have been attracting growing considerations. One of the widely used VSCs are the diode clamped multilevel VSC (DCM-VSC). As these converters proliferate, their harmonic impact may become significant. Nevertheless, a harmonic model for the DCM-VSC is currently lacking in the literature. In this paper, the ABCD matrix, mapping the input harmonics to the output harmonics of DCM-VSC is derived. As the matrix is formulated in the time-domain, the output harmonics are exact and do not suffer from harmonic truncation errors. As the paper will demonstrate, the derived ABCD matrix can be easily applied to a microgrid system and users can easily predicts all the uncharacteristic harmonics when a microgrid is subjected to various conditions of imbalance. In addition to all the results being validated with those of PSCAD/EMTDC, the computation time of the proposed method is in contrast much shorter.

碩士
國立臺北科技大學
電力電子產業研發碩士專班
95
The purpose of this thesis is to design and realize a diode-clamped three-level inverter with neutral-point voltage balance. The harmonic contents of output voltage of three-level inverters are less than those for two-level inverters. However, diode-clamped three-level inverter has the problem of neutral point voltage balance. This thesis uses two control methods to balance the voltage of DC-link capacitors and reduce the total harmonic distortion of output waveforms. The simulation results are derived from Matlab®/Simulink® software. The experimental results are derived from an induction motor drive controlled by digital signal processor. It will be shown that the simulation results and experimental results confirm the performance of the control methods for neutral point voltage balance in diode-clamped three-level inverters.

碩士
清雲科技大學
電機工程研究所
93
This paper describes the theory, design, and implementation of a neutral point voltage control for a three level inverter drive system. To reduce the harmonic content of the output voltage and decrease the switch loss, the 3-level inverter is highest importance in the high power application, particularly. When the semiconductor devices are not able to operate at high switch frequency to reduce the harmonic of the output voltage, the 3-level structure is a good choose to solve this problem. Another advantage of the 3-level inverter is that the normal rated voltage of the switch devices can reduce 50%, which can cost down the inverter system. But, there are some difficulties to overcome in the 3-level inverter, the most challenge problem is the neutral-point voltage drift, which not only increase the output voltage harmonic but also make the voltage ratings of each switch device different. In this paper, we use the harmonic injection Sine-PWM to produce the control signals of the inverter. Then, derive the relationship between the neutral-point voltage and the modulation voltage and design a controller to balance the neutral-point voltage. Experiment results show the proposed method can improve the problems of 3-level inverter.

碩士
國立臺灣科技大學
電機工程系
106
This thesis proposes an improved unity power factor controller, this controller can improve not only the input current unbalance factor but also the DC-BUS voltage ripple of three-level Neutral Point Clamped (NPC) rectifier works under unbalanced grid source condition. In addition to through the mathematical model of the three-level NPC rectifier and Unity Power Factor controller, we can get the relationship between input current, neutral point voltage and DC-BUS voltage. Hence, as long as we get the mathematical relations, it can be used to balance the neutral point voltage and reduce the neutral point voltage without using neutral point current sensor. The control scheme of this thesis uses MATLAB/SIMULINK simulation software to prove. The experiment establish a 750VDC/2kW, power factor 0.99 of three-level NPC rectifier, and employ digital signal processor TMS320F28069 as a controller to implement, simulation and experiment results shows in this thesis.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

Dissertação de mestrado integrado em Engenharia Eletrónica e de Computadores
A exigência na qualidade da forma de onda sintetizada pelos inversores de eletrónica de potência é cada vez maior, estando esta qualidade associada a um melhor funcionamento e a um maior tempo de vida por parte das cargas e sistemas associados aos inversores. A melhoria na qualidade das formas de onda geradas pelos inversores tem sido conseguida maioritariamente através do aumento da frequência de comutação dos semicondutores. Esta estratégia provoca perdas de comutação mais elevadas, maior stress aplicado ao semicondutor e um aumento das interferências eletromagnéticas. Outro método que começa a ser utilizado para melhorar a qualidade das formas de onda dos inversores é o aumento do número de níveis na forma de onda gerada à saída. Este método utiliza inversores com topologias multinível, podendo aumentar a qualidade das formas de onda produzidas sem as desvantagens da utilização de uma frequência de comutação muito alta. Inicialmente o uso dos inversores multinível era limitado a aplicações de tensões muito elevadas, devido ao custo elevado dos semicondutores e ao baixo poder de processamento dos controladores digitais existentes. Com a evolução das tecnologias é cada vez mais viável a utilização deste tipo de topologias em aplicações de baixa tensão que necessitam de uma foram de onda com uma distorção mínima. Esta dissertação de mestrado visa o desenvolvimento de um inversor multinível monofásico para uma aplicação de baixa tensão, atribuindo maior foco à qualidade da forma de onda a sintetizar. Para tal, foi escolhida uma aplicação de Qualidade de Energia Elétrica (QEE) nomeadamente um Filtro Ativo de Potência Paralelo (FAPP). A efetividade da compensação por parte do FAPP depende muito da qualidade das correntes sintetizadas. Sendo assim, o principal objetivo é a sintetização de correntes de compensação com elevada qualidade e com baixo ripple. Para tal, foi utilizada uma topologia de cinco níveis, cuja diferença de tensão entre níveis é menor quando comparada com um inversor convencional de 2 níveis, reduzindo assim o ripple da corrente produzida sem necessidade de aumentar os filtros passivos de saída. No decorrer deste trabalho foi realizado um estudo bibliográfico sobre inversores multinível e filtros ativos de potência. Posteriormente, foram realizadas simulações computacionais para validar a topologia a implementar. Por último, foi desenvolvido um protótipo laboratorial e foram realizados testes práticos com diferentes cargas, para comprovar o funcionamento adequado do FAPP.
The quality requirements of the signals synthesized by power inverters are increasing, being this quality associated to a better performance and longer lifetime of the loads and systems related to the inverters. The improvement in the quality of the inverters signal has been achieved by increasing the switching frequency. This strategy leads to high losses, greater stress applied to semiconductor and an increase of electromagnetic interference. Another method that is beginning to be used to improve the quality of the signals produced by power inverters is the increase in the number of levels of the output signals. This method uses inverters with multilevel topologies, allowing increase the quality of the produced signals without the disadvantages of the very high switching frequency. Initially the use of multilevel inverters was limited to high power applications, due to the high cost of semiconductors and low processing power of digital controllers. With the evolution of technologies, the use of multilevel topologies turns out to be more reliable in low voltage applications requiring signals with very low distortion. This dissertation aims at the development of a single-phase multilevel inverter for low-voltage application, giving greater focus to the quality of the synthesized signals. So, a power quality application was chosen, more precisely a Shunt Active Power Filter (SAPF). The effectiveness of a SAPF depends on the quality of the synthesized high quality and low ripple. To accomplish with this requirements, a five-level topology was selected, whose voltage difference between levels is less when compared to a conventional two level inverter, thus reducing the ripple without increasing the output passive filters. Along the work, a bibliographical study on multilevel inverters and active power filters was done. Later, simulations were performed to validate the topology, in order to proceed to its implementation. Finally, a laboratorial prototype has been developed and practical tests were carried out with different loads, to demonstrate the SAPF proper operation.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.