Journal articles: 'Direct Bonded Copper (DBC)'

1

Grzesiak, Wojciech, Piotr Maćków, Tomasz Maj, Beata Synkiewicz, Krzysztof Witek, Ryszard Kisiel, Marcin Myśliwiec, Janusz Borecki, Tomasz Serzysko, and Marek Żupnik. "Application of direct bonded copper substrates for prototyping of power electronic modules." Circuit World 42, no. 1 (February 1, 2016): 23–31. http://dx.doi.org/10.1108/cw-10-2015-0051.

Full text

Abstract:

Purpose – This paper aims to present certain issues in direct bonded copper (DBC) technology towards the manufacture of Al2O3 or AlN ceramic substrates with one or both sides clad with a copper (Cu) layer. Design/methodology/approach – As part of the experimental work, attempts were made to produce patterns printed onto DBC substrates based on four substantially different technologies: precise cutting with a diamond saw, photolithography, the use of a milling cutter (LPKF ProtoMat 93s) and laser ablation with differential chemical etching of the Cu layer. Findings – The use of photolithography and etching technology in the case of boards clad with a 0.2-mm-thick Cu layer, can produce conductive paths with a width of 0.4 mm while maintaining a distance of 0.4 mm between the paths, and in the case of boards clad with a 0.3-mm-thick copper layer, conductive paths with a width of 0.5 mm while maintaining a distance of 0.5 mm between paths. The application of laser ablation at the final step of removing the unnecessary copper layer, can radically increase the resolution of printed pattern even to 0.1/0.1 mm. The quality of the printed pattern is also much better. Research limitations/implications – Etching process optimization and the development of the fundamentals of technology and design of power electronic systems based on DBC substrates should be done in the future. A limiting factor for further research and its implementation may be the relatively high price of DBC substrates in comparison with typical PCB printed circuits. Practical implications – Several examples of practical implementations using DBC technology are presented, such as full- and half-bridge connections, full-wave rectifier with an output voltage of 48 V and an output current of 50 A, and part of a battery discharger controller and light-emitting diode illuminator soldered to a copper heat sink. Originality/value – The paper presents a comparison of different technologies used for the realization of precise patterns on DBC substrates. The combination of etching and laser ablation technologies radically improves the quality of DBC-printed patterns.

APA, Harvard, Vancouver, ISO, and other styles

2

Patterson, Brian, Srikanth Kulkarni, Aicha Elshabini, and Fred Barlow. "Evaluation of Direct Bond Aluminum Substrates for Power Electronic Applications in Extreme Environments." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000012–17. http://dx.doi.org/10.4071/cicmt-2012-ta12.

Full text

Abstract:

Power packages that require large current capacities typically employ some form of thick conductive traces attached to a thermally conductive ceramic material to create a suitable package substrate. The most common substrate currently used in high power applications is Direct Bonded Copper (DBC). Though this is a well established, reliable, and commonly used substrate, DBC suffers from poor long term mechanical reliability when exposed to extreme temperature excursions. In an attempt to improve on this technology, substrate materials such as Active Metal Bond / Braze (AMB) and Direct Bonded Aluminum (DBA) are being investigated. Previous work has shown that the accelerated aging / thermal shock lifetimes of DBC and AMB are significantly shorter than that of DBA substrates. Though DBA substrates last longer, they still have some issues that require attention before it can be accepted as an improved alternative to DBC substrates in these types of applications. The main issues that have been observed are DBA's increase in surface roughness during aging and aluminum's poor solderability when compared to copper or nickel. The emphasis of this paper is to investigate the dramatic increase in DBA's surface roughness and its' possible causes due to thermal cycling as well as present a thermal cycling lifetime comparison of the three different substrate. To evaluate this, a DBA sample with one side raw aluminum and one side electroless nickel plated (high phosphorous) was thermally shocked from −40°C to 200°C with surface roughness measurements preformed every 300 cycles. Another batch of samples was thermally shocked to 6000 cycles and lifetimes were compared. One nickel plated DBA sample shocked to 4000 cycles was cross-sectioned and analyzed with SEM and EDAX to evaluate any changes in the metal. The grain structure of a thermally cycled sample was also examined with a Scanning Electron Microscope (SEM).

APA, Harvard, Vancouver, ISO, and other styles

3

Gundel, Paul, Anton Miric, Kai Herbst, Melanie Bawohl, Jessica Reitz, Christina Modes, Gabriel Zier, Ilias Nikolaidis, and Mark Challingsworth. "Advanced DBC - Highly Reliable and Conductive Copper Ceramic Substrates." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, CICMT (May 1, 2016): 000073–78. http://dx.doi.org/10.4071/2016cicmt-tp2b2.

Full text

Abstract:

Abstract So far Direct Bonded Copper (DBC) substrates have been the standard for power electronics. They provide excellent electrical and thermal conductivity at low cost. Weaknesses of DBC technology are the inevitable warpage and the relatively low reliability under thermal cycling. The low reliability poses a significant hurdle in particular for automotive applications with high lifetime requirements. Thick Print Copper (TPC) substrates with low warpage and excellent reliability overcome these weaknesses, but also provide a reduced conductivity at a higher cost. We present two thick-film/DBC hybrid technologies which combine the best properties of DBC and TPC: excellent conductivity, low cost, reduced warpage and excellent reliability.

APA, Harvard, Vancouver, ISO, and other styles

4

Mei, Yunhui, Guo-Quan Lu, Xu Chen, Chen Gang, Shufang Luo, and Dimeji Ibitayo. "Investigation of Post-Etch Copper Residue on Direct Bonded Copper (DBC) Substrates." Journal of Electronic Materials 40, no. 10 (July 30, 2011): 2119–25. http://dx.doi.org/10.1007/s11664-011-1716-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Persons, Ryan, and Paul Gundel. "Print Copper on Ceramic for High Reliability Electronics." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000330–35. http://dx.doi.org/10.4071/isom-2015-wp12.

Full text

Abstract:

In the power electronics world, Direct Bonded Copper (DBC) is the primary substrate technology. In this paper, we will discuss an alternative technology utilizing screen printable copper pastes (Thick Printed Copper - TPC) on a variety of substrate technologies including Alumina (Al2O3) and Aluminum Nitride (AlN). These materials when processed, look and perform similar to DBC, but exhibit superior reliability and excellent design flexibility. DBC has drawbacks when it comes to thermal mechanical reliability and lacks the flexibility to have multiple copper thicknesses for power and signal circuits within the same design, which is easily achieved via screen printing. The benefits of this TPC system will be demonstrated through data generated on passive thermal shock tests in comparison to high end DBC. Furthermore, this Thick Print Copper technology has the excellent potential for replacing high end Metal Core Printed Circuit Board (MCPCB) technology due to utilization of higher thermal conductive dielectric materials like Al2O3 and AlN. This will allow for designers to drive their LED's harder and effectively producing LED modules with higher power densities.

APA, Harvard, Vancouver, ISO, and other styles

6

Lee, Chung Hyo, Young Sup Lee, Dong Choul Cho, and Chang Hee Lee. "Microstructure and Mechanical Properties of DBC on Sputter Deposited Copper on Alumina Substrate." Materials Science Forum 449-452 (March 2004): 677–80. http://dx.doi.org/10.4028/www.scientific.net/msf.449-452.677.

Full text

Abstract:

The process of Direct Bonding Copper (DBC) is performed by a spinel reaction between CuO and Al2O3. In order to develop DBC on alumina substrate with high bonding strength, alumina substrate was preformed as follows: Cu was sputter-deposited on alumina substrate. Sputter-Deposited Cu (SDC) on alumina substrate was oxidized at 673K for 30min in air atmosphere and then stabilized at 1273K for 30min in N2 gas atmosphere to improve bonding strtrength between preformed alumina substrate and SDC layer. Subsequently, the Cu-foil (300µm) was bonded on preformed-alumina substrate in N2 gas atmosphere at 1342~1345K. It was found that optimum condition of DBC on preformed-alumina substrate could be successfully obtained at 1345K for 30min. Consequently, bonding strength of DBC on alumina substrate was the high value of 80N/cm. Observation and analysis of microstructure for Cu sputtered DBC showed that reaction compounds such as CuAlO2 and CuAl2O4 approved to be formed in the vicinity of interface between Cu and alumina substrate.

APA, Harvard, Vancouver, ISO, and other styles

7

Kim, Dongjin, Yasuyuki Yamamoto, Shijo Nagao, Naoki Wakasugi, Chuantong Chen, and Katsuaki Suganuma. "Measurement of Heat Dissipation and Thermal-Stability of Power Modules on DBC Substrates with Various Ceramics by SiC Micro-Heater Chip System and Ag Sinter Joining." Micromachines 10, no. 11 (October 31, 2019): 745. http://dx.doi.org/10.3390/mi10110745.

Full text

Abstract:

This study introduced the SiC micro-heater chip as a novel thermal evaluation device for next-generation power modules and to evaluate the heat resistant performance of direct bonded copper (DBC) substrate with aluminum nitride (AlN-DBC), aluminum oxide (DBC-Al2O3) and silicon nitride (Si3N4-DBC) ceramics middle layer. The SiC micro-heater chips were structurally sound bonded on the two types of DBC substrates by Ag sinter paste and Au wire was used to interconnect the SiC and DBC substrate. The SiC micro-heater chip power modules were fixed on a water-cooling plate by a thermal interface material (TIM), a steady-state thermal resistance measurement and a power cycling test were successfully conducted. As a result, the thermal resistance of the SiC micro-heater chip power modules on the DBC-Al2O3 substrate at power over 200 W was about twice higher than DBC-Si3N4 and also higher than DBC-AlN. In addition, during the power cycle test, DBC-Al2O3 was stopped after 1000 cycles due to Pt heater pattern line was partially broken induced by the excessive rise in thermal resistance, but DBC-Si3N4 and DBC-AlN specimens were subjected to more than 20,000 cycles and not noticeable physical failure was found in both of the SiC chip and DBC substrates by a x-ray observation. The results indicated that AlN-DBC can be as an optimization substrate for the best heat dissipation/durability in wide band-gap (WBG) power devices. Our results provide an important index for industries demanding higher power and temperature power electronics.

APA, Harvard, Vancouver, ISO, and other styles

8

Molisani, André Luiz, and Humberto Naoyuki Yoshimura. "Intermediate Oxide Layers for Direct Bonding of Copper (DBC) to Aluminum Nitride Ceramic Substrates." Materials Science Forum 660-661 (October 2010): 658–63. http://dx.doi.org/10.4028/www.scientific.net/msf.660-661.658.

Full text

Abstract:

DBC is a process where copper foils are bonded to ceramic substrates for manufacturing hybrid electronic circuits and packages with high power-handling capabilities. For aluminum nitride (AlN) ceramics, a heat-treatment is required to grow an oxide layer to promote the bonding with copper. The oxidation treatment, however, must be conducted in special conditions to avoid the occurrence of severe cracking. In this work, an alternative method is proposed to form an intermediate oxide layers for DBC to AlN substrates. By this method, eutectic powder mixtures (CuO-CaO and CuO-Al2O3 systems) were applied to dense AlN substrates and then heat-treated at 1200 °C for 1 h in air. Different types of AlN ceramics sintered between 1650 and 1700 °C for 4 h in nitrogen atmosphere with additives of the system Y2O3-CaO-SrO-Li2O were investigated. The prepared oxide layers (thickness of ~25 m) presented good microstructural joining with the AlN substrates (characterized by SEM and EDS analysis), and did not affect significantly the thermal conductivity in the working temperature range of electronic devices (~100 to 50 W/m.K determined by laser flash method between 100 and 200 °C) compared to the AlN substrates.

APA, Harvard, Vancouver, ISO, and other styles

9

Ivanova, Mariya, Yvan Avenas, Christian Schaeffer, Jean-Bernard Dezord, and Juergen Schulz-Harder. "Heat Pipe Integrated in Direct Bonded Copper (DBC) Technology for Cooling of Power Electronics Packaging." IEEE Transactions on Power Electronics 21, no. 6 (November 2006): 1541–47. http://dx.doi.org/10.1109/tpel.2006.882974.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Toth Pal, Zsolt, Ya Fan Zhang, Ilja Belov, Hans Peter Nee, and Mietek Bakowski. "Investigation of Pressure Dependent Thermal Contact Resistance between Silver Metallized SiC Chip and DBC Substrate." Materials Science Forum 821-823 (June 2015): 452–55. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.452.

Full text

Abstract:

– Thermal contact resistances between a silver metallized SiC chip and a direct bonded copper (DBC) substrate have been measured in a heat transfer experiment. A novel experimental method to separate thermal contact resistances in multilayer heat transfer path has been demonstrated. The experimental results have been compared with analytical calculations and also with 3D computational fluid dynamics (CFD) simulation results. A simplified CFD model of the experimental setup has been validated. The results show significant pressure dependence of the thermal contact resistance but also a pressure independent part.

APA, Harvard, Vancouver, ISO, and other styles

11

Kang, Hyejun, Ashutosh Sharma, and Jae Pil Jung. "Recent Progress in Transient Liquid Phase and Wire Bonding Technologies for Power Electronics." Metals 10, no. 7 (July 11, 2020): 934. http://dx.doi.org/10.3390/met10070934.

Full text

Abstract:

Transient liquid phase (TLP) bonding is a novel bonding process for the joining of metallic and ceramic materials using an interlayer. TLP bonding is particularly crucial for the joining of the semiconductor chips with expensive die-attached materials during low-temperature sintering. Moreover, the transient TLP bonding occurs at a lower temperature, is cost-effective, and causes less joint porosity. Wire bonding is also a common process to interconnect between the power module package to direct bonded copper (DBC). In this context, we propose to review the challenges and advances in TLP and ultrasonic wire bonding technology using Sn-based solders for power electronics packaging.

APA, Harvard, Vancouver, ISO, and other styles

12

Bach, Hoang Linh, Daniel Dirksen, Christoph Blechinger, Tobias Maximilian Endres, Christoph Friedrich Bayer, Andreas Schletz, and Martin März. "Stackable SiC-Embedded Ceramic Packages for High-Voltage and High-Temperature Power Electronic Applications." Journal of Microelectronics and Electronic Packaging 16, no. 4 (October 1, 2019): 176–81. http://dx.doi.org/10.4071/imaps.952440.

Full text

Abstract:

Abstract This study encompasses the development of a high-voltage and high-temperature–capable package for power electronic applications based on the embedding of silicon carbide (SiC) semiconductor devices in the ceramic circuit carrier such as the direct bonded copper (DBC) substrate. By sealing semiconductor devices into DBC substrates, high temperature, high voltage, and high current capability as well as high corrosion resistance can be achieved compared with the state-of-the-art printed circuit board (PCB) embedding technology. The power devices are attached with high-temperature stable solder and sinter material and are surrounded by thermal conductive ceramic and high-temperature–capable potting materials that enable the complete package to operate at 250°C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of the PCB and low-temperature cofired ceramic–based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future wide bandgap devices. It is a promising solution not only for applications in harsh ambient environments such as aerospace and turbine, geothermal well logging, and downhole oil and gas wells but also for hybrid electric/electric vehicle and energy conversion.

APA, Harvard, Vancouver, ISO, and other styles

13

Bach, Hoang Linh, Daniel Dirksen, Christoph Blechinger, Tobias Maximilian Endres, Christoph Friedrich Bayer, Andreas Schletz, and Martin März. "Stackable SiC Embedded Ceramic Packages for High Voltage and High Temperature Power Electronics Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, HiTen (July 1, 2019): 000028–33. http://dx.doi.org/10.4071/2380-4491.2019.hiten.000028.

Full text

Abstract:

Abstract This paper encompasses the development of a high voltage and high temperature capable package for power electronic applications based on the embedding of SiC (silicon carbide) semiconductor devices in ceramic circuit carrier such as direct bonded copper (DBC) substrate. By sealing the semiconductor devices into DBC substrates, high temperature, high voltage and high current capability as well as high corrosion resistance can be achieved compared to state-of-the-art PCB (printed circuit board) embedding technology. The power devices are attached with high temperature stable solder and sinter material, and are surrounded by thermal conductive ceramic and high temperature capable potting materials that enable the complete package to operate at 250 °C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of PCB and LTCC (low-temperature co-fired ceramic) based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future WBG (wide band-gap) devices. It is a promising solution for applications in harsh ambient environment such as aerospace and turbine, geothermal well logging, down hole-well oil & gas, but also applicable for HEV/EV (hybrid electric/electric vehicle) and energy conversion.

APA, Harvard, Vancouver, ISO, and other styles

14

Yoon, Sang Won, Michael D. Glover, H. Alan Mantooth, and Koji Shiozaki. "Highly Reliable Double-sided Bonding used in Double-sided Cooling for High Temperature Power Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000045–50. http://dx.doi.org/10.4071/hitec-2012-ta23.

Full text

Abstract:

This paper demonstrates the feasibility of double-sided die attachment bonding, a key technology for double-sided cooling structures, using copper-tin transient liquid phase (Cu-Sn TLP) bonding. Recently, double-sided cooling has drawn particular interest by providing a notable improvement in thermal management and increasing allowable power density for automotive power electronics. The use of TLP bonding for double-sided attachment avoids a number of complications in the assembly process, enables multiple attachments, and provides a high bonding quality and reliability at high temperature operation (because of its high re-melting temperature). In addition, Cu-Sn TLP facilitates high thermal and electrical conductivities, which exactly correspond to the aim of double-sided cooling. Cu-Sn TLP bonding is developed using silicon dummy dies and DBC (direct bonded copper) substrates. The feasibility of double-sided Cu-Sn TLP bonding is demonstrated by (1) proof-of-concept fabrication, (2) optical analysis using optical microscopy and SAM, and (3) material identification using SEM and EDX analysis.

APA, Harvard, Vancouver, ISO, and other styles

15

Castillo, H. A., E. Restrepo-Parra, W. De La Cruz, B. Bixbi, and A. Hernandez. "CuO thin films produced for improving the adhesion between Cu and Al2O3 foils in a direct bonded copper (DBC) process." Journal of Adhesion 94, no. 8 (July 24, 2017): 615–26. http://dx.doi.org/10.1080/00218464.2017.1320222.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Myśliwiec, Marcin, Ryszard Kisiel, and Marek Guziewicz. "Material and technological aspects of high-temperature SiC device packages reliability." Microelectronics International 32, no. 3 (August 3, 2015): 143–48. http://dx.doi.org/10.1108/mi-01-2015-0009.

Full text

Abstract:

Purpose – The purpose of this paper is to deal with material and technological aspects of SiC diodes assembly in ceramic packages. The usefulness of combinations of different materials and assembly techniques for the creation of inner connection system in the ceramic package, as well as the formation of outer connections able to work at temperatures up to 350°C, were evaluated. Design/methodology/approach – The ceramic package consists of direct bonded copper (DBC) substrate with Cu pads electroplated by Ni or Ni/Au layers on which a SiC diode was assembled by sintering process using Ag microparticles. For the connections inside the ceramic package, the authors used Al/Ni and Au-Au material system based on aluminium or gold wire bonding. The authors sealed the ceramic package with glass encapsulation and achieved a full encapsulation. Outer connections were manufactured using Cu ribbon plated with Ag layer and sintered to DBC by Ag micro particle. The authors investigated the long-term stability of electrical parameters of SiC diodes assembled in ceramic package at temperature 350°C. Findings – The authors have shown that Schottky and PiN SiC diodes assembled with different technologies and materials in ceramic package keep their I-V characteristics unchanged during ageing at 350°C for 400 h. Originality/value – The SiC diodes assembled into ceramic package with Al/Ni or Au-Au inner electrical connection systems and outer connections system based on Ag microparticles sintering process of Cu/Ag ribbon to DBC substrate can work reliably in temperature range up to 350°C.

APA, Harvard, Vancouver, ISO, and other styles

17

Kulkarni, Srikanth, Shams Arifeen, Brian Patterson, Gabriel Potirniche, Aicha Elshabini, and Fred Barlow. "Evaluation of Ceramic Substrates for High Power and High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, CICMT (September 1, 2011): 000199–206. http://dx.doi.org/10.4071/cicmt-2011-wp11.

Full text

Abstract:

Ceramic substrates with thin film and thick film conductor traces are widely used in microelectronic packages for high temperature operation. In high power applications where the maximum current in the package may be hundreds of amperes, much thicker conductive traces are normally required. For such applications, Direct Bonded Copper (DBC), Direct Bonded Aluminum (DBA) or Active Metal Bonded (AMB) substrates are good candidates. These substrates provide low electrical resistance and high ampacity, thereby enable the design of high power circuits for high temperature operation. The most commonly observed failure mode in these substrates is the delamination of metal layer from the ceramic. The lifetime of a ceramic substrate can be significantly reduced by the processing conditions such as maximum process temperature, and the process gases that the substrates are exposed to. It has also been shown that the propagation of cracks in the ceramic can be abated by dimpling the metal layers along edges and corners. In order to evaluate the effectiveness of these types of substrates for power applications, substrates with various combinations of metal thicknesses and ceramic composition (Al2O3 and AlN) were evaluated for delamination as a function of thermal shock cycles. These samples included both dimpled and non-dimpled metallization. The samples were thermally cycled between −40 °C and 200 °C. A few of these substrates were exposed to forming gas at 340 °C prior to thermal cycling to imitate process conditions. Sample randomization was performed to provide statistically significant data. After a certain number of thermal cycles, delamination cracks were observed to nucleate and propagate in the substrates. Data regarding the reliability of these substrates as a function of thermal shock cycles is presented in this paper, along with failure mechanisms that are commonly observed. Computer simulations were performed to understand the conditions that lead to delamination cracks, and to estimate the crack growth rates in these substrates.

APA, Harvard, Vancouver, ISO, and other styles

18

Cheng, Tzu-Hsuan, Kenji Nishiguchi, Yoshi Fukawa, B. Jayant Baliga, Subhashish Bhattacharya, and Douglas C. Hopkins. "Characterization of Highly Thermally Conductive Organic Substrates for a Double-Sided Cooled Power Module." International Symposium on Microelectronics 2020, no. 1 (September 1, 2020): 000277–81. http://dx.doi.org/10.4071/2380-4505-2020.1.000277.

Full text

Abstract:

Abstract Silicon-Carbide (SiC) power devices have become a promising option for traditional Silicon (Si) due to the superior material properties. To fully take advantage of the SiC devices, a high-performance power device packaging solution is necessary. This study proposes a cost-effective double-sided cooled (DSC) 1.2 kV SiC half-bridge power module using organic epoxy-resin composite dielectric (ERCD) substrates. The high mechanical and thermal performance of the power module is achieved by the low-modulus, moderate thermal conductivity, and relatively thin (120 μm) layer of ERCD material compared with traditional metal-clad ceramic approaches. This novel organic dielectric can withstand high voltage (5 kV @ 120 μm) and operate up to 250°C continuously, which is indispensable for high power applications. The thermal modeling results show that the equivalent thermal resistance junction-to-case (Rjc_eq) of the DSC power module using dual direct bonded copper (DBC) is 17% higher than the dual ERCD configuration. Furthermore, a non-insulated DSC power module concept is proposed for maximizing thermal performance by considering thermal vias in the ERCD substrate and direct-soldered heat sink. A thought process for optimization of thermal via design is demonstrated and it shows up to 24% of improvement on thermal performance compared with the insulated DSC power module.

APA, Harvard, Vancouver, ISO, and other styles

19

Cheng, Tzu-Hsuan, Kenji Nishiguchi, Yoshi Fukawa, B. Jayant Baliga, Subhashish Bhattacharya, and Douglas C. Hopkins. "Thermal and Reliability Characterization of an Epoxy Resin-Based Double-Side Cooled Power Module." Journal of Microelectronics and Electronic Packaging 18, no. 3 (July 1, 2021): 123–36. http://dx.doi.org/10.4071/imaps.1427774.

Full text

Abstract:

Abstract Wide-Band Gap (WBG) power devices have become a promising option for high-power applications due to the superior material properties over traditional Silicon. To not limit WBG devices’ mother nature, a rugged and high-performance power device packaging solution is necessary. This study proposes a Double-Side Cooled (DSC) 1.2 kV half-bridge power module having dual epoxy resin insulated metal substrate (eIMS) for solving convectional power module challenges and providing a cost-effective solution. The thermal performance outperforms traditional Alumina (Al2O3) Direct Bonded Copper (DBC) DSC power module due to moderate thermal conductivity (10 W/mK) and thin (120 mm) epoxy resin composite dielectric working as the IMS insulation layer. This novel organic dielectric can withstand high voltage (5 kVAC @ 120 μm) and has a Glass Transition Temperature (Tg) of 300°C, which is suitable for high-power applications. In the thermal-mechanical modeling, the organic DSC power module can pass the thermal cycling test over 1,000 cycles by optimizing the mechanical properties of the encapsulant material. In conclusion, this article not only proposes a competitive organic-based power module but also a methodology of evaluation for thermal and mechanical performance.

APA, Harvard, Vancouver, ISO, and other styles

20

Zhang, Wenli, Zhengyang Liu, Fred Lee, Shuojie She, Xiucheng Huang, and Qiang Li. "A Gallium Nitride-Based Power Module for Totem-Pole Bridgeless Power Factor Correction Rectifier." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000324–29. http://dx.doi.org/10.4071/isom-2015-wp11.

Full text

Abstract:

The totem-pole bridgeless power factor correction (PFC) rectifier has recently gained popularity for ac-dc power conversion. The emerging gallium nitride (GaN) high-electron-mobility transistor (HEMT), having a small body diode reverse recovery effect and low switching loss, is a promising device for use in the totem-pole approach. The design, fabrication, and thermal analysis of a GaN-based full-bridge multi-chip module (MCM) for totem-pole bridgeless PFC rectifier are introduced in this work. Four cascode GaN devices using the same pair of high-voltage GaN HEMT and low-voltage silicon (Si) power metal-oxide-semiconductor field-effect transistor (MOSFET) chips, as used in the discrete TO-220 package, were integrated onto one aluminum nitride direct-bonded-copper (AlN-DBC) substrate in a newly designed MCM. This integrated power module achieves the same function as four discrete devices mounted on the circuit board. In this module design, the Si and GaN bare die were arranged in a stack-die format for each cascode device to eliminate the critical common source inductance, and thus to reduce parasitic ringing at turn-off transients. In addition, an extra capacitor was added in parallel with the drain-source terminals of the Si MOSFET in each cascode GaN device to compensate for the mismatched junction capacitance between the Si MOSFET and GaN HEMT, which could accomplish the internal zero-voltage switching of the GaN device and reduce its turn-on loss. The AlN-DBC substrate and the flip-chip format were also applied in the module design. This GaN-based MCM shows an improved heat dissipation capability based on the thermal analysis and comparison with the discrete GaN device. The totem-pole bridgeless PFC rectifier built using this integrated power module is expected to have a peak efficiency of higher than 99% with a projected power density greater than 400 W/in3.

APA, Harvard, Vancouver, ISO, and other styles

21

Noh, Seungjun, Hao Zhang, and Katsuaki Suganuma. "Heat-Resistant Microporous Ag Die-Attach Structure for Wide Band-Gap Power Semiconductors." Materials 11, no. 12 (December 12, 2018): 2531. http://dx.doi.org/10.3390/ma11122531.

Full text

Abstract:

In this work, efforts were made to prepare a thermostable die-attach structure which includes stable sintered microporous Ag and multi-layer surface metallization. Silicon carbide particles (SiCp) were added into the Ag sinter joining paste to improve the high-temperature reliability of the sintered Ag joints. The use of SiCp in the bonding structures prevented the morphological evolution of the microporous structure and maintained a stable structure after high temperature storage (HTS) tests, which reduces the risk of void formation and metallization dewetting. In addition to the Ag paste, on the side of direct bonded copper (DBC) substrates, the thermal reliability of various surface metallizations such as Ni, Ti, and Pt were also evaluated by cross-section morphology and on-resistance tests. The results indicated that Ti and Pt diffusion barrier layers played a key role in preventing interfacial degradations between sintered Ag and Cu at high temperatures. At the same time, a Ni barrier layer showed a relatively weak barrier effect due to the generation of a thin Ni oxide layer at the interface with a Ag plating layer. The changes of on-resistance indicated that Pt metallization has relatively better electrical properties compared to that of Ti and Ni. Ag metallization, which lacks barrier capability, showed severe growth in an oxide layer between Ag and Cu, however, the on-resistance showed fewer changes.

APA, Harvard, Vancouver, ISO, and other styles

22

Yahyaee, Ali, Amir Bahman, and Frede Blaabjerg. "A Modification of Offset Strip Fin Heatsink with High-Performance Cooling for IGBT Modules." Applied Sciences 10, no. 3 (February 7, 2020): 1112. http://dx.doi.org/10.3390/app10031112.

Full text

Abstract:

For reliability and thermal management of power devices, the most frequently used technique is to employ heatsinks. In this work, a new configuration of offset strip fin heatsink based on using the concept of curvy fins and U-turn is proposed with the aim of improving the heat transfer performance. With this aim, a three-dimensional model of heatsink with Silicon Insulated-Gate Bipolar Transistors (IGBTs) and diodes, solder, Direct Bonded Copper (DBC) substrate, baseplate and thermal grease is developed. Richardson’s extrapolation is used for increasing the accuracy of the numerical simulations and to validate the simulations. To study the effectiveness of the new offset design, results are compared with conventional offset strip fin heatsink. Results show that in aspects of design of heatsinks (including heat transfer coefficient, maximum chip temperature and thermal resistance), the new introduced model has advantages compared to the conventional offset strip fin design. These enhancements are caused by the combination of the longer coolant passage in the heatsink associated with generation of disturbance and recirculation areas along the curvy fins, creation of centrifugal forces in the U-turn, and periodic breaking up boundary layers. Also, it is shown that due to narrower passage and back-and-forth route, the new introduced design can handle the hot spots better than conventional design.

APA, Harvard, Vancouver, ISO, and other styles

23

Zhang, Wenli, Fengchang Yang, Rui Qiao, and Dushan Boroyevich. "Integrated Microchannel Cooling for Power Electronic Modules." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, CICMT (May 1, 2016): 000122–29. http://dx.doi.org/10.4071/2016cicmt-wa25.

Full text

Abstract:

Abstract The power electronic module plays a key role in the power system by providing the needed physical support, electrical contact and insulation, and thermal pathway for power devices. Using wide bandgap power semiconductors in the power modules enables high-frequency and low-loss switching at relatively high temperatures for efficient power conversion. These advantages could lead to an increase in power-density for the power module as well as a reduction of cost, weight, and volume at the system level. However, the highly integrated power module requires advanced thermal management solutions for effective heat removal from the active chips to achieve high reliability. The evaluation of thermal performance for the power module is critical for its packaging design, because most of the heat generated by the semiconductors is dissipated through the module package. It is even more critical for the gallium nitride (GaN)-based power modules due to the lower thermal conductivity of the GaN material compared with that of silicon and silicon carbide. This paper provides a brief introduction of power modules in conventional packaging design and a review of several new packaging structures with advanced thermal management solutions. The direct-bonded-copper (DBC) substrate with integrated microchannel cooling designed for a new packaging structure is proposed for highly integrated power modules. In this design, the cooling microchannels are embedded inside the aluminum nitride (AlN) layer of the DBC substrate. In finite element analysis (FEA) simulation model of the new package, six high-voltage GaN transistors are arranged on the top surface of the DBC substrate to realize a three-phase inverter circuit. Three straight embedded microchannels with a cross-sectional area of 0.3 mm × 5 mm are located underneath the GaN devices. The average maximum temperature of the GaN devices in the new package is around 72 °C (50 W power loss applied on each die), which is about 16 °C lower than that in the traditional power module package. A thermal transfer coefficient of 2000 W/m2 K, which is equivalent to the liquid cooling condition, is applied on the bottom surface of the baseplate in the traditional package. Enhanced heat dissipation capability is demonstrated using this integrated microchannel cooling method. Further study will focus on the fabrication of a prototype and experimental testing.

APA, Harvard, Vancouver, ISO, and other styles

24

Zhao, Xin, K. Jagannadham, Wuttichai Reainthippayasakul, Michael T. Lanagan, and Douglas C. Hopkins. "Characterization of Ultra-Thin Epoxy-Resin Based Dielectric Substrate for Flexible Power Electronics Applications." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000151–56. http://dx.doi.org/10.4071/isom-2017-tp55_094.

Full text

Abstract:

Abstract Available substrate materials for power module applications has been investigated for a long time. Though Direct Bonded Copper (DBC) substrates, nowadays, have been widely applied in power electronics applications, especially power modules, due to its superior performance in mechanical ruggedness, thermal conductivity, and isolation capability. Its cost and complicated requirements during fabrication processes are always concerns in industries. At the same time, flexible electronics has become a rapidly expanding area with commercial applications including displays, medical, automotive, sensors arrays, wearable electronics, etc. This paper will initiate an investigation on a dielectric material that has potential in high power wearable electronics applications. A recently developed ultra-thin Epoxy-Resin Based Dielectric (ERBD) substrate material which is suitable for power electronic applications, is introduced. The ERBD can be fabricated with thickness as low as 80μm, with more than 5kV DC isolation capability. Its thermal conductivity is 8W/mK, higher than similar product currently available in the market. ERBD is also able to be bonded with Cu plates on both sides. In this paper, the properties of ERBD are investigated. Scanning Electron Microscope (SEM) is applied to analyze the microstructure of ERBD, and its bonding interface with Cu plates. 3-omega and Transient Thermal Reflectance methods are employed to precisely measure the thermal conductivity. Dielectric constant and loss are measured at different frequency. Simulations are applied to correct the error from the fringing effect during the measurement. The leakage current of ERBD is also measured under different voltage and temperature with DC and AC condition. Reliability tests are conducted to examine the electrical isolation and shearing strength of ERBD. The suitability of ERBD for potential flexible power electronics application is discussed based on the results from investigation of properties of the dielectric.

APA, Harvard, Vancouver, ISO, and other styles

25

Tripathi, Rajesh, Sejin Im, Douglas Devoto, Joshua Major, Sreekant Narumanchi, Paul Paret, and Xuhui Feng. "Power electronics thermal solutions using thermally conductive polyimide films." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000616–46. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp3_042.

Full text

Abstract:

Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. DuPont has developed a thermally conductive polymer film that provides very low thermal resistance and very high insulation. The film can be bonded to conductive and thick metallic layers and this polymer equivalent of DBC shows very high reliability in addition to high performance characteristics. Electrically insulating layers within a power electronics module are critical for separating circuitry from thermal management layers. Electrical insulating substrates typically used in power electronics modules utilize a ceramic layer, comprised most commonly of either Al2O3, AlN, or Si3N4. Thin Cu layers are bonded to either side of the substrate using a direct bond Cu (DBC) or active metal brazing (AMB) process. These processes involve bonding metallization layers to both sides of the ceramic at a high temperature as bonding to only one side would cause deformation during the cooling phase. Typical metal thickness bonded to either side of the ceramic is about 0.3–0.6 mm as the high temperature manufacturing process does not allow very thick metals to be bonded and this limits the heat spreading capability of the thermal substrate. DuPont's new Temprion™ Organic Direct Bond Copper (ODBC) address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC's dielectric layer will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. Al2O3 and Si3N4-based substrates were utilized as a baseline for reliability comparison with the DuPont substrates. The industry-standard substrates in used in this study have a thickness of 0.3 and 0.8 mm for the Cu metallization layers and 0.38 and 0.32 mm for the insulating layer respectively for Al2O3 an Si3N4 insulators. DuPont ODBC substrates were fabricated by attaching a polyimide layer to a layer of 0.8-mm-thick Cu. The polyimide and bottom Cu layer cross-sectional footprints are both 50.8 mm × 50.8 mm. The corners of both layers were filleted with various radii (0.5, 1.0, 2.0, and reversed 2.0 mm) to explore the impact of different stress concentrations between the metallization and insulating layers. The top Cu metallization was inset 2.0 mm from the perimeter of the electrically-insulating substrate and bottom Cu metallization.10 samples each of the DuPont ODBC and industry Al2O3 substrates were placed in a thermal shock chamber and cycled between temperature extremes of −40°C and 200°C. Substrates were inspected every 1000 cycles. After 5000 cycles, the ODBC substrates experienced no hipot failures, but preliminary edge delamination was visually observed. Al2O3 substrates all failed after 50 thermal cycles.Five DuPont ODBC samples were placed in a thermal chamber and subjected to an elevated temperature of 175°C. After 2000 hours, no hipot failures were observed, but edge delamination was again observed.Five DuPont ODBC samples were attached to a cold plate with Kapton tape. Heater cartridges were attached to the top of the substrates with Kapton tape and thermocouples were placed in several locations through the package. The heater cartridges were alternated between on and off states to allow for the substrates to cycle between −40°C and +200°C. While the change between the maximum and minimum temperatures is smaller for the power cycling test compared to the thermal cycling test, the heater cartridge and cold plate create a thermal gradient within the samples that is not possible with passive thermal cycling. After 2000 hrs cycles of testing, no hipot failures or edge delamination have been observed. Herein we show that the DuPont ODBC substrate design is a promising alternative to traditional industry substrates based on ceramic insulators. The reliability of the substrate design has been demonstrated under several thermomechanical accelerated tests and the electrical and thermal performance has been measured. Future work will include reliability comparisons to other industry substrates, including thermal shock testing of substrates with HPS, AlN, and Si3N4 ceramic layers. Thermal models will correlate thermal resistance values measured by the transient thermal tester and compare the ODBC substrate performance to industry substrates within a commercialized power electronics module. The modeling will also optimize the thickness of the metallization layers within the ODBC substrates to minimize the junction temperature of the switching devices.

APA, Harvard, Vancouver, ISO, and other styles

26

Morgan, Adam, Xin Zhao, Jason Rouse, and Douglas Hopkins. "Characterization of Silicone Gel for High Temperature Encapsulation in High Voltage WBG Power Modules." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000312–17. http://dx.doi.org/10.4071/isom-2017-wa54_099.

Full text

Abstract:

Abstract One of the most important advantages of wide-bandgap (WBG) devices is high operating temperature (>200°C). Power modules have been recognized as an enabling technology for many industries, such as automotive, deep-well drilling, and on-engine aircraft controls. These applications are all required to operate under some form of extreme environmental conditions. Silicone gels are the most popular solution for the encapsulation of power modules due to mechanical stress relief enabled by a low Young's modulus, electrical isolation achieved due to high dielectric strength, and a dense material structure that protects encapsulated devices against moisture, chemicals, contaminants, etc. Currently, investigations are focused on development of silicone gels with long-term high-temperature operational capability. The target is to elevate the temperature beyond 200°C to bolster adoption of power modules in the aforementioned applications. WACKER has developed silicone gels with ultra-high purity levels of < 2ppm of total residual ions combined with > 200°C thermal stability. In this work, leakage currents through a group of WACKER Chemie encapsulant silicone gels (A, B, C) are measured and compared for an array of test modules after exposure to a 12kV voltage sweep at room temperature up to 275°C, and thermal aging at 150°C for up to more than 700 hours. High temperature encapsulants capable of producing leakage currents less than 1μA, are deemed acceptable at the given applied blocking voltage and thermal aging soak temperature. To fully characterize the high temperature encapsulants, silicone gel A, B, and C, an entire high temperature module is used as a common test vehicle. The power module test vehicle includes: 12mil/40mil/12mil Direct Bonded Copper (DBC) substrates, gel under test (GUT), power and Kelvin connected measurement terminals, thermistor thermal sensor to sense real-time temperature, and 12mil Al bonding wires to manage localized high E-Fields around wires. It was ultimately observed that silicone gels B and C were capable of maintaining low leakage current capabilities under 12kV and 275°C conditions, and thus present themselves as strong candidates for high-temperature WBG device power modules and packaging.

APA, Harvard, Vancouver, ISO, and other styles

27

Welker, T., S. Günschmann, N. Gutzeit, and J. Müller. "Integration of Silver Heat Spreaders in LTCC utilizing Thick Silver Tape in the Co-fire Process." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, CICMT (September 1, 2015): 000062–66. http://dx.doi.org/10.4071/cicmt-tp13.

Full text

Abstract:

The integration density in semiconductor devices is significantly increased in the last years. This trend is already described by Moore's law what forecasts a doubling of the integration density every two years. This evolution makes greater demands on the substrate technology which is used for the first level interconnect between the semiconductor and the device package. Higher pattern resolution is required to connect more functions on a smaller chip. Also the thermal performance of the substrate is a crucial issue. The increased integration density leads to an increased power density, what means that more heat has to dissipate on a smaller area. Thus, substrates with a high thermal conductivity (e. g. direct bonded copper (DBC)) are utilized which spread the heat over a large area. However, the reduced pattern resolution caused by thick metal layers is disadvantageous for this substrate technology. Alternatively, low temperature co-fired ceramic (LTCC) can be used. This multilayer technology provides a high pattern resolution in combination with a high integration grade. The poor thermal conductivity of LTCC (3 … 5 W*m−1*K−1) requires thermal vias made of silver paste which are placed between the power chip and the heat sink and reduce the thermal resistance of the substrate. The via-pitch and diameter is limited by the LTCC technology, what allows a maximum filling grade of approx. 20 to 25 %. Alternatively, an opening in the ceramic is created, to bond the chip directly to the heat sink. This leads to technological challenges like the CTE mismatch between the chip and the heat sink material. Expensive materials like copper molybdenum composites with matched CTE have to be used. In the presented investigation, a thick silver tape is used to form a thick silver heat spreader through the LTCC substrate. An opening is structured by laser cutting in the LTCC tape and filled with a laser cut silver tape. After lamination, the substrate is fired using a constraint sintering process. The bond strength of the silver to LTCC interface is approx. 5.6 MPa. The thermal resistance of the silver structure is measured by a thermal test chip (Delphi PST1, 2.5 mm × 2.5 mm) glued with a high thermal conducting epoxy to the silver structure. The chip contains a resistor and diodes to generate heat and to determine the junction temperature respectively. The backside of the test structure is temperature stabilized by a temperature controlled heat sink. The resulting thermal resistance is in the range of 1.1 K/W to 1.5 K/W depending on the length of silver structure (5 mm to 7 mm). Advantages of the presented heat spreader are the low thermal resistance and the good embedding capability in the co-fire LTCC process.

APA, Harvard, Vancouver, ISO, and other styles

28

Yao, Yiying, Zheng Chen, Dushan Boroyevich, and Khai D. T. Ngo. "High-Temperature Reliability of Direct-Bond-Copper Substrates with Sealed Edges." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 1–5. http://dx.doi.org/10.4071/hitec-2012-wa23.

Full text

Abstract:

Recent reports have shown the reliability of direct-bond-copper (DBC) substrates was significantly improved by sealing their edges with polymeric materials. In this work, DBC substrates with and without sealed edges had been prepared. Parylene HT and Nusil R-2188 had been chosen as sealing materials. Parylene HT was applied to the edges of the DBC by chemical vapor deposition (CVD), and Nusil R-2188 by programmable fluid dispensing. The DBC substrates with and without sealed edges were cycled between −55°C to 200°C. The cycled substrates were monitored by optical microscope and scanning electron. DBC substrates whose edges were not sealed were found to fail in approximately 100 cycles. No failure was observed in DBC substrates coated with parylene HT before 300 cycles. Samples whose edges were sealed with Nusil R-2188 exhibited the highest lifetime under the thermal cycling condition of −55°C – 200°C. After 300 cycles, neither detachment of Nusil from DBC surfaces nor failure at Cu/Al2O3 interface was detected. After 900 cycles, 30 μm – 60 μm cracks appeared at the edges of Cu/Al2O3 interface, which are signaling the early stage of substrate failure. Additionally, Nusil was found to be partially detached from DBC surfaces. The improvement in reliability is attributed to the release of thermo-mechanical stress concentrated at the edges of the Cu/Al2O3 interface.

APA, Harvard, Vancouver, ISO, and other styles

29

Toth Pal, Zsolt, Tag Hammam, and Hans Peter Nee. "Pressure Dependence of Thermal Contact Resistance between Copper Heat Sink and Copper DBC Surfaces in SiC Power Device Packages." Materials Science Forum 778-780 (February 2014): 1118–21. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.1118.

Full text

Abstract:

Thermal contact resistances have been measured in an experiment emulating heat transfer from a SiC die to a cooled heat sink through a heat spreader and a DBC structure. The major surface-dependent parameters are the surface roughness, surface hardness, and planarity. The measured thermal contact resistances are in agreement with theoretical values. When investigating DBC copper surfaces a second interface between the bonded Cu to AlN has to be taken into account.

APA, Harvard, Vancouver, ISO, and other styles

30

Squires, Matthew B., James A. Stickney, Evan J. Carlson, Paul M. Baker, Walter R. Buchwald, Sandra Wentzell, and Steven M. Miller. "Atom chips on direct bonded copper substrates." Review of Scientific Instruments 82, no. 2 (February 2011): 023101. http://dx.doi.org/10.1063/1.3529434.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Alizadeh, Rana, Kaoru Uema Porter, Tom Cannon, and Simon S. Ang. "Fabrication of Ceramic Interposers for Module Packaging." Journal of Microelectronics and Electronic Packaging 17, no. 2 (April 1, 2020): 67–72. http://dx.doi.org/10.4071/imaps.1114553.

Full text

Abstract:

Abstract In this study, low-temperature cofired ceramic (LTCC) and 3D-printed ceramic interposers are designed and fabricated for a double-sided power electronic module. The interposer acts as electrical insulation between two direct-bond copper (DBC) power substrates as well as mechanical support to evenly distribute the weight of the top DBC substrate onto the entire bottom DBC substrate instead of directly onto the bare power semiconductor die. A novel LTCC fabrication process for 14 layers of green tapes with premachined recesses and holes is developed. A similar interposer is 3D printed using a ceramic resin. Finally, the fabricated LTCC and 3D-printed interposers are compared.

APA, Harvard, Vancouver, ISO, and other styles

32

Schulz-Harder, Jürgen. "Advantages and new development of direct bonded copper substrates." Microelectronics Reliability 43, no. 3 (March 2003): 359–65. http://dx.doi.org/10.1016/s0026-2714(02)00343-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Yu, Ho-Chieh (Jay), and Jason Huang. "Investigation of the Direct Plating Copper (DPC) on Al2O3, BeO or AlN Ceramic Substrates for High Power Density Applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000079–86. http://dx.doi.org/10.4071/isom-2016-tp43.

Full text

Abstract:

Abstract In the high power module applications, the power increasing and the size shrinking becomes one of the major topics for the power module design. Due to both the power increasing and the size decreasing, the power density of the device will be much increased. Therefore, not only the thermal conductivity and stability of the substrate material but the long-term material reliability of the substrate have to be seriously considered. For these reasons, the ceramic PCB becomes one of the best solutions. The ceramic substrates now used are normally based on Ag-printed or direct bonding copper (DBC) technology. In the case of the Ag-printed ceramic substrate, the pattern resolution and metallization thickness are limited by the Ag-printed process. Also the combination strength of the silver and ceramic substrate by glass (which is normally mixed in the silver paste) is normally not good enough. A thermal dissipation barrier will then be formed between silver and ceramic substrate due to the poor thermal conductivity of the glass material. For the DBC ceramic substrate, DBC substrates are manufactured at 1065°C by the diffusion between ceramic and Cu/CuO layer. A thicker Cu layer thickness of normally more than 300 um is required in the thermal compressing bonding process. The Cu pattern resolution will then be limited by the thickness of the Cu layer. However, the about 5~10% of the voids exist randomly between ceramic and Cu layer is the other major issue. The resolution issues of the Ag-printed and DBC ceramic substrates make the limitation for the device density design (fine line/width and flip-chip device design become very difficult). The glass material in the Ag printed ceramic substrate and the 5~10% voids existence in DBC ceramic substrate may cause the reliability issue operating at a high power density applications. For high power density module applications, we introduce the DPC technology on the ceramic substrate. In DPC ceramic substrate system, the sputtered Ti is used as the combination material between Cu and ceramic substrate. And the first copper is then sputtered on the top of Ti layer as seed-layer for the following Cu electrode plating (second cupper layer). By the material and the sputtering process control, several ceramic substrate raw materials can be used, such as Al2O3, AlN, BeO, Si3N4 and so on. The Ti combined/buffer layer provides good adhesion strength and material stability. The second copper layer is plated by electrode casting plating to 3 to 5 oz. (100~150um) in thickness. The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. In the DPC system, the double layers design is available. The laser drilled via holes on the various ceramic substrates is introduced. The conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material stability during high temperature laser drilled is well controlled. DPC ceramic substrates provide a better metal/ceramic interface uniformity and material reliability due to the stable Ti combination material and much less voids in the metal/ceramic interface. Also, the DPC ceramic substrates provide a gold pattern resolution of 50 um line space with tight tolerance of 20 um min. We believe the material characteristic make DPC a very suitable substrate material for high power module applications.

APA, Harvard, Vancouver, ISO, and other styles

34

Akhtar, S. S., L. T. Kareem, A. F. M. Arif, M. U. Siddiqui, and A. S. Hakeem. "Development of a ceramic-based composite for direct bonded copper substrate." Ceramics International 43, no. 6 (April 2017): 5236–46. http://dx.doi.org/10.1016/j.ceramint.2017.01.049.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Cui, Jinzi, R. Wayne Johnson, and Michael C. Hamilton. "Investigation into the Role of Different Substrate Ni Compositions and Plating Methods on Die Attach Reliability." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000073–82. http://dx.doi.org/10.4071/hiten-session2-paper2_6.

Full text

Abstract:

Nickel is a commonly used diffusion barrier for direct bond copper (DBC) substrates used in high temperature, high power applications. The Ni can be deposited by electroless or electrolytic plating and may be pure Ni, Ni:P, Ni:B or Ni:Co. The reactivity of these different Ni layers with AuGe and BiAgX® solder is explored. Specifically the reaction to form Ni-Ge intermetallics and NiBi3 during high temperature storage and the impact on die shear strength and failure mode are discussed.

APA, Harvard, Vancouver, ISO, and other styles

36

Cavaco, Celso, Lan Peng, Koen De Leersnijder, Stefano Guerrieri, Deniz S. Tezcan, and Haris Osman. "Copper Oxide Direct Bonding of 200mm CMOS Wafers: Morphological and Electrical Characterization." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000594–97. http://dx.doi.org/10.4071/isom-2015-tha26.

Full text

Abstract:

We show for the first time complete data on 200mm wafer to wafer copper oxide direct bonding of two metal levels. Both surface acoustic microscope (SAM) and cross-section scanning electron microscope (X-SEM) images taken across the bonded wafer pairs confirm the good direct bonding quality of the resulting interface. Daisy chains with up to 3200 copper to copper bonded pads and of about 50mOhm/pad, are shown to be connected successfully and its resistance value to match a target value, as well as to scale linearly with the increase of connections in the chain.

APA, Harvard, Vancouver, ISO, and other styles

37

Piekoszewski, J., Wieslawa Olesińska, J. Jagielski, D. Kaliński, M. Chmielewski, Z. Werner, M. Barlak, and Wiesław Szymczyk. "Ion Implanted Nanolayers in AlN for Direct Bonding with Copper." Solid State Phenomena 99-100 (July 2004): 231–34. http://dx.doi.org/10.4028/www.scientific.net/ssp.99-100.231.

Full text

Abstract:

Experiments to directly bond AlN with Cu were conducted for different pre-treatments of the bonded components. AlN substrates were implanted either with oxygen, or titanium or iron ions at low (15 keV) or high (70 keV) energy, or thermally oxidized. Some Ti-implanted samples were also thermally oxidized. The copper component was annealed and thermally oxidized. The best results, with respect to the bond shear strength, were obtained for low-energy implantation of oxygen and titanium.

APA, Harvard, Vancouver, ISO, and other styles

38

Hagiwara, Naoki, Shinji Koyama, and Ikuo Shohji. "Cu/Cu Direct Bonding by Metal Salt Generation Bonding Technique with Formic Acid and Citric Acid." Advanced Materials Research 922 (May 2014): 219–23. http://dx.doi.org/10.4028/www.scientific.net/amr.922.219.

Full text

Abstract:

The effect of formic acid and citric acid surface modification on the bonded strength of the solid-state direct bonded interface of copper was investigated by SEM observations of interfacial microstructures and fractured surfaces. Copper surfaces were modified by boiling in 98% formic acid for 0.6 ks and 17% aqueous solution of citric acid for 0.96 s. Solid-state bonding was performed in a vacuum chamber at bonding temperature of 423 ~ 673 K under a pressure of 588 N (bonding time of 0.9 ks). As a result of surface modification by formic acid and citric acid, bonded joints were obtained at a bonding temperature 150 K (formic acid) and 100 K (citric acid) lower than that required for non-modified surfaces, and the bond strength was comparable to that of the maximum load.

APA, Harvard, Vancouver, ISO, and other styles

39

Akhtar, S. S., K. T. Lemboye, A. F. M. Arif, and K. S. Al-Athel. "Design and Performance Evaluation of Al2O3-SiC Composite for Direct-Bonded Copper Substrate." Journal of Materials Engineering and Performance 27, no. 11 (October 15, 2018): 5831–44. http://dx.doi.org/10.1007/s11665-018-3702-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Chua, S. T., and K. S. Siow. "Microstructural studies and bonding strength of pressureless sintered nano-silver joints on silver, direct bond copper (DBC) and copper substrates aged at 300 °C." Journal of Alloys and Compounds 687 (December 2016): 486–98. http://dx.doi.org/10.1016/j.jallcom.2016.06.132.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Yu, Ho-Chieh (Jay), and Jason Huang. "The Direct plating copper (DPC) ceramic material on Al2O3/AlN or LTCC (Low-temperature co-fired ceramic) substrates." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 001773–90. http://dx.doi.org/10.4071/2016dpc-wp46.

Full text

Abstract:

RESEARCH BACKGROUND: The now used ceramic substrate or sub-mounted are normally based on Ag-printed, direct bonding copper (DBC) ceramic or LTCC (Low temperature co-fired ceramic)/HTCC (High temperature co-fired ceramic) technology.Due to the limit of the screen-printed process, the resolution and conducting material thickness the Ag-printed, LTCC and HTCC substrate are poor. The poor resolutions make these materials difficult to use in high density and flip-chip device design. And the related thinner conducting material (normally <20um) limits the power rating of the design.DBC is now widely applied in power circuit design, however, duo to the copper lamination process requirement, more than 300um in thickness of copper layer is needed. Any lower copper thickness design should have an extra costly grind to reach. Also, the DBC material is difficult to provide to the multilayer trace design. OUR GOAL: We want to provide a solution with multilayer ceramic substrate for high power and high device density applications. Besides, the material properties, the adhesion of the metal/ceramic also be considered. Following are the material characteristics required for the development:A low electrical resistance material: Copper.A thick trace material thickness of more than 3 oz.A high thermal conductivity and stability ceramics with via-holes for TSV plating (Drilled Al2O3/AlN substrate ) or non- shrinking LTCC materialHigh metal trace resolution whose line width and space could be only 50 umWell metal/ceramic adhesion uniformity and strength is required: The voids between metal/ceramic < 1%; The adhesion strength> 2 kg/2*2mm2. METHODS & RESULTS: Metal trace plating: For high resolution and lower material electrical resistance request of the trace metal, we introduce electrical casting direct-plating copper (DPC) technology. The first copper is sputtered on the ceramic substrate using Ti as combined/buffer layer between copper and ceramic to provide good adhesion strength and stability. The second copper is made by electrical casting process to increase its thickness to 3 to 5 oz. (100~150um). The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. Multilayer Ceramic substrates: For double layers design, we use sintered Al2O3 or AlN substrates with electrical conducting via-holes design. The via-holes are made by laser drilling. And the conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material variation during high temperature laser drilled is well controlled. For the more than three layers design, the non-shrinking LTCC is used. The dimension mismatch of the non-shrinking LTCC can controlled less than 100um., much better than that of normal LTCC/HTCC. By the correction of the following DPC process, the tolerance of the metal trace can be controlled < 30 um. The key technology of this process is the non-shrinking LTCC technology and the adhesion of the DPC metal on LTCC material.

APA, Harvard, Vancouver, ISO, and other styles

42

Myśliwiec, Marcin, and Ryszard Kisiel. "Thermal and mechanical properties of sintered Ag layers for power module assembly." Microelectronics International 32, no. 1 (January 5, 2015): 37–42. http://dx.doi.org/10.1108/mi-10-2013-0050.

Full text

Abstract:

Purpose – The purpose of our paper is to investigate thermal and mechanical properties of Ag sintered layers used for assembly of SiC diode to Direct Bonding Copper (DBC) interposer. How SiC devices are assembled to ceramic package defines efficiency of heat transfer and mechanical support. Design/methodology/approach – Ag microparticles, sized 2-4 μm and flake shaped, were used as joining material. The parameters of sintering process were as follows: temperature 400°C, pressure 10 MPa and time 40 min. It was found that after sintering and long-term aging in air at 350°C the adhesion is in the range of 10 MPa, which is enough from a practical point of view. The thermal properties of the SiC die assembled into a ceramic package were also investigated. In the first step, the calibration of the temperature-sensitive parameter VF (IF = 2 mA) was done and the relation between VF and temperature was found. In the next step, the thermal resistance between junction and case was determined knowing junction and case temperature. Findings – For SiC diode with Au bottom metallization joined to the DBC interposer by Ni/Au metallization by Ag microparticle layer, Rth j-c is in the range of 2-3.5°C/W, and for SiC diode with Ag bottom metallization joined to DBC interposer with Ag metallization by Ag microparticle layer, Rth j-c is in the range of 4.5-5.5°C/W. Research limitations/implications – In the future, research on thermal resistance of SiC diodes assembled onto the DBC interposer with Au and Ag metallization in the temperature range up to 350°C needs to be carried out. To do this, it necessary to find a solution for the attaches that leads to ceramic package able to work at such high temperature. Originality/value – Obtained results are comparable with results mentioned by other studies for eutectic Au/Sn or SAC solder joints; however, the solution proposed by us can properly work at significantly higher temperatures.

APA, Harvard, Vancouver, ISO, and other styles

43

Tang, Rongjiang, Hong He, Xiong Jiang, Fabing Zeng, Haidong Yan, and Ping Zhang. "The Preparation of Ag Nanopaste with Silver-Plated Diamond by Low-Temperature Pressureless Sintering." Journal of Nanoelectronics and Optoelectronics 16, no. 6 (June 1, 2021): 933–40. http://dx.doi.org/10.1166/jno.2021.3035.

Full text

Abstract:

Diamond/Ag nanopaste has been prepared by mixing Ag nanoparticles, silver-plated diamond particles, and an organic solvent system. Then, we characterized and studied the sintering properties of diamond/Ag nanopaste. Meanwhile, the impact factor of sintering temperature on the sintered microstructure of the diamond/Ag nanopaste on direct bonding copper (DBC) substrate was investigated. The influences of sintering temperature on the shear strength of diamond/Ag nanopaste connection layer for attaching silicon chip on the silver-plated copper substrate were analyzed. The results show that silver plating on the surface of the diamond can significantly strengthen the bonding ability between the diamond and nano-silver. When the pressureless sintering temperature increased from 150 °C to 350 °C, the porosity of diamond/Ag nanopaste decreased from 29.8% to 8.9%, and the sintered diamond/Ag joint with uniform and dense connection layer showed the maximum shear strength of 15.26 MPa as sintering at 350 °C.

APA, Harvard, Vancouver, ISO, and other styles

44

Gaiser, Patrick, Markus Klingler, and Jürgen Wilde. "The influence of strain hardening of copper on the crack path in Cu/Al2O3/Cu direct bonded copper substrates." International Journal of Fatigue 140 (November 2020): 105821. http://dx.doi.org/10.1016/j.ijfatigue.2020.105821.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Xu, Qianye, Yunhui Mei, Xin Li, and Guo-Quan Lu. "Correlation between interfacial microstructure and bonding strength of sintered nanosilver on ENIG and electroplated Ni/Au direct-bond-copper (DBC) substrates." Journal of Alloys and Compounds 675 (August 2016): 317–24. http://dx.doi.org/10.1016/j.jallcom.2016.03.133.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Eichwald, Paul, Simon Althoff, Reinhard Schemmel, Walter Sextro, Andreas Unger, Michael Brökelmann, and Matthias Hunstig. "Multi-dimensional Ultrasonic Copper Bonding – New Challenges for Tool Design." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000438–43. http://dx.doi.org/10.4071/isom-2017-wp43_071.

Full text

Abstract:

Abstract In power electronics, copper connector pins are e.g. used to connect control boards with power modules. The new chip generation based on SiC and GaN technology increase the power density of semiconductor modules significantly with junction temperatures reaching 200°C. To enable reliable operation at such high temperature, the soldering of these connector pins should be substituted by a multi-dimensional copper-copper bonding technology. A copper pin welded directly on DBC substrate also simplifies the assembly. With this aim, a proper bond tool and a suitable connector pin geometry are designed. This paper presents a two-dimensional trajectory approach for ultrasonic bonding of copper pieces, e.g. connector pins, with the intention to minimize mechanical stresses exposed to the substrate. This is achieved using a multi-dimensional vibration system with multiple transducers known from flip chip bonding. Applying a planar relative motion between the bonding piece and the substrate increases the induced frictional power compared to one-dimensional excitation. The core of this work is the development of a new tool design which enables a reliable and effective transmission of the multidimensional vibration into the contact area between nail-shaped bonding piece and substrate. For this purpose, different bonding tool as well as bonding piece designs are discussed. A proper bonding tool design is selected based on the simulated alternatives. This tool is examined in bonding experiments and the results are presented. In addition, different grades of hardness for bonding piece and substrate are examined as well as different bonding parameters. Optical inspection of the bonded area shows the emergence of initial micro welds in form of a ring which is growing in direction of the interface boundaries with increasing bonding duration.

APA, Harvard, Vancouver, ISO, and other styles

47

Silvain, Jean François, Valérie Denis-Lutard, Pierre Marie Geffroy, and Jean Marc Heintz. "Adaptive Composite Materials with Novel Architectures." Materials Science Forum 631-632 (October 2009): 149–54. http://dx.doi.org/10.4028/www.scientific.net/msf.631-632.149.

Full text

Abstract:

Today, there is a strong push to improve the thermal management of electronic components in order to increase the performance and the reliability of electronic devices. Up to now, most of the heat sinks are mainly made of Copper that presents a good thermal conductivity (TC) but a coefficient of thermal expansion (CTE) much higher than the ceramic of the DBC (direct bonding Copper). It induces interfacial thermal stresses and indeed it decreases the reliability of the global electronic system. Therefore, there is a strong need for the development of novel heat dissipation material having low CTE combined with high TC. Carbon fibres reinforced copper matrix offers a good compromise between thermo mechanical properties (i.e. CTE) and medium TC. In order to increase surface TC, pure Copper can be added on the top surface and/or on the bottom one of the composite heat sink playing the role of heat spreader for hot spots linked with the Si components. The fabrication technique of these materials is based on powder metallurgy technique. The thermal properties of adaptive materials, TC and CTE, have been measured for different Copper thicknesses and architectures ([C/Cu], [Cu – C/Cu] and [Cu – C/Cu – Cu]). Simulation of the TC and CTE have been performed and compared to the experimental results.

APA, Harvard, Vancouver, ISO, and other styles

48

Shen, Zhenzhen, Kun Fang, Mike Hamilton, R. Wayne Johnson, Erica Snipes, and Michael Bozack. "Lead-free Solder Attach for 200°C Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000260–67. http://dx.doi.org/10.4071/hiten-wa18.

Full text

Abstract:

Conventional SAC lead-free solders have a melting point of 217°C to 227°C, limiting their suitability for applications at 200°C. AgBiXTM solder has potential for 200°C applications because of its ~260°C solidus temperature. BiAgX paste has been used to assemble SiC test die to ceramic substrates with direct bond copper (DBC), reactive brazed CuMo, thick film Au, thick film PtAu, thick film PdAg and thick film Ag. Surface mount chip resistors have also been attached to thick film metallized substrates. The assembly process and initial shear strength test results are presented. Assemblies have also been subjected to thermal testing: thermal cycling (−55°C to +195°C) and high temperature (200°C) storage. The shear strength of these assemblies after thermal testing are presented and compared to initial results.

APA, Harvard, Vancouver, ISO, and other styles

49

Agbim, Kenechi A., Darshan G. Pahinkar, and Samuel Graham. "Integration of Jet Impingement Cooling With Direct Bonded Copper Substrates for Power Electronics Thermal Management." IEEE Transactions on Components, Packaging and Manufacturing Technology 9, no. 2 (February 2019): 226–34. http://dx.doi.org/10.1109/tcpmt.2018.2863714.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Pak, Han-ryong, Chung-wen Chen, O. T. Inal, and Kali Mukerjee. "Microstructures of straight and wavy interfaces formed in explosively bonded copper single crystals." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 426–27. http://dx.doi.org/10.1017/s0424820100143717.

Full text

Abstract:

Explosive welding is essentially a solid-phase bonding process, hence any metal can be bonded even if they are totally dissimilar physically and chemically. Our group recently found that a straight interface is superior, with respect to plastic deformation behavior, to a wavy one, in direct contrast to a model that an interlocking structure of a wavy interface produces strong bonds. To obtain some insight into the superiority of such a straight interface, microstructures of copper single crystals (size: 4 x 40 x 130 mm) explosively welded in a parallel standoff configuration are investigated by means of transmission electron microscopy.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Direct Bonded Copper (DBC)'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles