Relevant bibliographies by topics / Direct Digital Synthesizer

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  2. Dissertations / Theses
  3. Books
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Academic literature on the topic 'Direct Digital Synthesizer'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Direct Digital Synthesizer"

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Spooner, A., Binneg Lao, D. Rowe, C. Harper, S. Schwarzbek, D. J. Durand, L. Eaton, and A. D. Smith. "Superconducting direct digital synthesizer." IEEE Transactions on Appiled Superconductivity 7, no. 2 (June 1997): 2270–73. http://dx.doi.org/10.1109/77.621691.

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Yih-Chyun Jenq. "Direct digital synthesizer with jittered clock." IEEE Transactions on Instrumentation and Measurement 46, no. 3 (June 1997): 653–55. http://dx.doi.org/10.1109/19.585421.

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Mukhanov, Oleg, Amol Inamdar, Timur Filippov, Anubhav Sahu, Saad Sarwana, and Vasili Semenov. "Superconductor Components for Direct Digital Synthesizer." IEEE Transactions on Applied Superconductivity 17, no. 2 (June 2007): 416–21. http://dx.doi.org/10.1109/tasc.2007.898055.

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Polikarovskykh, O. I. "DIRECT DIGITAL SYNTHESIZER IN A NEW MATHEMATICAL BASIS." Proceedings of the O.S. Popov ОNAT 1, no. 2 (December 31, 2020): 100–110. http://dx.doi.org/10.33243/2518-7139-2020-1-2-100-110.

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The principles of the construction and operation of a digital synthesizer for direct frequency synthesis with acceleration of computational operations by using a residual class system (RNS) are considered. The specifics of the implementation of the operation of direct and inverse transformations from the positional number system to the number system of the residual classes are described. A mathematical model of a synthesizer with a phase accumulator in the system of residual classes is considered. The ways of designing a digital synthesizer of direct synthesis with a phase accumulator in the RNS system and a sinusoidal DAC are considered. In traditional schemes, the conversion of residuals to the value of an analog signal occurs in several stages, where conversion to a binary system is one of the stages. This procedure degrades the speed of the RNS system, adding additional constraints and increasing the waiting time for the conversion result. Methods of converting from RNS to binary number system for basic operations are considered. A DDS design with a phase accumulator in the residual class system and a converter to an analog signal form without using a slow ROM is proposed. The problems of efficient use of the synthesizer crystal area and reduction of delays in the formation of the output signal are considered. A study of one of the main functional blocks of a direct digital frequency synthesizer, a digital-to-analog converter, has been carried out. The architecture of a direct digital frequency synthesizer with a DAC direct conversion from a non-positional number system to an analog signal is proposed. The main sources of noise generation in digital computational synthesizers of the proposed type are investigated. A mathematical model is proposed for calculating the power spectral density of phase noise, which will allow analyzing the noise characteristics in synthesizers built on the indicated principles.
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Kuzichkin, Oleg R., Dmitriy I. Surzhik, Gleb S. Vasiliev, Igor A. Kurilov, and Nikolai V. Dorofeev. "Analysis of Noise Characteristics of Multichannel Systems of the Formation of Signals of Georadars with Synthesized Aperture." Active and Passive Electronic Components 2018 (December 4, 2018): 1–7. http://dx.doi.org/10.1155/2018/9429863.

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The noise characteristics of multichannel systems of forming signals based on hybrid frequency synthesizers with automatic compensation of phase distortions of direct digital synthesizers, which are used in the composition of georadars with synthesized aperture, are investigated. It is established that the phase noise of the output signals of the formers at the 1 kHz detuning from the carrier oscillation at the output frequencies of the devices in the range from 500 to 3500 MHz is characterized by a level of minus 100 - minus 130 dB. In this case, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a reference oscillator of a phase locked loop is characterized by the worst noise characteristics but with the highest degree of autocompensation (about 13 dB). Conversely, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a support generator of the phase-locked loop has the best phase noises level from the considered variants of devices and least degree of autocompensation (about 6 dB).
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Ryabov, I. V., I. V. Strelnikov, P. M. Yuriev, and N. V. Degtyarev. "A Direct Digital Synthesizer of Complex Signals." Instruments and Experimental Techniques 61, no. 6 (November 2018): 788–95. http://dx.doi.org/10.1134/s0020441218050238.

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Nakagawa, T., and H. Nosaka. "A direct digital synthesizer with interpolation circuits." IEEE Journal of Solid-State Circuits 32, no. 5 (May 1997): 766–70. http://dx.doi.org/10.1109/4.568849.

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Yang, Hui Jing, and Fan Yu. "FPGA Implementation of Direct Digital Frequency Synthesizer." Applied Mechanics and Materials 380-384 (August 2013): 3312–15. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3312.

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Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.
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Prakash, B., K. Hariharan, and V. Vaithiyanathan. "An optimized direct digital frequency synthesizer (DDFS)." Contemporary Engineering Sciences 7 (2014): 427–33. http://dx.doi.org/10.12988/ces.2014.4326.

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Liu, Cai Hong, Jin Shui Ji, Ai Qin Qi, and Wei Zhang. "Design of Direct Digital Synthesizer Based on FPGA." Advanced Materials Research 748 (August 2013): 829–32. http://dx.doi.org/10.4028/www.scientific.net/amr.748.829.

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Traditional designs of high bandwidth frequency synthesizers employ the use of a phase locked-loop. A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. The thesis emphasizing discusses the designing of DDS basing on FPGA. DDS is made up of the phrase accumulator and sine ROM looking-up table, which is realized by functional EAB chip. And through setting different initial accumulator value and initial phrase value, the difference of phrase between the two sine signals can be changed. As a result, two serials of sine signals with changeable digital frequency, phrase and magnitude are produced. The simulate results show that logic in FPGA is consistent with the requirements.
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Dissertations / Theses on the topic "Direct Digital Synthesizer"

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Yu, Xuefeng Dai Fa. "High speed ROM-less direct digital frequency synthesizer." Auburn, Ala, 2009. http://hdl.handle.net/10415/1863.

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Finateu, Thomas. "A direct digital retransmitter based on phase-interpolar direct digital synthesizer and injection locking." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13671/document.

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Cette thèse présente un émetteur radio-fréquences, composé d’un synthétiseur numérique de fréquences, lui-même construit autour d’un sigma delta et d’un interpolateur de phase, ainsi que d’un oscillateur verrouillé par injection. Le synthétiseur numérique direct génère des fréquences de 400 à 500 MHz avec une résolution fréquentielle d’au moins 60 Hz. L’oscillateur verrouillé par injection, quand à lui, transpose ces fréquences dans la bande Bluetooth en assurant une multiplication de fréquences par 5. De plus, l’oscillateur verrouillé filtre le bruit de phase du signal d’injection jusqu’à récupérer celui de l’oscillateur libre. La bande passante de l’oscillateur verrouillé par injection peut être programmée numériquement. Cet émetteur a été développée dans une technologie CMOS 65 nm
This Ph.D dissertation presents a radio-frequency transmitter, made of a direct digital frequency synthesizer, built around a sigma delta and a phase interpolator, and an injection locked oscillator. The direct digital synthesizer generates frequencies between 400 and 500 MHz with a frequency resolution better than 60 Hz. On the other hand, the injection locked oscillator up-converts synthesizer output up to the Bluetooth band by multiplying frequencies by 5. Moreover, the locked oscillator filters injected signal phase noise up to recover the one of the free running oscillator. The locked oscillator bandwidth can be tuned digitally. This transmitter has been developed on 65-nm CMOS technology
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Chimakurthy, Lakshmi Sri Jyothi Dai Foster. "Design of direct digital frequency synthesizer for wireless applications." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/CHIMAKURTHY_LAKSHMI_54.pdf.

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Nguyen, Tri Trong. "DIRECT DIGITAL FREQUENCY SYNTHESIZER ARCHITECTURE FOR WIRELESS COMMUNICATION IN 90 NM CMOS TECHNOLOGY." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1301763225.

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Pothuri, Aditya R. "Design of Pulse Output Direct Digital Synthesizer with an Analog Filter Bank." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1215482245.

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Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by

generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.

At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.

Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.

Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.

HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.

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Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.
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Manandhar, Sanjeev. "High Speed ROM for Direct Digital Synthesizer Applications in Indium Phosphide DHBT Technology." Fogler Library, University of Maine, 2006. http://www.library.umaine.edu/theses/pdf/ManandharSX2006.pdf.

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Gerald, Matthew R. "DIRECT DIGITAL FREQUENCY SYNTHESIZER IMPLEMENTATION USING A HIGH SPEED ROM ALTERNATIVE IN IBM 0.13u TECHNOLOGY." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1154850215.

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Ghosh, Malinky Dai Foster. "A novel ROM compression technique and a high speed sigma-delta modulator design for direct digital synthesizer." Auburn, Ala., 2006. http://hdl.handle.net/10415/1312.

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Books on the topic "Direct Digital Synthesizer"

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Vankka, Jouko, and Kari Halonen. Direct Digital Synthesizers. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2.

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Vankka, Jouko. Direct digital synthesizers: Theory, design and applications. Espoo: Helsinki University of Technology, 2000.

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I, Halonen K. A., ed. Direct digital synthesizers: Theory, design, and applications. Boston: Kluwer Academic Publishers, 2001.

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Vankka, Jouko. Direct Digital Synthesizers: Theory, Design and Applications. Boston, MA: Springer US, 2001.

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Forte, Anton. Design, analysis and assessment of an HF direct digital synthesiser. [s.l: The Author], 1994.

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1923-, Kroupa Venceslav F., ed. Direct digital frequency synthesizers. New York: Institute of Electrical and Electronics Engineers, 1999.

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Kroupa, Věnceslav F. Direct Digital Frequency Synthesizers. Wiley-IEEE Press, 1998.

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Kroupa, Venceslav F. Direct Digital Frequency Synthesizers. IEEE, 1998. http://dx.doi.org/10.1109/9780470544396.

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Vankka, Jouko, and Kari A. I. Halonen. Direct Digital Synthesizers: Theory, Design and Applications (The Springer International Series in Engineering and Computer Science). Springer, 2001.

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Book chapters on the topic "Direct Digital Synthesizer"

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Vankka, Jouko, and Kari Halonen. "Direct Digital Synthesizer." In Direct Digital Synthesizers, 8–17. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_2.

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Vankka, Jouko, and Kari Halonen. "Indirect Digital Synthesizer." In Direct Digital Synthesizers, 18–22. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_3.

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Vankka, Jouko, and Kari Halonen. "Blocks of Direct Digital Synthesizer." In Direct Digital Synthesizers, 48–62. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_6.

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Vankka, Jouko, and Kari Halonen. "CMOS Quadrature IF Frequency Synthesizer/Modulator." In Direct Digital Synthesizers, 101–14. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_10.

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Vankka, Jouko, and Kari Halonen. "Spur Reduction Techniques in Sine Output Direct Digital Synthesizer." In Direct Digital Synthesizers, 63–78. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_7.

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Vankka, Jouko, and Kari Halonen. "Direct Digital Synthesizer with an On-Chip D/A-Converter." In Direct Digital Synthesizers, 87–100. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3395-2_9.

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Prasad, N., Manas Ranjan Tripathy, Ansuman DiptiSankar Das, Nihar Ranjan Behera, and Ayaskanta Swain. "Efficient VLSI Implementation of CORDIC-Based Direct Digital Synthesizer." In Advances in Intelligent Systems and Computing, 597–603. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2012-1_64.

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Wozniak, Robert, and Les Sabel. "Avoiding Phase Accumulator Truncation in a Direct Digital Frequency Synthesizer." In Digital Signal Processing for Communication Systems, 297–305. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6119-4_33.

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Tung, Desmond, and Rosmiwati Mohd-Mokhtar. "Direct Digital Synthesizer Based Clock Source for ADC Sampled System." In Lecture Notes in Electrical Engineering, 435–45. Singapore: Springer Singapore, 2014. http://dx.doi.org/10.1007/978-981-4585-42-2_50.

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Castro, Cristhian, and Mireya Zapata. "Efficient FPGA Implementation of Direct Digital Synthesizer and Digital Up-Converter for Broadband Multicarrier Transmitter." In Advances in Intelligent Systems and Computing, 414–21. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-51328-3_57.

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Conference papers on the topic "Direct Digital Synthesizer"

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Chaiel, Hussain K., Mohammad H. Ali, and M. Al-Shamary Saad. "Fast direct digital synthesizer." In 2006 IEEE GCC Conference. IEEE, 2006. http://dx.doi.org/10.1109/ieeegcc.2006.5686238.

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Heredia, Francisco, Cuauhtemoc Carbajal, and Sergio Martinez. "Direct Digital-Frequency Synthesizer for Dielectrophoresis." In 2008 Electronics, Robotics and Automotive Mechanics Conference (CERMA). IEEE, 2008. http://dx.doi.org/10.1109/cerma.2008.58.

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Saber, M. saber, M. Elmasry, and M. eldin Abo-Elsoud. "Quadrature Direct Digital Frequency Synthesizer Using FPGA." In 2006 International Conference on Computer Engineering and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icces.2006.320418.

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Lai Lin-hui, Li Xiao-jin, and Lai Zong-sheng. "A low-complexity direct digital frequency synthesizer." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734868.

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McCune, Earl. "Direct digital frequency synthesizer with designable stepsize." In 2010 IEEE Radio and Wireless Symposium (RWS). IEEE, 2010. http://dx.doi.org/10.1109/rws.2010.5434125.

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Ryabov, I. V., S. V. Tolmachev, and P. M. Yuriev. "DIRECT DIGITAL SYNTHESIZER WITH FAST FREQUENCY TUNING." In 2018 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO). IEEE, 2018. http://dx.doi.org/10.1109/synchroinfo.2018.8456988.

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Sharma, Anita, and Daruwala R.D. "Direct Digital (Sinusoidal) Synthesizer using CORDIC Algorithm." In International Conference on Computer Applications — Computer Applications - I. Singapore: Research Publishing Services, 2010. http://dx.doi.org/10.3850/978-981-08-7618-0_1473.

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Moran, David, and Javier Menoyo. "Novel Direct Digital Synthesizer Design for OFDM Digital Receivers." In 2006 European Conference on Wireless Technologies. IEEE, 2006. http://dx.doi.org/10.1109/ecwt.2006.280426.

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Omran, Hesham, Khaled Sharaf, and Magdy Ibrahim. "An all-digital direct digital synthesizer fully implemented on FPGA." In 2009 4th International Design and Test Workshop (IDT). IEEE, 2009. http://dx.doi.org/10.1109/idt.2009.5404133.

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Zhanfeng, Zhao, Zhou Zhiquan, and Qiao Xiaolin. "Novel Method for Quadrature Direct Digital Frequency Synthesizer." In 2006 CIE International Conference on Radar. IEEE, 2006. http://dx.doi.org/10.1109/icr.2006.343244.

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Reports on the topic "Direct Digital Synthesizer"

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Pei, Alex. Numerically Controlled Phase Locked Loop Using Direct Digital Synthesizer. Office of Scientific and Technical Information (OSTI), April 1993. http://dx.doi.org/10.2172/1119180.

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