Dissertations / Theses on the topic 'Direct Digital Synthesizer'
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Yu, Xuefeng Dai Fa. "High speed ROM-less direct digital frequency synthesizer." Auburn, Ala, 2009. http://hdl.handle.net/10415/1863.
Full textFinateu, Thomas. "A direct digital retransmitter based on phase-interpolar direct digital synthesizer and injection locking." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13671/document.
Full textThis Ph.D dissertation presents a radio-frequency transmitter, made of a direct digital frequency synthesizer, built around a sigma delta and a phase interpolator, and an injection locked oscillator. The direct digital synthesizer generates frequencies between 400 and 500 MHz with a frequency resolution better than 60 Hz. On the other hand, the injection locked oscillator up-converts synthesizer output up to the Bluetooth band by multiplying frequencies by 5. Moreover, the locked oscillator filters injected signal phase noise up to recover the one of the free running oscillator. The locked oscillator bandwidth can be tuned digitally. This transmitter has been developed on 65-nm CMOS technology
Chimakurthy, Lakshmi Sri Jyothi Dai Foster. "Design of direct digital frequency synthesizer for wireless applications." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/CHIMAKURTHY_LAKSHMI_54.pdf.
Full textNguyen, Tri Trong. "DIRECT DIGITAL FREQUENCY SYNTHESIZER ARCHITECTURE FOR WIRELESS COMMUNICATION IN 90 NM CMOS TECHNOLOGY." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1301763225.
Full textPothuri, Aditya R. "Design of Pulse Output Direct Digital Synthesizer with an Analog Filter Bank." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1215482245.
Full textMajid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.
Full textDirect Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by
generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.
At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.
Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.
Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.
HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.
Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.
Full textManandhar, Sanjeev. "High Speed ROM for Direct Digital Synthesizer Applications in Indium Phosphide DHBT Technology." Fogler Library, University of Maine, 2006. http://www.library.umaine.edu/theses/pdf/ManandharSX2006.pdf.
Full textGerald, Matthew R. "DIRECT DIGITAL FREQUENCY SYNTHESIZER IMPLEMENTATION USING A HIGH SPEED ROM ALTERNATIVE IN IBM 0.13u TECHNOLOGY." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1154850215.
Full textGhosh, Malinky Dai Foster. "A novel ROM compression technique and a high speed sigma-delta modulator design for direct digital synthesizer." Auburn, Ala., 2006. http://hdl.handle.net/10415/1312.
Full textHu, Anqiao. "Multi-modulus divider in fractional-N frequency synthesizer for direct conversion DVB-H receiver." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1196105249.
Full textKilic, Argun. "Implementation Of A Digital Signal Synthesizer With High Spurious Free Dynamic Range." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/3/12607406/index.pdf.
Full text#8217
s analog modulators and upconverters are inadequate to synthesize and modulate signals with high &
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Spurious Free Dynamic Range&
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(SFDR). Thus, the main objective of this thesis is to design and implement a &
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Digital Signal Synthesizer&
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(DSS) that is capable of synthesizing signals between 50-100 MHz with 60dB SFDR and to modulate them variable symbol rates and modulation techniques with very high phase/frequency resolution and switching speed while keeping the amplitude modulation occurring during a modulated symbol duration as small as possible. In this thesis, digital words of the desired signals are first synthesized in a &
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Field Programmable Gate Array&
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(FPGA) using &
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Direct Digital Synthesizer&
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(DDS) fundamentals and then converted to analog signals with a high speed &
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Digital to Analog Converter&
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(DAC). In order to attain the analog requirements, the system variables such as DAC analog performance, nonlinearities, sample and hold affects, DDS parameters, system clock, bandwidth requirements of analog filters and how they effect the output performance are studied. FPGA blocks that are capable of modulating and synthesizing desired signals are designed and programmed on a FPGA. Finally, single tone and modulated signals are synthesized with this DSS implementation and measured in order to verify this system&
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s performance and capabilities.
Dommaraju, Sunny Raj. "Design and Implementation of a 16-Bit Flexible ROM-less Direct Digital Synthesizer in FPGA and CMOS 90nm Technology." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1374351629.
Full textWeitzman, Jonathan M. "APPROACH FOR A WIDE DEVIATION RF PHASE MODULATOR on a 6U-VME-CARD." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609672.
Full textA Phase Modulator combining digital techniques with non-traditional analog circuitry can minimize the shortcomings of a traditional (purely analog) Phase Modulator. These shortcomings are: nonlinear response from input modulating signal to output modulated signal; parameters (frequency and modulation index) that are difficult to set; and the need for complex filters. The design approach discussed in this paper uses a combination of Direct Digital Synthesis (DDS) and analog devices operating in their linear range to generate a Phase Modulated RF (140 MHz) signal. A Numerically Controlled Oscillator (NCO) digitally generates the first IF yielding a very accurate, repeatable and linear signal with easily adjustable parameters such as frequency and modulation index. Linear multipliers (instead of saturated diode mixers or step recovery diodes) are used for up-conversion to RF. Using linear multipliers eases the filtering requirements due to the significantly reduced harmonics and IM (Inter-Modulation) terms. The resulting RF signal is easily translated to higher frequency bands such as L, S, C, X or K.
Shrestha, Amit [Verfasser], Viktor [Akademischer Betreuer] Krozer, Viktor [Gutachter] Krozer, and Lars [Gutachter] Hedrich. "SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization / Amit Shrestha ; Gutachter: Viktor Krozer, Lars Hedrich ; Betreuer: Viktor Krozer." Frankfurt am Main : Universitätsbibliothek Johann Christian Senckenberg, 2021. http://d-nb.info/1239729847/34.
Full textSvoboda, Josef. "Přímý číslicový frekvenční syntezátor." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217986.
Full textThuries, Stéphane. "Conception et intégration d'un synthétiseur digital direct micro-onde en technologie silicium SiGe : C 0.25um." Toulouse 3, 2006. http://www.theses.fr/2006TOU30163.
Full textDirect Digital Synthesizer (DDS) is a very versatile signal generation block, known to have many attractive characteristics among which: fast settling time, high frequency resolution, low phase noise, phase and frequency modulation capabilities, large bandwidth. . . All these features make DDS very attractive for modern microwave telecommunication systems. Although the principle of DDS has been known for many years, it did not get a dominant role in microwave communication systems due to its frequency limitation and high power consumption. A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. The DDS consists of a phase accumulator, a complementer, a digital-to-analog (D/A) converter and a bipolar differential pair. This paper discusses on the BiCMOS improvement design techniques used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop register. With this design, the power dissipation is reduced by 30 % over the usual four-levels series logic. The phase-to-amplitude conversion is completed through a bipolar differential pair instead of a ROM and/or complex computing circuit, providing significant saving in power consumption and die size. The circuit has been processed in a BiCMOS SiGe:C technology. The power consumption is 308 mW and it operates from a 2. 8 V supply
McEwan, Alistair. "Direct digital synthesis by analogue interpolation." Thesis, University of Oxford, 2004. http://ora.ox.ac.uk/objects/uuid:3def187d-5172-463c-9498-55898782f663.
Full textBuš, Ondřej. "Přímý frekvenční číslicový syntezátor s externí synchronizací." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219881.
Full textOng, Winston. "Commercial off the shelf direct digital synthesizers for digital array radar. /." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Dec%5FOng.pdf.
Full textThesis Advisor(s): David C. Jenn, Donald L. Walters. Includes bibliographical references (p. 63-64). Also available online.
Ong, Winston E. S. "Commercial off the shelf direct digital synthesizers for digital array radar." Thesis, Monterey California. Naval Postgraduate School, 2005. http://hdl.handle.net/10945/1752.
Full textZhou, Zhihe. "Non-linear D/A converters for direct digital frequency synthesizers." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Dissertations/Summer2006/z%5Fzhou%5F060606.pdf.
Full textBetowski, David James. "Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Fall2004/d%5Fbetowski%5F111104.pdf.
Full textMohieldin, Ahmed Nader. "High performance continuous-time filters for information transfer systems." Texas A&M University, 2003. http://hdl.handle.net/1969/233.
Full textTurner, Steven Eugene. "High-Speed Digital and Mixed-Signal Components for X– and KU–Band Direct Digital Synthesizers in Indium Phosphide DHBT Technology." Fogler Library, University of Maine, 2006. http://www.library.umaine.edu/theses/pdf/TurnerSE2006.pdf.
Full textYang, Dayu Dai Foster. "Frequency syntheses with delta-sigma modulations and their applications for mixed signal testing." Auburn, Ala., 2006. http://hdl.handle.net/10415/1294.
Full textMaréchal, Baptiste. "Microsystèmes inertiels vibrants pour applications spatiales : apport des fonctions numériques." Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT265/document.
Full textOnera has been developing vibrating inertial MEMS sensors with performances good enough for space uses. Associated conventional analog electronics are not limiting the physical performances of the sensors. They are, however, bulky, not reconfigurable, and do not deliver digital measurements to the on-board computer. Furthermore, when used for space applications, they have to cope with dependency and obsolescence requiring a new qualification when any part is changed.This thesis offers a new digital generic architecture with as few analog parts as possible. Work has been focused on two sensors developed by Onera: the VIA, a vibrating beam accelerometer, and the VIG, a Coriolis vibrating gyro, but can address other sensors. A first digital function identified is event timestamping for frequency and phase measurements; a second key function is the direct digital synthesis of the oscillating sensors driving signal; the third one generates pure sine signals from binary sequences output from the digital platform. These function are implemented as peripherals of an embedded processor on a FPGA.This dissertation firstly reminds physical laws and technologies of inertial measurements, followed by a quick review of oscillators, analog and digital, in order to introduce the chosen digital architecture. A following chapter studies the theory of the digital functions considered and identifies their performances. Afterwards, realisations and first experimental results are exposed, at a function level first, at a global level then, with the sensor and the embedded software to provide real inertial readings. The results gathered boost the idea of deploying digital electronics in future sensor releases
Shan, Cheng Hen, and 鄭恒杉. "Application Of Direct Digital Frequency Synthesizer In Digital Modulator." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/24733856920890506538.
Full text國立交通大學
電機資訊學院碩士在職專班
92
Abstract In this thesis, we propose a digital modulator with FSK, DFSK, BPSK and QPSK function by using direct digital frequency synthesizer (DDFS). For DDFS, the spur item were caused by finite output word length, phase truncation and sine/cosine mapping function (SCMF) are also presented. The initial guess and error correct ROM table are used to approximate the sine function, Initial guesses techniques using 2-segment line approximation. In order to reduce the ROM size, the ROM memory was partitioned into two ROM blocks. Coarse ROM (384 bits) and fine ROM (192 bits) were explored. The total size of ROM table is 576 bits. Only adder circuits were required in the additional circuits. No subtractor and multiplier were needed. Simulation shows that the worst case of SFDR (spurious free dynamic range) is 61dBC for various output frequency. When we compared with other same spec DDFS, Rom table size and additional circuits are smallest, but under sacrificing the performance of SFDR. The proposed DDFS is used to implement the digital modulator with FSK, DFSK, BPSK and QPSK function; the digital modulator is also with sine/cosine output. Using Synplify Pro to synthesize the verilog code and Altera device EPF10K100ARC240-1 to verify the function of digital modulator; it share the 238 logic elements (4%) and 1152 bits (2%) memory with device.
Liu, De-Ji, and 劉得吉. "Research of the Direct Digital Frequency Synthesizer." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87019725345958488740.
Full text國立彰化師範大學
積體電路設計研究所
96
This paper proposed that realizes ROM-less direct digital frequency synthesizer (DDFS) to utilize based on trigonometric formula, and using dynamic feedback circuit to reduce the errors. This proposed DDFS consists of two adders、two multipliers and dynamic correction circuit to generation quadrature outputs, so it can effective reduce the occupied chip area, the power consume and the cost. The present paper simulation results maximum of errors is about 0.0146 by using Matlab, and Spurious Free Dynamic Range (SFDR) is about 100db, the maximum clock frequency around at 50MHz. Now architecture with conventions of direct digital frequency synthesizer to compare, the errors to improve is about 27.4%.
Liu, Chiun-An J., and 劉鈞安. "Investigation of Direct Digital Synthesizer System Prototype." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/02589185426938988910.
Full text國立交通大學
電信研究所
83
The direct digital synthesizer(DDS),presented in the thesis ,is a new type of controllable rapid hopping machine. Using the sampling theorem in digital signal processing and the realizable techniques of digital integrated circuit such as FPGA,TTL,it may be the fast hopping frequency machine in the world.It had the advantage over the conventional phase lock loop synthesizer because in frequency response the transient time of the new machine is mach smaller than 1usec compared with that of conventional one 1msec. And the phase of the new machine is continuous in frequency exchange.Ano- ther advantage is the theoretic frequency resolution can be reduced to mHz and below. So it can nearly generate adjusta- ble unlimited frequency band.
魏維瑩. "A direct digital frequency synthesizer using mixed polynomials." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/70677530550957851828.
Full text中華大學
電機工程學系(所)
97
There are two categories of frequency synthesizer: 1) The Phase-Locked Loop (PLL) 2) The Direct Digital Frequency Synthesizer (DDFS).The DDFS electric circuit has higher frequency resolution, fast time, less of frequency conversion mutually noise, and have mutually the continuous of.Because have these than lock mutually the circuit good characteristic, play very important role in the communication system of the measurement equipment and the modern in recent years.The DDFS technique is extensively applied in the signal to produce machine, radar, the system of the communication receiver up.In order to turn down hardware cost and electric circuit comlications, on the DDFS structure, we are initial what to pay attention to is the area of the hardware and the size of ROM.The present paper application take the string wave symmetrical way, did in recent years as the construction compress technique main axle, used four polynomials algorithm is: Least Square, Laguage polynomial, Chebshev polynomial, Hermite polynomial, respectively, using the mix order analysis and mix algorithms analysis synthesize the operation of a sine wave function.In this, the circuit design and the implementation of the sinusoidal signal generation with DDFS verified by Matlab and QuartusII.
Liang, Jeng-Shiun, and 梁正勳. "The Design of Direct Digital Frequency Synthesizer on FPGA." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/36850932963496959826.
Full text國立彰化師範大學
資訊工程學系
100
This paper proposed that realizes ROM-less direct digital frequency synthesizer (DDFS) to utilize based on trigonometric formula, and using dynamic feedback circuit to reduce the error rate. This proposed DDFS consists of three adders, two multipliers and two dynamic correction circuits to generation quadrature outputs. So this architecture can effectively reduce the chip area occupied, power consumption and the production cost of. The present paper simulation results maximum of error rate is about 0.0251 when FCW input at 8 by using MATLAB, and Spurious Free Dynamic Range (SFDR) is about 111db, the maximum clock frequency around at 100MHz. The proposed DDFS was implemented in TSMC 0.35um Cell-Based flow and ALTERA Cyclone EP1C6Q240C8 FPGA board. The chip layout by CIC SOC Encounter Cell-Based design flow, according to TSMC 0.35um design flow, the layout power is about 6.913mW/MHz, the layout area of core is about 0.116mm2
林瑞仁. "A direct digital frequency synthesizer using unequal piecewise methods." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/03933993531629449302.
Full textHE-PENG-ZHE and 何朋哲. "Implementation of Direct Digital Frequency Synthesizer using Dual Slope Integration." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/42978613016678124122.
Full text聖約翰科技大學
自動化及機電整合研究所
95
There exists a phase jitter problem in using the conventional DDS as a pulse or clock generator. In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the capacitance value error can be avoided and less chip size can be used in circuit implementation. Therefore, the proposed DDS can achieve a low-jitter clock output due to generating the more precise delay time. In the hardware for achieve, The structure of this page thesis adopts ”Direct Digital Frequency Synthesizer” for Dr.Chen puts forward, and use “Very High Speed ICs Hardware Description Language, VHDL” to be designed, and cooperate with some relevant analog components and achieve this DDFS structure.
Chou, Huei Ya, and 周暉雅. "The Development of Direct Digital Synthesizer based on VXI bus." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/27656233223520771716.
Full textZhou, Hui Ya, and 周暉雅. "The development of direct digital synthesizer based on VXI bus." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/08185835999590907390.
Full textChuang, Jin-San, and 莊進參. "A Direct Digital Frequency Synthesizer With Reduced Wave Form Distortion." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/04829258866483223812.
Full text國立交通大學
電子研究所
83
In many applications of electronic engineering, an extreme pure sine wave is always needed as a signal source. And the look-up table Direct Digital Frequency Synthesizer(DDFS) is the most famous structure for generating this extreme pure sine wave. But in conventional DDFS, via D/A Converter, the output signal is reconstructed to a continous sine wave in stepping way. If we use a slopping way instead of stepping way to reconstruct the sine wave, this sine wave must be more smooth. That is to say, the harmonics of the reconstructed sine wave would be reduced a lot. In this thesis, a new method that based on the conventional DDFS which would be arisen to produce a sine wave in slopping way.
Weng, Jun-Hong, and 翁峻鴻. "Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/r9m4y7.
Full text國立中興大學
電機工程學系所
99
In this thesis, we introduce the theorem of direct digital frequency synthesizer (DDFS) and the differences between the different DDFS structures, and then propose a new ROM-less DDFS using the method of Triangle-to-Sine Converter (TSC). In the proposed circuit, it not only combines the linear digital to analog converter which is often used in the convention ROM-base DDFS circuits, but also retains the advantage o from ROM-less DDFS ones. As a result, it is good at die area and power consumption than generally ROM-less DDFS. The TSC is the key point in proposed DDFS, thus we study and analyze the TSC in detail. There are five chips designed in this thesis. The first one is translinear circuits. The chip is implemented in 0.18um CMOS technology with the die area 0.51×0.58mm² and the power consumption is about 19mW. The second is the same circuit the first chip implemented which is in 0.35um SiGe technology with the die area 0.66×0.62mm² and the power consumption is about 37mW. The third chip is the DDFS in 0.18um CMOS technology with the die area 0.81×0.65mm². The measured result of operation speed is up to 2GHz,and the maximum of SFDR is 49 dBc with 1GHz speed. The four is for the ultra-high DDFS in 90nm CMOS technology with the die area 0.98×1.34mm². The operation speed is up to 5GHz, and the maximum SFDR is 49 dBc with 5GHz speed. In the last work, the DDFS is implemented in 0.35um SiGe technology. The operation speed is up to 5GHz, and the maximum SFDR is 49 dBc with 5GHz speed.
Shih, Yu-Ting, and 施侑廷. "A Recursive Based VLSI Design for Direct Digital Frequency Synthesizer." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/65336891384446221935.
Full text國立雲林科技大學
電子與資訊工程研究所碩士班
91
With the advent of communication system, how to obtain a precise frequency is very important to us. So we need to design a frequency synthesizer that is capable of tuning quickly, in small frequency steps, over a wide frequency range. In this thesis, our target was to construct a fast-switching speed and high-resolution frequency synthesizer. In order to obtain a better frequency resolution, we didn’t use the traditional frequency synthesizer architecture, the PLL, and chose the direct digital synthesizer (DDS) to realize our synthesizer. In this dissertation, an efficient VLSI architecture design for direct digital frequency synthesizer algorithm is proposed based on recursive trigonometric function. It only employs two multipliers, two adders, a small ROM table, and a counter to generates16-bit cosine and sine outputs. Comparing to the existing design approaches, our architecture design has the advantages of low-cost and higher performance. In addition, both output waveforms can achieve 100dBc. The proposed architecture has been implemented in TSMC 0.35-μm 1p4m CMOS process technology. The chip layout size is 0.38μm2 and it working frequency is 70MHz with power consuming 1.63mw.
Chen, Yen-Ju, and 陳彥如. "The Implementation of Direct Digital Frequency Synthesizer Based on Trigonometric Algorithm." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/25085377213051515059.
Full text國立彰化師範大學
電機工程學系
95
With the advent of communication system, how to obtain a precise frequency is very important to us. Owing to the fine tuning and fast frequency switching of Direct Digital Frequency Synthesizers（DDFS）, it is very suitable for the strict requirement with the frequency, like communication system, instrument and etc. In this thesis, we propose a high speed, low complexity and high performance direct digital frequency synthesizer by using the trigonometric and Taylor’s expansion method for sinusoidal and cosine functions. We present the architecture by using trigonometric angle sum formula for sinusoidal and cosine functions at the same time. The proposed DDFS consists of one adder, one subtracter and two 11bit×16bit multipliers to generate quadrature outputs. Therefore the hardware complexity of the new DDFS architecture compared to the traditional ROM-Less DDFS. The proposed DDFS was implemented in TSMC 0.35-μm 2P4M cell base flow and ALTERA Stratix EP1S40F780C5 FPGA board. The architecture of the DDFS is synthesized with a Spurious-Free Dynamic Range（SFDR）of 85.2dBc in average sampling, ran up 111MHz, consumed 114.7mW at 3.3V and the power efficiency is 1.147-mW/MHz.
TSENE, SHIH-YING, and 曾世穎. "Implementation of Frequency Multiplication Generator Based on Direct Digital Frequency Synthesizer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/13499400313505140741.
Full text中華大學
電機工程學系碩士班
103
Direct digital frequency synthesizers (DDFS) with the development of communication systems have caused attention. The advantages of direct digital frequency synthesizer are accurate frequency resolution, fast frequency switching, less phase noise, and high frequency spectrum purity characteristic. We can use the size of the memory, circuit area and a fine frequency resolution to evaluate its effectiveness. Traditional frequency synthesizers are divided into DDFS and analog frequency synthesizer. However, inefficient and unable simultaneously output multiple frequencies are their shortcomings. In this thesis, we adopt a pipeline method to design DDFS. We enhance the performance of simultaneously output multiple frequencies and achieve a good high spectral purity. In this thesis, we use the Matlab 7.10.0 and ISE 13.3 synthesis softwares. The MATLAB model simulation is applied first and implemented with Verilog. Finally, the model is simulated in Modelsim6.3. The maximum spurious free dynamic signal range (SFDR) are from 81.4 dBc to 84.3 dBc.
Chou, Chih-Yuan, and 周治轅. "A Direct Digital Fractional Divider and Its Application to Frequency Synthesizer." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/85897296831347341297.
Full text國立清華大學
電機工程學系
93
A hybrid architecture is described as an alternative solution to sigma-delta fractional-N frequency synthesizer for wireless communication. A direct digital frequency synthesizer (DDFS) is wellknown as its high frequency resolution and fast settling, while a phase lock loop is more likely to be used at high frequency. This architecture takes the advantages of both synthesis method and is designed for a DCS-1800 communication system. The synthesizer is implemented primarily as a PLL. For small channel spacing and short settling time specifications, the reference frequency must be set high to acquire larger loop filter bandwidth. The fractional division is then necessary to decouple the frequency resolution and the bandwidthsettling requirements. Instead of a sigma-delta modulated multi-division divider [1] [2], DDFS serves as an direct digital fractional divider. The DDFS core is further modified by a sigma-delta modulated accumulator (SDMA) to save more power and area. Measured results from a prototype shows good match to the simulation. The key circuits were implemented on a 0.18um CMOS techonology. Hspice simulation indicates only moderate power and area are required.
Huang, Chih-Chun, and 黃值春. "Design of A High-Speed Low-Spurious Direct Digital Frequency Synthesizer." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/85753826779802663948.
Full text國立臺灣大學
電信工程學研究所
91
In this thesis, a high-speed, low spurious direct digital frequency synthesizer with quadrature sine/cosine outputs is presented. An efficient architecture based on an angle rotation algorithm (similar to CORDIC) is proposed. It shows that the architecture can be implemented as a multiplierless, feed-forward, and easily pipelineable datapath. In order to effectively achieve low spurious, a 32-bit phase accumulator, and sine and cosine outputs with 16-bit precision were chosen. The 32-bit output of the phase accumulator is truncated to 20 bits. A 20-bit internal word length in the radian converter (π/4 multiplier and iteration stages) results in an spurious-free dynamic range of greater than 100 dBc. A 32-bit frequency control word gives a tuning resolution of 0.047 Hz at a 300 MHz sampling rate. Also contained in the thesis is a review on the low-spurious digital design. Some of our simulation results are given. We found that the modified π/4 multiplier has more than 10 dB improvement in spurious-free dynamic range. The simulation results of our design are added to the thesis too, showing the algorithm is correct. In general, we have demonstrated a high-speed, low-spurious DDFS design by applying the following high-speed and low-spurious design methodologies: a high-speed accumulator, angle rotation algorithm, parallel architecture, and multiplierless iteration, which could be extended to other design and beneficial to speed and noise concerning design.
Chen, Shi-wei, and 陳世瑋. "A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54920445417497539170.
Full text國立中山大學
電機工程學系研究所
99
In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR). The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip’s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2.
Hwang, Jaw Shing, and 黃照興. "A Direct Digital Frequency Synthesizer with Sine/Cosine Output in 0.6um 1P3M." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/41057020308611913184.
Full textChen, Bo-Chen, and 陳泊辰. "THE DESIGN OF A DIRECT DIGITAL FREQUENCY SYNTHESIZER WITH FINE-TUNING CIRCUIT." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/46897351960556133495.
Full text大同大學
電機工程研究所
89
With the advent of communication system, how to obtain a precise frequency is very important to us. So we need to design a frequency synthesizer that is capable of tuning quickly, in small frequency steps, over a wide frequency range. In this thesis, our target was to construct a fast-switching speed and high-resolution frequency synthesizer. In order to obtain a better frequency resolution, we didn’t use the traditional frequency synthesizer architecture, the PLL, and chose the direct digital synthesizer (DDS) to realize our synthesizer. By using direct digital synthesizers, it makes us to achieve our design goal more easily, since it offers us a fast switching speed, high resolution (the step size of the synthesizer), small size and low power sine wave generator. In order to get a higher resolution, a fine-tuning circuit was incorporated to our design. This extra circuit makes our design have finer resolution, and won’t much increase the circuit complexity. We use the TSMC 0.35μm process to implement our design. The reference clock of this design is 50 MHz. The tuning range can reach form 0 to 25 MHz. And the frequency resolution is 50 MHz / 220 ≈ 47 Hz.
YEH, PO-CHEN, and 葉柏辰. "A High-Performance Direct Digital Frequency Synthesizer Based on Error Compensation Algorithm." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/57156821340384327307.
Full text中華大學
電機工程學系碩士班
94
With the development of communication system, how to design a frequency synthesizer that is capable of precise and stable frequency is very important to us. In this thesis, we do not use the traditional frequency synthesizer generated by PLL to obtain a better frequency resolution. We propose a new architecture of direct digital frequency synthesizer (DDFS). It has the merit of fast frequency switching speed, low utilization of memory, low complexity, low phase noise, high frequency resolution and high spectrum purity. This new DDFS is based on a novel error compensation algorithm for computing sinusoidal functions. This new algorithm accurately reduces the error of approximation function and enhances the analysis of frequency domain.The circuit of DDFS is well simulated and download to a Field Programmable Gate Array (FPGA) for verification and measurement. The highest operating frequency of this circuit is 241.6 MHz(4.139ns). The tuning range of output frequency can is form 0 to 120 MHz. The frequency resolution is only 0.056 Hz. The Spurious Free Dynamic Range (SFDR) of output spectrum is 92 dBc. And the total hardware utilization is 382 Logic Elements (LEs).
Liao, Shyuan, and 廖旋. "Design and chip implementation of a low-power direct digital frequency synthesizer." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/63946541856079663007.
Full textLIAO, XUAN, and 廖旋. "Design and Chip Implementation of A Low-Power Direct Digital Frequency Synthesizer." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/75111688906755990290.
Full textMeng-Hsueh, Lin, and 林孟學. "An Efficient Pipeline Direct Digital Frequency Synthesizer Based on a Novel Interpolation Algorithm." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/15247524862848599332.
Full text國立交通大學
電子工程系
90
In this thesis, we propose a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity. It is based on a novel interpolation algorithm for sinusoidal functions. The algorithm accurately characterizes the interpolation error. With a small lookup table of words, the DDFS successively interpolate the target value in a pipeline fashion using only N addition operations, where N is the output word length. Simulation shows that for N=16-bit example, 100dBc of SFDR (spurious free dynamic range) is achieved, with a lookup table of only 304 bits. In addition, due to its pipeline structure, the new DDFS have a very high throughput rate and a very short cycle time of about an adder delay. The new design has a smaller table size and less datapath requirement than the best known DDFS by Madisetti et al, at the same speed performance.