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Journal articles on the topic 'Direct Digital Synthesizer'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Spooner, A., Binneg Lao, D. Rowe, C. Harper, S. Schwarzbek, D. J. Durand, L. Eaton, and A. D. Smith. "Superconducting direct digital synthesizer." IEEE Transactions on Appiled Superconductivity 7, no. 2 (June 1997): 2270–73. http://dx.doi.org/10.1109/77.621691.

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2

Yih-Chyun Jenq. "Direct digital synthesizer with jittered clock." IEEE Transactions on Instrumentation and Measurement 46, no. 3 (June 1997): 653–55. http://dx.doi.org/10.1109/19.585421.

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3

Mukhanov, Oleg, Amol Inamdar, Timur Filippov, Anubhav Sahu, Saad Sarwana, and Vasili Semenov. "Superconductor Components for Direct Digital Synthesizer." IEEE Transactions on Applied Superconductivity 17, no. 2 (June 2007): 416–21. http://dx.doi.org/10.1109/tasc.2007.898055.

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4

Polikarovskykh, O. I. "DIRECT DIGITAL SYNTHESIZER IN A NEW MATHEMATICAL BASIS." Proceedings of the O.S. Popov ОNAT 1, no. 2 (December 31, 2020): 100–110. http://dx.doi.org/10.33243/2518-7139-2020-1-2-100-110.

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The principles of the construction and operation of a digital synthesizer for direct frequency synthesis with acceleration of computational operations by using a residual class system (RNS) are considered. The specifics of the implementation of the operation of direct and inverse transformations from the positional number system to the number system of the residual classes are described. A mathematical model of a synthesizer with a phase accumulator in the system of residual classes is considered. The ways of designing a digital synthesizer of direct synthesis with a phase accumulator in the RNS system and a sinusoidal DAC are considered. In traditional schemes, the conversion of residuals to the value of an analog signal occurs in several stages, where conversion to a binary system is one of the stages. This procedure degrades the speed of the RNS system, adding additional constraints and increasing the waiting time for the conversion result. Methods of converting from RNS to binary number system for basic operations are considered. A DDS design with a phase accumulator in the residual class system and a converter to an analog signal form without using a slow ROM is proposed. The problems of efficient use of the synthesizer crystal area and reduction of delays in the formation of the output signal are considered. A study of one of the main functional blocks of a direct digital frequency synthesizer, a digital-to-analog converter, has been carried out. The architecture of a direct digital frequency synthesizer with a DAC direct conversion from a non-positional number system to an analog signal is proposed. The main sources of noise generation in digital computational synthesizers of the proposed type are investigated. A mathematical model is proposed for calculating the power spectral density of phase noise, which will allow analyzing the noise characteristics in synthesizers built on the indicated principles.

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5

Kuzichkin, Oleg R., Dmitriy I. Surzhik, Gleb S. Vasiliev, Igor A. Kurilov, and Nikolai V. Dorofeev. "Analysis of Noise Characteristics of Multichannel Systems of the Formation of Signals of Georadars with Synthesized Aperture." Active and Passive Electronic Components 2018 (December 4, 2018): 1–7. http://dx.doi.org/10.1155/2018/9429863.

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The noise characteristics of multichannel systems of forming signals based on hybrid frequency synthesizers with automatic compensation of phase distortions of direct digital synthesizers, which are used in the composition of georadars with synthesized aperture, are investigated. It is established that the phase noise of the output signals of the formers at the 1 kHz detuning from the carrier oscillation at the output frequencies of the devices in the range from 500 to 3500 MHz is characterized by a level of minus 100 - minus 130 dB. In this case, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a reference oscillator of a phase locked loop is characterized by the worst noise characteristics but with the highest degree of autocompensation (about 13 dB). Conversely, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a support generator of the phase-locked loop has the best phase noises level from the considered variants of devices and least degree of autocompensation (about 6 dB).

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6

Ryabov, I. V., I. V. Strelnikov, P. M. Yuriev, and N. V. Degtyarev. "A Direct Digital Synthesizer of Complex Signals." Instruments and Experimental Techniques 61, no. 6 (November 2018): 788–95. http://dx.doi.org/10.1134/s0020441218050238.

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7

Nakagawa, T., and H. Nosaka. "A direct digital synthesizer with interpolation circuits." IEEE Journal of Solid-State Circuits 32, no. 5 (May 1997): 766–70. http://dx.doi.org/10.1109/4.568849.

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8

Yang, Hui Jing, and Fan Yu. "FPGA Implementation of Direct Digital Frequency Synthesizer." Applied Mechanics and Materials 380-384 (August 2013): 3312–15. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3312.

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Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

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9

Prakash, B., K. Hariharan, and V. Vaithiyanathan. "An optimized direct digital frequency synthesizer (DDFS)." Contemporary Engineering Sciences 7 (2014): 427–33. http://dx.doi.org/10.12988/ces.2014.4326.

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10

Liu, Cai Hong, Jin Shui Ji, Ai Qin Qi, and Wei Zhang. "Design of Direct Digital Synthesizer Based on FPGA." Advanced Materials Research 748 (August 2013): 829–32. http://dx.doi.org/10.4028/www.scientific.net/amr.748.829.

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Traditional designs of high bandwidth frequency synthesizers employ the use of a phase locked-loop. A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. The thesis emphasizing discusses the designing of DDS basing on FPGA. DDS is made up of the phrase accumulator and sine ROM looking-up table, which is realized by functional EAB chip. And through setting different initial accumulator value and initial phrase value, the difference of phrase between the two sine signals can be changed. As a result, two serials of sine signals with changeable digital frequency, phrase and magnitude are produced. The simulate results show that logic in FPGA is consistent with the requirements.

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11

Loskutov, Ilia, Ivan Shvetsov-Shilovskiy, and Dmitry Boychenko. "Testing System for Analog Devices Direct Digital Synthesizer." MATEC Web of Conferences 79 (2016): 01015. http://dx.doi.org/10.1051/matecconf/20167901015.

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12

Ryabov, I. V., S. V. Tolmachev, and D. A. Chernov. "A direct digital synthesizer of compound wideband signals." Instruments and Experimental Techniques 57, no. 4 (July 2014): 420–25. http://dx.doi.org/10.1134/s0020441214040095.

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13

O'Leary, P., and F. Maloberti. "A direct-digital synthesizer with improved spectral performance." IEEE Transactions on Communications 39, no. 7 (July 1991): 1046–48. http://dx.doi.org/10.1109/26.87209.

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14

Alsharef, A. A., M. A. Mohd Ali, and H. Sanusi. "Direct Digital Frequency Synthesizer Design and Implementation on FPGA." Research Journal of Applied Sciences 7, no. 8 (August 1, 2012): 387–90. http://dx.doi.org/10.3923/rjasci.2012.387.390.

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15

De Caro, Davide, Nicola Petra, and Antonio Giuseppe Maria Strollo. "Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation." IEEE Transactions on Circuits and Systems I: Regular Papers 58, no. 10 (October 2011): 2409–19. http://dx.doi.org/10.1109/tcsi.2011.2123730.

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16

Gutierrez-Aitken, A., J. Matsui, E. N. Kaneshiro, B. K. Oyama, D. Sawdai, A. K. Oki, and D. C. Streit. "Ultrahigh-speed direct digital synthesizer using InP DHBT technology." IEEE Journal of Solid-State Circuits 2, no. 9 (September 2002): 1115–19. http://dx.doi.org/10.1109/jssc.2002.801174.

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17

Saul, P. H., and M. S. J. Mudd. "A direct digital synthesizer with 100-MHz output capability." IEEE Journal of Solid-State Circuits 23, no. 3 (June 1988): 819–21. http://dx.doi.org/10.1109/4.323.

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18

Ko, Lu-Ting, Jwu-E. Chen, Yaw-Shih Shieh, Hsi-Chin Hsin, and Tze-Yun Sung. "Difference-Equation-Based Digital Frequency Synthesizer." Mathematical Problems in Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/784270.

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This paper presents a novel algorithm and architecture for digital frequency synthesis (DFS). It is based on a simple difference equation. Simulation results show that the proposed DFS algorithm is preferable to the conventional phase-locked-loop frequency synthesizer and the direct digital frequency synthesizer in terms of the spurious-free dynamic range (SFDR) and the peak-signal-to-noise ratio (PSNR). Specifically, the results of SFDR and PSNR are more than 186.91 dBc and 127.74 dB, respectively. Moreover, an efficient DFS architecture for VLSI implementation is also proposed, which has the advantage of saving hardware cost and power consumption.

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19

Gupta, Gaurav, and Monika Kapoor. "An Improved Analog Waveforms Generation Technique using Direct Digital Synthesizer." International Journal of Computer Applications 78, no. 5 (September 18, 2013): 17–20. http://dx.doi.org/10.5120/13484-1188.

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20

Yamagishi, A., H. Nosaka, M. Muraguchi, and T. Tsukahara. "A phase-interpolation direct digital synthesizer with an adaptive integrator." IEEE Transactions on Microwave Theory and Techniques 48, no. 6 (June 2000): 905–9. http://dx.doi.org/10.1109/22.846716.

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21

Vankka, J. "A direct digital synthesizer with a tunable error feedback structure." IEEE Transactions on Communications 45, no. 4 (April 1997): 416–20. http://dx.doi.org/10.1109/26.585916.

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22

Yang, Yuanwang, Jingye Cai, and Jose Schutt‐Aine. "A novel truncation spurs free structure of direct digital synthesizer." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 32, no. 2 (March 2013): 454–66. http://dx.doi.org/10.1108/03321641311296864.

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23

Aranda, Luis Alberto, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sanchez-Macian, and Juan Antonio Maestro. "Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications." IEEE Access 8 (2020): 83167–76. http://dx.doi.org/10.1109/access.2020.2991882.

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24

Yi, Shu-Chung. "A direct digital frequency synthesizer based on ROM free algorithm." AEU - International Journal of Electronics and Communications 64, no. 11 (November 2010): 1068–72. http://dx.doi.org/10.1016/j.aeue.2009.08.006.

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25

Itoh, Kenji, Akio Lida, and Yousuke Kanagawa. "Wideband phase-locked loop synthesizer using linear frequency variation direct digital synthesizer as reference oscillator." Electronics and Communications in Japan (Part I: Communications) 78, no. 9 (September 1995): 79–90. http://dx.doi.org/10.1002/ecja.4410780908.

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26

Polikarovskykh, Oleksiy, Lesia Karpova, Ihor Hula, and Vasyl Melnychuk. "Comparative Study of DDS with Different Types of Phase Accumulators." Inventions 4, no. 3 (July 17, 2019): 35. http://dx.doi.org/10.3390/inventions4030035.

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The paper deals with the problems of delayed transfer signals in the direct digital synthesizer (DDS) phase accumulator adders. Transfer delay is one of the factors that affect the maximum output frequency of the DDS synthesizer. The main types of adders used in DDS synthesizers are described. Separately, attention was paid to the adder with a consistent transfer of the transfer signal, adders with a transmission carry signal with a fixed block length, adders with a signal transmission delay with a variable block length, and a mathematical analysis of the origin and duration of the delay of the transfer signal in them. It was found that the use of a transfer adder with a variable length of a block in the core of a direct digital synthesizer would increase the maximum output frequency by 2.4 times compared to the adder with a parallel transfer, and by 1.43 times as compared with the adder with a fixed length the block.

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27

Pei, Xiaoshuai, Chao Meng, Minzan Li, Wei Yang, and Peng Zhou. "Measurement of soil electrical conductivity based on direct digital synthesizer (DDS) and digital oscilloscope." International Journal of Agricultural and Biological Engineering 12, no. 6 (2019): 162–68. http://dx.doi.org/10.25165/j.ijabe.20191205.4840.

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28

Pei, Xiaoshuai, Chao Meng, Minzan Li, Wei Yang, and Peng Zhou. "Measurement of soil electrical conductivity based on direct digital synthesizer (DDS) and digital oscilloscope." International Journal of Agricultural and Biological Engineering 12, no. 6 (2019): 162–68. http://dx.doi.org/10.25165/j.ijabe.20191206.4840.

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29

Ibrahim, Salah Hasan, Sawal Hamid Md Ali, and Md Shabiul Islam. "Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/131568.

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The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

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30

Omran, Qahtan Khalaf, Mohammad Tariqul Islam, Norbahiah Misran, and Mohammad Rashed Iqbal Faruque. "A ROM-Less Direct Digital Frequency Synthesizer Based on Hybrid Polynomial Approximation." Scientific World Journal 2014 (2014): 1–12. http://dx.doi.org/10.1155/2014/812576.

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In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.

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31

Jun-an, Zhang, Li Guang-jun, Zhang Rui-tao, Li Jiao-xue, Wei Ya-feng, Yan Bo, and Li Ru-zhang. "A 2.5-GHz Direct Digital Frequency Synthesizer with spurious noise cancellation." IEICE Electronics Express 11, no. 14 (2014): 20140533. http://dx.doi.org/10.1587/elex.11.20140533.

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32

Jun-an, Zhang, Li Guangjun, Zhang Ruitao, Li Jiaoxue, Wei Yafeng, and Yan Bo. "A 2.5-GHz direct digital frequency synthesizer in 0.18 μm CMOS." Analog Integrated Circuits and Signal Processing 82, no. 2 (December 30, 2014): 369–79. http://dx.doi.org/10.1007/s10470-014-0475-x.

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33

Lyles, Umar J., Tino Copani, Bertan Bakkaloglu, and Sayfe Kiaei. "An Injection-Locked Frequency-Tracking $\Sigma \Delta$ Direct Digital Frequency Synthesizer." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 5 (May 2007): 402–6. http://dx.doi.org/10.1109/tcsii.2007.892406.

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34

Jiandong Jiang and E. K. F. Lee. "A low-power segmented nonlinear DAC-based direct digital frequency synthesizer." IEEE Journal of Solid-State Circuits 37, no. 10 (October 2002): 1326–30. http://dx.doi.org/10.1109/jssc.2002.803047.

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35

Nosaka, H., Y. Yamaguchi, and M. Muraguchi. "A non-binary direct digital synthesizer with an extended phase accumulator." IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control 48, no. 1 (January 2001): 293–98. http://dx.doi.org/10.1109/58.896142.

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36

Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

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37

Vankka, J., M. Waltari, M. Kosunen, and K. A. I. Halonen. "A direct digital synthesizer with an on-chip D/A-converter." IEEE Journal of Solid-State Circuits 33, no. 2 (1998): 218–27. http://dx.doi.org/10.1109/4.658623.

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38

Kamboj, Bindiya, and Rajesh Mehra. "Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios." International Journal of Computer Applications 37, no. 10 (January 28, 2012): 25–29. http://dx.doi.org/10.5120/4645-6714.

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39

Nosaka, Hideyuki, Yo Yamaguchi, and Masahiro Muraguchi. "A Wide-Bandwidth-Output Direct Digital Synthesizer with Multiple Delay Generators." Japanese Journal of Applied Physics 39, Part 1, No. 4B (April 30, 2000): 2268–72. http://dx.doi.org/10.1143/jjap.39.2268.

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40

Jiang, Zhanpeng, Rui Xu, Hai Huang, and Changchun Dong. "Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA." International Journal of Signal Processing, Image Processing and Pattern Recognition 8, no. 5 (May 31, 2015): 327–40. http://dx.doi.org/10.14257/ijsip.2015.8.5.33.

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41

Li, Xiaojin, Linhui Lai, Ao Lei, and Zongsheng Lai. "A memory-reduced direct digital frequency synthesizer for OFDM receiver systems." IEEE Transactions on Consumer Electronics 54, no. 4 (November 2008): 1564–68. http://dx.doi.org/10.1109/tce.2008.4711202.

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42

Jinshan, Yu, Fu Dongbing, Li Ruzhang, Yao Yafeng, Yan Gang, Liu Jun, Zhang Ruitao, Yu Zhou, and Li Tun. "A direct digital frequency synthesizer with high-speed current-steering DAC." Journal of Semiconductors 30, no. 10 (October 2009): 105006. http://dx.doi.org/10.1088/1674-4926/30/10/105006.

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43

Hao, Zhikun, Qiang Zhang, Weining Ni, and Yin Shi. "A high-performance MUX-direct digital frequency synthesizer with quarter ROMs." Journal of Semiconductors 33, no. 1 (January 2012): 015008. http://dx.doi.org/10.1088/1674-4926/33/1/015008.

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44

Geng, Xueyang, Fa Foster Dai, J. David Irwin, and Richard C. Jaeger. "24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 $\mu$m SiGe BiCMOS Technology." IEEE Journal of Solid-State Circuits 45, no. 5 (May 2010): 944–54. http://dx.doi.org/10.1109/jssc.2010.2041398.

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45

Ma, Jie. "The Design and Simulation of DDS Based on Multisim and C51." Applied Mechanics and Materials 416-417 (September 2013): 1368–72. http://dx.doi.org/10.4028/www.scientific.net/amm.416-417.1368.

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In order to facilitate intuitive and understanding of the frequency synthesizer technology, research on direct digital frequency synthesizer by the phase accumulator , waveform storage ROM, the D/ Aconverter and low-pass filter modules .Multisim provides powerful virtual electronic platform, realize DDS synthetic sine wave design and circuit simulation by C51 MCU control center, while providing key code. By adjustingthe reference clock frequency fc, or to adjust the frequency control word K, can be clearly seen of the frequency of the synthesized sine wave will be changed.

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46

Romashov, Vladimir V., Kirill A. Yakimenko, Andrey N. Doktorov, and Lubov V. Romashova. "Low-noise hybrid frequency synthesizers based on direct digital and direct analog synthesis." Izmeritel`naya Tekhnika, no. 4 (April 2020): 51–56. http://dx.doi.org/10.32446/0368-1025it.2020-4-51-56.

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The research of the possibility of using hybrid frequency synthesizers based on direct digital and direct analog methods of frequency synthesis as heterodynes of modern spectrum analyzers constructed according to the superheterodyne scheme is presented. The main advantages of such synthesizers over traditionally used heterodyne schemes based on direct digital and indirect frequency synthesis methods are shown. The requirements for the heterodynes of the first mixing stages of spectrum analyzers are presented. A block diagram of a wideband heterodyne generating a frequency range from 4000 MHz to 8000 MHz with a step not exceeding 1 Hz is proposed. Formulas for calculating the main frequency ratios in the structure of the heterodyne have been developed. A mathematical model of phase noise power spectral density (PSD) depending on the offset frequency from the carrier is developed. The noise characteristics of the proposed scheme are studied using the model. It is determined that at the output frequency of the heterodyne equal to 4521,4 MHz, the level of phase noise PSD is: minus 90 dBc/Hz at the offset frequency equal to 100 Hz; minus 140 dBc/Hz at the offset frequency equal to 100 kHz. It is shown that the hybrid synthesizer based on direct digital and direct analog synthesis methods has an advantage in the level of phase noise from 5 to 30 dB over the low-noise heterodynes of modern spectrum analyzers at frequencies above 1 kHz from the carrier. Additional advantages of the proposed scheme are a simple architecture, low power consumption and high frequency tuning speed due to the absence of phaselocked loops in the structure of the heterodyne.

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47

Guo, Jian, Jie Zhu, Jiu Liu, and Li Zhou. "A Novel Method to Calculate Frequency Control Word of Direct Digital Synthesizer." Advanced Materials Research 267 (June 2011): 433–37. http://dx.doi.org/10.4028/www.scientific.net/amr.267.433.

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When designing signal generator with adjustable frequency based on direct digital synthesis technology (DDS), it is very important to calculate the frequency control word. To address the shortcoming of large computation, low efficiency of frequency setting, more storage space occupied or significant cumulative errors of frequency setting when calculating frequency control word with traditional methods, a novel calculation way for frequency control word is researched in this paper. This new method does not need large computation and more space and simultaneously it can decrease the error greatly, which plays an important role in improving the frequency setting speed and precision in signal generator.

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48

Moon, Seunghyun, Mingyu Kang, Jung-Hwan Kim, Kyeo-Reh Park, and ChaeHo Shin. "Creation of Optimal Frequency for Electrostatic Force Microscopy Using Direct Digital Synthesizer." Applied Sciences 7, no. 7 (July 8, 2017): 704. http://dx.doi.org/10.3390/app7070704.

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49

Snehal Gaikwad, Snehal Gaikwad. "Design and Implementation of Feasible Direct Digital Synthesizer to Eliminate Manual Tweaking." IOSR journal of VLSI and Signal Processing 2, no. 4 (2013): 53–56. http://dx.doi.org/10.9790/4200-0245356.

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50

Ashrafi, Ashkan, Reza Adhami, and Aleksandar Milenkovic. "A Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 4 (April 2010): 863–72. http://dx.doi.org/10.1109/tcsi.2009.2027645.

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