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Dissertations / Theses on the topic 'Discrete Time Sigma Delta Modulation'

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Published: 4 June 2025

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Pham, Dang Kien Germain. "Conversion analogique-numérique Sigma-Delta large bande appliquée à la mesure des non-linéarités des amplificateurs de puissance." Thesis, Paris, ENST, 2013. http://www.theses.fr/2013ENST0003/document.

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Les amplificateurs de puissance, éléments constitutifs essentiels de tout système de télécommunication, vont jouer un rôle capital dans le développement des futurs systèmes de communication. Aujourd'hui l'amélioration des amplificateurs de puissance nécessite un progrès technologique au niveau du composant lui même mais doit aussi tenir compte d'une approche plus globale. En particulier, le progrès dans les traitements numériques permet aujourd'hui de corriger en amont certaines distorsions qui seront générées en aval de la chaîne de communication. La pré-distorsion numérique est une technique de correction des amplificateurs de puissance qui connaît un intérêt grandissant de par son intégration complètement numérique et par les gains en linéarité et en consommation. Cette technique nécessite une voie de retour dont un élément critique est le convertisseur analogique-numérique. Ce composant doit répondre à des contraintes de résolution, de bande passante et de linéarité élevées. Dans cette thèse, nous proposons une nouvelle architecture de convertisseur analogique-numérique à base de modulateurs Sigma-Delta passe-bande. Cette architecture tire partie du fonctionnement passe bande des modulateurs que nous faisons travailler en parallèle, chacun centré sur différentes fréquences, mais aussi d'un agencement en cascade particulier pour éliminer le signal utile, qui est de forte puissance, dans le but de diminuer les contraintes de dynamique.La conception haut niveau et les simulations ont été menées pour des systèmes à temps discret et aussi à temps continu et a nécessité le développement d'outils adaptés de simulation se basant sur la boîte à outils Delta Sigma Toolbox de Richard Schreier Power amplifiers, which are essential elements of any communication system, will play a crucial role in the development of future communication systems. Today improving power amplifiers requires technological advances at the circuit device level, but one also must consider a more global approach. In particular, advances in digital processing can now correct in the early stage of the communication chain some distortions that are generated downstream in the chain. Digital pre-distortion is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and of its gains in linearity and energy consumption. This technique requires a feedback path where the analog-to-digital converter is a critical element. This component must satisfy the constraints of high resolution , wide bandwidth, and high linearity. In this thesis, we propose a new architecture of analog-to-digital converter based on bandpass Delta-Sigma modulators. This architecture takes advantage of operating bandpass modulators that are designed to work in parallel, each focusing on different frequencies, but also of a particular cascading arrangement to eliminate the useful signal, which has a high power, in order to reduce dynamics constraints. High-level design and simulations were carried out for discrete time and continuous time systems and also required the development of appropriate simulation tools

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Nathany, Sumit Kumar. "Design of a 14-bit fully differential discrete time delta-sigma modulator /." Online version of the thesis, 2006. https://ritdml.rit.edu/dspace/handle/1850/2799.

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Pham, Dang Kien Germain. "Conversion analogique-numérique Sigma-Delta large bande appliquée à la mesure des non-linéarités des amplificateurs de puissance." Electronic Thesis or Diss., Paris, ENST, 2013. http://www.theses.fr/2013ENST0003.

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Khushk, Hasham Ahmed. "Modulateur ΣΔ passe-haut et application dans la réception multistandards". Phd thesis, Télécom ParisTech, 2009. http://pastel.archives-ouvertes.fr/pastel-00006055.

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Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

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Baltolu, Anthony. "Etude et conception analogique d’architectures d’acquisition acoustique très faible consommation pour applications mobiles." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0339/document.

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Les récentes avancées technologiques des microphones de type microsystème électromécanique (MEMS) leurs permettent une utilisation sur une large gamme d’amplitudes sonores. Leur niveau de bruit ayant baissé, il devient possible de capter des sons provenant d’une distance plus lointaine, tandis que l’augmentation de leur pression acoustique maximale leur permet de ne pas saturer dans un environnement très bruyant de type concert ou évènement sportif. Ainsi le système électronique de conversion analogique-numérique connecté au microphone devient l’élément limitant les performances du système d’acquisition acoustique. Un besoin de nouvelles architectures de conversion analogique-numérique ayant une plage dynamique augmentée se fait donc ressentir. Par ailleurs, ces microphones étant de plus en plus utilisés dans des systèmes fonctionnant sur batterie, la contrainte de limitation de la consommation devient importante.Dans la bande de fréquences audio, les convertisseurs analogiques-numériques de type sigma-delta sont les plus aptes à obtenir une grande résolution combinée à une faible consommation. Ils sont divisés en deux grandes familles: ceux à temps discret utilisant principalement des circuits à capacités commutées, et ceux à temps continu utilisant des circuits classiques. Cette thèse se concentre sur l’étude et la conception de chacun des deux types de convertisseurs sigma delta, en insistant sur la faible consommation, le faible coût de production (surface occupée) et la robustesse du circuit, cela en vue d’une production de masse pour équipements portables.La conception d’un convertisseur analogique numérique de type sigma-delta à temps discret a été réalisé, ce dernier atteignant un rapport signal sur bruit de 100 décibels sur une bande de 24kHz, pour une puissance consommée de seulement 480μW. Pour limiter la consommation, de nouveaux amplificateurs à base d’inverseurs sont utilisés, et dont la robustesse contre les variations du procédé de fabrication ou de la température a été améliorée. Les spécifications ont été définies grâce au développement d’un modèle de haut-niveau précis, ce qui permet d’éviter le surdimensionnement tout en atteignant les performances voulues. Enfin, un grand ratio de suréchantillonnage a été choisi afin de réduire l’espace utilisé par les capacités commutées, minimisant le coût de fabrication.Après une étude théorique de l’équivalence entre les modulateurs sigma-delta à temps discret et à temps continu, ainsi que des spécificités propres aux modulateurs à temps continu, une réalisation de ces derniers a été effectuée. Celui-ci atteint un rapport signal sur bruit de 95 décibels sur une bande de fréquence de 24kHz, tout en consommant 142μW. Pour réduire la consommation ainsi que l’espace utilisé, un filtre de boucle du second-ordre a été réalisé avec un seul amplificateur, et le quantificateur fait aussi office d’intégrateur grâce à l’utilisation d’une structure d’oscillateurs contrôlés en tension. Ce quantificateur à base d’oscillateurs est réalisé par des cellules numériques, réduisant la consommation et l’espace utilisé, mais est hautement non-linéaire. Cette non-linéarité a été prise en compte par des choix architecturaux afin de ne pas réduire les performances finales du modulateur The recent technological advances in microelectromechanical system (MEMS) microphones allow them to be used on a large sound amplitude range. Due to their lower noise level, it becomes possible to capture sound from a faraway distance, while their increased acoustic overload point gives them the ability to capture sound without saturation in a loud environment like a concert or a sport event. Thus, the electronic analog / digital conversion system connected to the microphone becomes the limiting element of the acoustic acquisition system performance. There is then a need for a new analog / digital conversion architecture which has an increased dynamic range. Furthermore, since more and more of these microphones are used in battery-powered devices, the power consumption limitation constraint becomes of high importance.In the audio frequency band, the sigma-delta analog / digital converters are the ones most able to provide a high dynamic range combined to a limited power consumption. They are split in two families: the discrete-time ones using switched-capacitors circuits and the continuous-time ones using more classical structures. This thesis concentrates on the study and the design of both of these two types of sigma-delta converters, with an emphasis on the low-power consumption, the low production cost (area occupied) and the circuit robustness, in sight of a mass production for portable devices.A discrete-time sigma-delta modulator design has been made, the latter reaching a signal to noise ratio of 100dB on a 24kHz frequency bandwidth, for a power consumption of only 480μW. To limit the power consumption, new inverter-based amplifiers are used, with an improved robustness against the variations of the fabrication process or the temperature. Amplifier specifications are obtained thanks to an accurate high-level model developed, which allows to avoid over-design while ensuring that the wanted performances are reached. Finally, a large oversampling ratio has been used to reduce the switched-capacitors area, lowering the modulator cost.After a theoretical study of the equivalence between discrete-time and continuous-time modulators, and of continuous-time modulators specificities, a design of the latter has been made too. It reaches a signal to noise ratio of 95dB on a 24kHz bandwidth, while consuming 142μW. To reduce the power consumption and the occupied area, a second-order loop filter is implemented using a single amplifier, and the quantizer uses a VCO-based structure that provides inherently an integrating stage. The VCO-based quantizer is made using digital cells, lowering the consumption and area, but is highly non-linear. This non-linearity has been handled by architectural choices to not influence the final modulator performances

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Ameri, Ali. "Time-mode reconstruction IIR filters for sigma-delta phase modulation applications." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104809.

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The design of several low-pass IIR time-mode filters for use as reconstruction filters in digital-to-time conversion (DTC) applications is proposed. Previously, such reconstruction filters were implemented using phase-locked loops. The proposed filters are constructed from a simple digital-like structure involving voltage-controlled delay units. The resulting circuits require very small silicon area and consume very little power. A first-order filter design for wideband reconstruction applications was fabricated in a 0.13 um CMOS process occupying a silicon area of 170 um x 100 um and consumes 670 uW. The results prove for the first time that the concept of time-mode filtering is feasible in a CMOS monolithic process. Another design, intended for narrowband sigma-delta phase signal generation applications, is proposed that utilizes similar building blocks but uses a filter topology that is better suited for implementations with transfer functions having low-frequency poles. High-order realizations can be constructed as a cascade of several first-order sections. Such an approach will be demonstrated in the design of a sigma-delta phase-encoding signal-generation scheme. Dans cette dissertation nous proposons plusieurs filtres IIF passe-bas qui opèrent en mode temps. Ces dispositifs sont conçus pour être utilisé comme filtres de reconstruction dans les convertisseurs numérique-temps (CNT). Dans le passé, de tels filtres ont été implémenté à partir de boucles à verrouillage de phase. Les filtres proposés dans cette thèse sont construits à partir d'une simple structure numérique impliquant des unités de retards commandés en tension. Les circuits résultant de cette approche requièrent de petites surfaces sur silicium et consomment très peu d'énergie. Un filtre du premier ordre pour les applications larges bandes a été fabriqué dans un processus CMOS 0.13 um. Le filtre occupe une surface de silicium de 170 um x 100 um et consomme 670 uW. Les résultats montrent pour la première fois que la notion de filtrage en mode temps est possible dans un processus CMOS monolithique. Un autre filtre destiné à des applications de génération de signal de phase sigma-delta à bande étroite est aussi proposé. Ce filtre utilise des blocs de construction similaire au premier mais utilise une topologie qui est mieux adapté pour les implémentations de fonctions de transfert ayant des pôles à forte valeur de Q. Les filtre d'ordre supérieur peuvent être construits en cascadant plusieurs filtres du premier ordre. Une telle approche sera démontrée par la conception d'un système de génération de signaux de phase codes en sigma-delta.

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Peev, Pavel. "An anti-aliasing filter based on continuous-time delta-sigma modulation." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86920.

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An anti-aliasing filter that incorporates a sampler is proposed. Its architecture is inspired by the anti-aliasing filtering property of continuous-time (CT) delta-sigma (DS) modulators. However, contrary to CT DS modulators, the proposed sampling anti-aliasing filter is not sensitive to clock jitter. Furthermore, its key characteristics include: 1) high suppression of aliases - for example, compared to a Butterworth filter of the same order - owing to its notches at multiples of the sampling frequency; 2) high-pass shaping of sampling errors, similar to the shaping of quantization noise in DS modulators; and 3) its alias suppression is preserved over a broad range of sampling frequencies, thereby enabling its use as a general-purpose intellectual property (IP) block. Thus, the proposed sampling anti-aliasing filter is particularly attractive at the input of noise-shaping analog-to-digital converters (ADCs), such as discrete-time (DT) DS ADCs. Its performance advantages are derived theoretically and confirmed through simulations. Un filtre anticrénelage qui incorpore un échantillonneur est proposé ci-après. Son architecture s'inspire des proprietés d'anticrénelage des modulateurs delta-sigma (DS) en temps continu (TS). Néanmoins, contrairement aux modulateurs DS TC, le filtre proposé n'est pas victime de la sensibilité au bruit d'horloge. De plus, ce filtre anticrénelage possède entre autres les qualités suivantes: 1) Réduction élevée des créneaux non désirés - en comparaison par exemple aux crénaux d'un filter Butterworth du même ordre - ceci grâce à la présence de points rejet dans le réponse du filtre aux multiples de la fréquence d'èchantillonnage; 2) Transformation passe-haut des erreurs d'échantillonnage, de façon similaire à la transfomation du bruit de quantification dans les modulateurs DS; 3) Préservation de la suppression des créneaux a travers une bande large de fréquences d'échantillonnage; ce qui en permet l'usage banalisé sous forme de block de propriété intellectuelle (PI). Ainsi, le filtre d'échantillonnage anticrénelage proposé ci-après est particulièrement adéquat à l'entrée de la transformation de bruit d'un convertisseur analogue-numérique (CAN) comme les CAN a temps discrets. La performance de ce filtre est dérivée de manière théorique et confirmée par des simulations.

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Gao, Xi. "Digital RF-over-Fiber Links Based on Continuous-Time Delta Sigma Modulation." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1579018039888542.

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Kulchycki, Scott Douglas. "Continuous-time [sigma-delta] modulation for high-resolution, broadband A/D conversion /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.

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Garcia, Julian. "Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447.

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The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative. QC 20120528

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Lota, Jaswinder. "A comprehensive design methodology for the design of discrete-time sigma-delta (Î£-Î”) modulators." Thesis, University of Westminster, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442104.

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Park, Matthew (Matthew J. ). "An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33332.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. In title on t.p., [Sigma] and [Delta] appear as the upper-case Greek letters. Includes bibliographical references (p. 87-89). This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power. by Matthew Park. M.Eng.

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Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.

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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs. QC 20150422

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Aguirre, Paulo Cesar Comassetto de. "Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/105065.

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Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

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Fakhoury, Hussein. "Conception de modulateurs Delta-Sigma passe-bas en technologie CMOS pour des applications à large bande passante et haute résolution." Electronic Thesis or Diss., Paris, ENST, 2014. http://www.theses.fr/2014ENST0088.

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Le marché des convertisseurs analogique-numérique peut être segmenté en deux catégories de circuits. Nous distinguons d’une part, les blocs de propriété intellectuelle (IP) qui sont généralement optimisés pour une application spécifique. Et d’autre part, les circuits intégrés discrets qui sont conçus pour répondre aux besoins d’une plus large gamme d’applications. Ce travail de thèse concerne la deuxième catégorie de composants. Il s’inscrit dans le cadre d'un programme de recherche et développement initié en 2010 dans le projet européen FP7 SACRA et dont le but était d'étudier la faisabilité d'un convertisseur analogique-numérique Delta-Sigma (DS) qui pourrait rivaliser avec l'architecture pipeline pour des applications nécessitant une large bande passante (≥10MHz) et une haute résolution (>10-bit) comme l’imagerie médicale, les communications numériques sans fils ou câblées, la vidéo ou encore l’instrumentation. Ce manuscrit synthétise les travaux de conception, fabrication et mesure d’un modulateur DS Passe-bas à temps continu avec une bande passante de 40MHz, et visant une résolution effective de 12-bit tout en consommant moins de 100mW The market of A/D converters can be segmented in two categories. From one side we distinguish the Intellectual Property (IP) blocks that are generally optimized for a specific application. On the other side, the general-purpose discrete Integrated Circuits (ICs) that are designed such as they could be used in different applications. This thesis work deals with the second category. It is part of a research and development program initiated in 2010 in the European project FP7 SACRA, whose purpose was to study the feasibility of a delta-sigma (DS) analog-to-digital converter that could compete with the pipeline architecture for applications that require high bandwidth (≥10MHz) and high resolution (>10-bit) such as medical imaging, wireless and wireline communications, video or instrumentation. Currently, the pipeline is still largely predominant for such applications and the few commercial wideband solutions based on a DS architecture have a signal bandwidth limited to 10 MHz or 25 MHz while consuming respectively 100mW and 20mW for an ENOB around 12-bit. This manuscript summarizes the design, fabrication and measurement of a low-pass CT DS modulator with a signal bandwidth of 40MHz, while targeting an effective resolution of 12-bit and a power consumption of less than 100mW

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Leitão, Pedro Miguel Vicente. "Design of a power output stage for a class D audio power amplifier based on an 1.5-bit ∑ ∆ M." Master's thesis, Faculdade de Ciências e Tecnologia, 2013. http://hdl.handle.net/10362/10229.

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Zeller, Sebastian [Verfasser], Robert [Gutachter] Weigel, Christian [Gutachter] Münker, and Friedel [Gutachter] Gerfers. "Wide-Bandwidth Single-Bit Continuous-Time-Sigma-Delta-Modulation for Area- and Power-Efficient A/D Conversion with Low Jitter Sensitivity / Sebastian Zeller ; Gutachter: Robert Weigel, Christian Münker, Friedel Gerfers." Erlangen : FAU University Press, 2017. http://d-nb.info/1149368713/34.

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Fakhoury, Hussein. "Conception de modulateurs Delta-Sigma passe-bas en technologie CMOS pour des applications à large bande passante et haute résolution." Thesis, Paris, ENST, 2014. http://www.theses.fr/2014ENST0088/document.

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Belkadi, Djilali. "Contribution à la modélisation et à la simulation des circuits intégrés analogiques : application aux systèmes échantillonnés et aux circuits linéaires de haute fréquence." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0062.

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Ce travail est une contribution a la modelisation et la simulation temporelle des circuits integres analogiques. Suite au besoin de la conception descendante et aux limites de la simulation electrique, la conception sur differents niveaux d'abstraction est devenue necessaire. Puisque les circuits integres analogiques sont divers, nous en avons choisi deux types : les systemes echantillonnes et les circuits lineaires de haute frequence. Dans le premier genre, une methode de simulation est proposee. Elle est basee sur la linearisation du circuit par phase d'horloge et la resolution analytique des equations differentielles. La nouveaute qu'elle porte est de rendre la simulation transitoire du bruit physique possible en utilisant la notion du bruit gele. Quant aux circuits lineaires de haute frequence, une nouvelle methode appelee cifft est proposee afin de calculer une reponse impulsionnelle causale a partir des donnees frequentielles tabulees. En concretisation de ce travail, nous avons developpe deux modules delta sigma design kit et s-model (integre dans le simulateur eldo) pour la simulation transitoire des modulateurs - de type mash et les circuits definis par des donnees frequentielles tabulees.

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Hung, Yang-Cheng, and 洪揚程. "Generalization of Discrete-Time Sigma-Delta Modulator Non-Ideality Power Models to Various Sigma-Delta Modulator Architectures." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68049481827279158962.

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碩士 國立交通大學 電控工程研究所 100 The conventional high-level ΣΔM synthesis is mainly based on behavior simulation which is very time-consuming. Thus we propose model-based high-level ΣΔM synthesis. Model-based approach can be at the order of 104 times faster than simulation-based approach. Model-based method employs only mathematical models, which is set of ΣΔM non-ideality power models. Thus, the completeness of non-ideal power models is a must when we use model-based method to design ΣΔM. In this paper, major non-ideality power models of 2nd-order ΣΔM are discussed, and generalizations of those non-ideality power models to various ΣΔM topologies are also discussed. In addition, continuous-time ΣΔM is discussed in this paper, which incorporates comparison between discrete-time, continuous-time ΣΔM and loop filter design of continuous-time ΣΔM, and continuous-time ΣΔM behavioral model in MATLAB-Simulink environment.

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Chiu, Jih-Chin, and 邱日進. "Distributed Feedback and Feedforward of Discrete-Time Sigma-Delta Modulator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12358399977956662187.

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碩士 國立中山大學 電機工程學系研究所 100 This paper presents a distributed feedback and feedforward of discrete-time delta sigma modulator applications in the radio. We know the delta-sigma modulator using oversampling and noise shaping technique, thus we can relax the specifications of the components. This paper described the architectural differences and compare, the in-band signal is less sensitive to noise interference, and improve the resolution of the circuit. In the resonator, a simple structure with a small number of capacitor in resonator circuit. This paper uses the TSMC 0.18μm process parameters to the simulation, implementation, and measurement. Our fourth-order discrete-time delta-sigma modulator specifications as follows: the input signal frequency is 10.7MHz, the sampling frequency is 42.8MHz, the signal bandwidth is 200kHz, oversampling rate is 107, and one bit quantizer.

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Yang, Dong-Sheng, and 楊東盛. "A Discrete-Time Lowpass Sigma-Delta Modulator for Voice Band Application." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/08911904882866438278.

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Chang, Shing-Yun, and 張馨云. "A Seventh-Order Low-Noise Discrete-Time Delta-Sigma Modulator for Audio Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/n82kac.

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碩士 國立交通大學 電機工程學系 107 Due to our ears’ high ability of sound distinction, the resolution demand of the audio applications is higher and higher, such as audio equipment or speech recognition. To obtain a well performed SNR, we usually use the delta-sigma modulator to implement the ADC. When the order of the system is higher, the ability of de-noise is stronger. However, it will be more unstable as the order gets higher, so most people choose the third-order system to avoid this problem. Thus, the goal of this research is to achieve a very low noise floor (in-band noise power) with a seventh-order delta-sigma modulator and still stay stable. In this thesis, the design of the seventh-order delta-sigma modulator will be presented. It is utilized as the ADC in the analog front end of MEMS microphones. The design has to be medium-low power, low frequency, high SNR, and low noise to fit the demand of hearing applications. Results show for a 24kHz signal bandwidth the ADC achieves a dynamic range of 79dB, a peak signal-to-noise and distortion ratio of 68.1dB, and a in-band noise of -90.2dBFS with an oversampling ratio of 32 (sample rate of 1.536MHz). It was fabricated in a TSMC 0.18-m CMOS process with a 2.306mm2 active area, and dissipates 7.5mW from a 1.8-V power supply.

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Wang, Sheng-Tsung, and 王聖琮. "A Discrete-Time 2-2 Sturdy-MASH Delta-Sigma Modulator with a Multi-bit Quantizer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/q76z4b.

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Li, Chia-Hsun, and 李家勛. "Design of the Forth-Order 4-bit Discrete-Time Sigma-Delta Modulator for Audio Application." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/7h888e.

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碩士 國立交通大學 電機工程學系 108 Due to the development of speech recognition systems in recent years, the demand of resolution for audio applications is getting higher and higher. To obtain a well performed SNR, we usually use the delta-sigma modulator to implement the ADC. When the order of the system is higher, the ability of noise shaping is stronger. However, the consideration of stability is very important as the order gets higher. A common solution to improve stability is to use a multi-bit quantizer. The goal of this research is to obtain the best resolution through balance between stability and circuit complexity. In this thesis, the design of the forth-order 4-bit sigma-delta modulator will be presented. It is utilized as the ADC in the analog front end of MEMS microphones. The design has to be medium-low power, low frequency, and high SNR to fit the demand of audio applications. Results show for a 24kHz signal bandwidth the ADC achieves a dynamic range of 57dB and a peak signal-to-noise and distortion ratio of 49.3dB with an oversampling ratio of 32 (sample rate of 1.536MHz). The chip was fabricated in a TSMC 0.18-m CMOS process with a 3.992mm2 active area and dissipates 7.7mW from a 3.3V/1.8V power supply.

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Wang, Tao. "Low-power high-resolution delta-sigma ADC design techniques." Thesis, 2012. http://hdl.handle.net/1957/29740.

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This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented. Graduation date: 2012 Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014

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Wu, Su-Hao, and 吳書豪. "Calibration Techniques for Discrete-Time Delta-Sigma Modulators." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/61347686737160856938.

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博士 國立交通大學 電子工程學系電子研究所 101 This thesis presents background calibration techniques to reshape the capability of noise shaping of discrete-time (DT) Delta-Sigma modulators (DSMs). The calibration can operate in the background without interrupting the normal operation of the DSM. The proposed scheme relaxes the requirement of opamp DC gain in a DT DSM. and relaxes the matching requirement in a cascaded-DSM. The opamp in a DT DSM is requested to sacrifice the DC gain for wide-band applications. This induces the issue of integrator-leakage and a degraded signal-to-noise-anddistortion ratio (SNDR). We develops an integrator-leakage calibration technique for a DT DSM. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can be used to calibrate all of the integrators in a DT DSM of any form. The developed scheme can relax the requirement of opamp DC gain in the high-speed high-resolution DT DSMs. A cascaded DSM without the perfect matching between analog loop filters and digital noise cancellation filters exhibits a degraded SNDR due to noise leakage. We develops an noise-leakage calibration technique with low-complex circuits. The noise leakage is determined by injecting an out-of-band signal, and the leakage is eliminated by merely adjusting the gain of digital filter. The developed scheme can relax the matching requirement in the cascaded DSMs and accomplish the higher-order noise shaping. A 2-2 cascaded discrete-time DSM is fabricated in a 65 nm CMOS technology. Each stage of DSM consists of two integrators realized the low gain high speed opamp. The integrator leakage originated in the first stage is reduced by integrator leakage calibration at first. Then, the mismatch between the analog loop filter and the digital noise cancellation filter is cured by noise leakage calibration. The proposed calibrations enable the modulator to perform the high-speed high-resolution analog-to-digital conversion. The active area of the fabricated DSM is 0.58x0.33 mm2. This cascaded DSM with open-loop opamp gain of 20 dB is operating at 1.1 GHz clock rate. Its OSR is 33 and its bandwidth is 16.67 MHz. The DSM consumes 94mW from 1.0 V power supply. Before activating the calibrations, the SNDR is 54 dB and the dynamic range (DR) is 60 dB. After activating the integrator leakage calibration and the noise leakage calibration, the SNDR becomes 74 dB and the DR becomes 81 dB. The figure-of-merit of the DSM is 163.5 dB.

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Lu, Cho-Ying. "Calibrated Continuous-Time Sigma-Delta Modulators." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7914.

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To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

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Fan, Kuo-Cheng, and 范國政. "Model-based Design Optimization for Discrete-Time Sigma-Delta Modulators." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/58360167040085000017.

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碩士 國立交通大學 電控工程研究所 100 Conventional high-level ΣΔM synthesis is mainly based on behavior simulation which is very time-consuming. The model-based approach can be 50000 times faster than simulation-based approaches, but it is never realized before due to the incompleteness of non-ideality models. The Recent establishment of a settling noise model and an OTA distortion model facilitates fast model-based ΣΔM designs which involve no time-consuming behavior simulations. Nonetheless, new problems associated with model-based approaches arise, notably the correlation between noises and the overload on quantizers. In this thesis, noise correlation models are derived, and a ΣΔM input magnitude estimator is proposed to avoid quantizer overload. Quantitative comparisons between model-based and simulation-based approaches are made. It is demonstrated that, compared with simulated annealing by the simulation-based method, direct search by the model-based method is much faster and reliable, and produces better results.

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CHEN, SZE-CHI, and 陳思齊. "A New High-Efficiency Continuous-Time Delta-Sigma-Modulation Boost Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/h6fda4.

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碩士 國立臺北科技大學 電子工程系 107 This thesis proposesa DC-DC converterswith a light load efficiency up to 94.5% and using a Delta-Sigma-Modulation control loop of boost converter to achieve a low electromagnetic interference.In this paper, the characteristics of noise shifting in the Delta-Sigma-Modulation technique are used to shift the noise in the high frequency, then the filter will be moved to the high frequency noise filtering. The converter can have low electromagnetic interference and can be applied to communication power supplies. The chiphas fabricated in TSMC 0.18μm CMOS 1P6M technology.The total area of the chip is 1.44 mm2 (including PADs). The converter is a new high-efficiency continuous delta-sigma modulation boost converter that usea continuous-time delta-sigma to shift the noise to high frequencies, solve the effects of output noise, and improve the static caused by the circuit at light loads. Power consumption, greatly improving light load efficiency. The input voltage is 1.2V, the output voltage is 1.8V, the transient response time is 20us, and the maximum efficiency is 94.5% when the load current is 20mA.

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Jiang, Yu-Ci, and 江玉琪. "A High-Resolution Digital-to-Time Converter Using Delta-Sigma Modulation Technique." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/39411493843504740844.

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碩士 國立雲林科技大學 電機工程系碩士班 101 Delay-Locked Loop (DLL) has been employed widely in some designs which are related to timing, for example, Clock Generator, Clock Deskewing. Delay-Locked Loop(DLL) is more applicable to Digital-to-Time Converter (DTC) because its higher stability and easier design. Digital-to-Time Converter(DTC) employs chiefly in Auto Instrumentation Automatic Test Equipment and Digital Phase Modulator. The precision of converter resolution is more and more important to satisfy the more demand of Auto Instrumentation nowadays, consequently, base on the conception of Digital-to-Time Converter, and relative to employ the circuit of interpolator, which is researching into the resolution of phase and providing the source of multiple phases in the past. In this thesis, it was proposed that we apply Delay-Locked Loop (DLL) and accede to the technique of Delta-Sigma Modulator(DSM) to the Digital-to-Time Converter(DTC). We can finish the manipulation of total system by Digital Control Word passing through Delta-Sigma Modulator (DSM) to generate the reference clock signal which can control Delay-Locked Loop(DLL). In this thesis, the test chip fabricated in a TSMC 0.18μm 1P6M process, operates from 250-350MHz. At 250MHz operation with 10-bit Digital Input Code, the unit interval was approximated as 3.9ps,and power consumption 2.8mW. By the analysis of circuit simulation, the Integral Nonlinearity(INL) and Differential Nonlinearity(DNL) are 41 LSB ~ 136 LSB are -35 LSB ~ 20 LSB respectively.

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Hsieh, I.-Hao, and 謝乙豪. "A Discrete Time Second Order Feed-Forward Delta Sigma Analog-to- Digital Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/42020924603232888583.

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碩士 國立清華大學 電機工程學系 102 Abstract(英文摘要) As technology advances, the process gradually updates, more and more circuits can be design in the same area, and the performance is getting better and better. With this scientific and technological progress, many people are willing to try to carry out large-scale system integrated in one chip design, but if they want to put the signal into a computer for analysis and processing, they must use the analog to digital converter. So analog to digital converter is the essential bridge between nature world and digital world. Due to the rapid development of medical technology, the requirement of the physiological signal measurement promote gradually. In this thesis, a sampling frequency of 10MHz, the signal bandwidth of 20kHz, and oversampling ratio (OSR) for 256 of the second-order delta-sigma analog-to digital converters, mainly used in biomedical sensing. The discrete-time system of Delta Sigma analog to digital converter is implemented by switch capacitor circuit. The affect by the clock jitter and additional delay (Excess Loop Delay) is small, but the gain bandwidth requirement of the amplifier is higher. So the high-resolution system can be designed for the low-speed application. The whole architecture includes amplifiers, comparator, analog switches ...... and so on. Add many kinds of non-ideal effects into the system to simulate like Clock Feedthrough, Clock Jitter , Finite Gain , Limited Gain bandwidth Product, Thermal noise...... and so on to formulate the amplifier specification. And then the choice of this work, Full Feed -forward low distortion structure, significantly reduces overall system amplifier specifications and the distortion of the integrator overload. This paper uses a standard TSMC 0.18um CMOS process design, and Cadence Spectre software for circuit simulation. Finally the technique of Full- Customer design implement the whole circuit. The circuit operating voltage at 1.8V, signal bandwidth 20kHz, signal to noise ratio SNR> 95dB, effective number of bits reach more than 15bits , the overall average power consumption is 3.06mW, the figure of merit (FoM) is 1.06 pJ/conv. and the total Layout area is 0.7x0.67〖 mm〗^2

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盛子恩. "Noise Correlation Model and Model-based Design Optimization for Discrete-Time Sigma-Delta Modulators." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/10838632739386322989.

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碩士 國立交通大學 電控工程研究所 99 The conventional high-level SDM synthesis is mainly based on behavior simulation which is very time-consuming. This thesis is the first one in the literature to propose model-based SDM synthesis. Model-based method can be at the order of ten thousand times faster than simulation-based method, but it is never realized before due to the incompleteness of non-ideality models. The recent establishment of settling noise model [18] and OTA distortion model [17] facilitates model-based SDM designs. Nonetheless, new problem associated with model-based method arises, notably correlation between noises. Noise correlation models here are derived. In addition, a SDM design optimization scheme is proposed, which incorporates a comprehensive power consumption model. This model-based optimization is tested against a published SDM design, achieving higher SNDR and lower power results in a much shorter design time.

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歐嘉昌. "Quantizer Overload Model and Model-based Design Optimization for Discrete-Time Sigma-Delta Modulators." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03299127213933117300.

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Kuo, Jin-Yi, and 郭駿逸. "A Discrete-time Complex Delta-Sigma A/D Converter with Time Division and Programmable Full-Scale for Wireline Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/04513214862675629324.

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碩士 國立交通大學 電信工程研究所 100 With the rapid development of communication systems, there has been more focus on analog-to-digital converter (ADC). Among all of ADCs, delta-sigma converters have better trade-off between bandwidth and accuracy. The complex delta-sigma converter is one of the band-pass delta-sigma converters in the wireless communication system to solve the issue of imaginary signal injection into signal band during down conversion. Besides, complex system can achieve better noise suppression than real counterpart since the system pole/zero need not be formed as complex-conjugate pairs. In this thesis, the design of the complex delta-sigma modulator will be presented. Its feature of the asymmetric zeros about dc is applied for wireline application. Results show for a 500-kHz signal bandwidth the ADC achieves a dynamic range of 53dB and a peak signal-to-noise and distortion ratio of 37dB with an oversampling ratio of 6 (sample rate of 6.125MHz). It was fabricated in a TSMC 0.18-μm CMOS process with a 1.87 mm2 active area, and dissipates 35.6mW from a 1.8-V power supply.

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陳英瑋. "Nonlinear Distortion, Noise and Power Analyses of Discrete-time Single-Loop Sigma-Delta ADCs for Design Optimization." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60329470480492481009.

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碩士 國立交通大學 電機與控制工程系所 94 In this work, we analyses the distortion problems resulting from the nonlinear characteristic of ADCs, including settling distortion and DAC distortion, etc. By these distortion and noise power models derived, we utilize Signal-to-Noise and Distortion Ratio (SNDR) as our design specification. Utilizing this specification and power consumption model, we can forward to do design optimization under the specific specifications. Design optimization means that under the specific specifications (signal bandwidth, SNDR), we find a set of optimal design parameters such that the power consumption of ADCs is minimum and SNDR is maximum. We use SNDR instead of SNR as our specification because SNDR is a combination of the SNR and the THD specifications and it is an overall measure of ADC dynamic performance. Finally, design optimization is tested against a published design result.

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Wang, Yan. "Design techniques for wideband low-power Delta-Sigma analog-to-digital converters." Thesis, 2009. http://hdl.handle.net/1957/13664.

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Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected. Graduation date: 2010

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Hong, Lu-Quan, and 洪祿權. "An AOT Buck Converter with Zero-Current-Detection Techniques and A New Continuous-Time Delta-Sigma-Modulation Boost Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/y9h29x.

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碩士 國立臺北科技大學 電子工程系 106 This thesis proposes two DC-DC converters. The first converter is an adaptive on-time(AOT) buck converter with zero-current-detection techniques. The ripple-based on-time controller achieves fast transient response and the zero-current-detector improves the efficiency in discontinue conduction mode (DCM). The input voltage is 3.3V, the output voltage range is from 1V to 2V. The recovery time are all 2us when the load current is changed from 100mA to 500mA and from 500mA to 100mA. The buck converter has fabricated in TSMC 0.35μm CMOS 2P4M technology. The total area of the chip is 1.46 x 1.4057 mm2. The maximum power efficiency is 89% at 200mA load current. The second converter is a new continuous-time delta-sigma-modulation boost converter. It use continuous-time delta-sigma modulator to reduce output noise. and add a fast transient circuit to allow the boost converter to have a faster transient response when the load is changed. The boost converter has fabricated in TSMC 0.35μm CMOS 2P4M technology. The total area of the chip is 1.45 x 1.47 mm2. Input voltage is 1.8V, output voltage is 3.3V, for the load current change from light load to heavy load and from heavy load to light load is 8us and 6us, respectively. The maximum power efficiency is 90% at 50mA load current.

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李孟學. "Design Optimization of Discrete-Time Single-Loop Sigma-Delta ADCs based on Analytical Models of Noises, Nonlinear Distortions, and Power Consumptions." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65159610787728720760.

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碩士 國立交通大學 電機與控制工程系所 95 The conventional sigma-delta ADC design approach is a time consuming process and needs much trials and errors. This paper analyze the mainly noise sources and nonlinear distortions. Utilizing the noise power models, nonlinear distortion power models and accurate power consumption models derived in this paper, and the assigned signal to noise and distortion ratio (SNDR) to be the design goal, we can forward to do design optimization under the specific specifications. Design optimization means that under the specific specifications (signal bandwidth, SNDR), we find a set of optimal design parameters such that the power consumption of ADCs is minimum and SNDR is maximum, and reduce the huge time-cost to set up the circuit specifications. Finally, design optimization is tested against a published design result. Although design automation issues have been partially addressed by recent behavior- simulation–based methods, yet such methods can be slower than our analytical approach far.

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Yang, Jyun, and 楊濬. "Design of A Low-EMI Delta-Sigma-Modulation Buck Converter and A Low-Voltage Adaptive-On-Time Controlled Boost Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2bnaqp.

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碩士 國立臺北科技大學 電子工程系 106 This thesis proposes a low-EMI delta-sigma modulation buck converter and a low voltage adaptive on-time controlled boost converter. The first converter is proposed to improve the drawback of the conventional PWM converter. This converter mainly utilizes the noise-shaping and oversampling theories to spread the harmonic tones in the output spectrum. The proposed delta-sigma buck converter has been fabricated with TSMC 0.35-μm 2P4M CMOS process. The output range is 1V-2.8V and input range is 3V-3.6V. When the output load range changes from 50mA to 500mA and from 500mA to 50mA, the time of transient response is 4μs and 4μs, respectively. The chip area is 1.32×1.38 mm2. The second converter is a boost converter, which is for the output of the solar battery. It will convert the lower voltage of the cell to the appropriate level for the portable product and lithium battery. It proposes the current ripple sensing and zero current detector (ZCD) circuit to improve the efficiency in the light load. The proposed boost converter has been fabricated with TSMC 0.18-μm 1P6M CMOS process. The output voltage is designed at 1.8V and the input range is from 0.5V to 1.2V. When the load current steps are from 1mA to 200mA and from 200mA to 1mA, the time of the transient response is 2μs and 1.5μs, respectively. The total chip area is 1.15×1.17 mm2.

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Gao, Min, and 高敏. "An Adaptive-On-Time Controlled Buck Converter with Pseudo-Current Sensing Techniques and A New Low-EMI Continuous-Time Delta-Sigma-Modulation Boost Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/nkny36.

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碩士 國立臺北科技大學 電子工程系 106 This paper proposes two DC-DC voltage converters. The first converter is an adaptive on-time controlled buck converter with pseudo-current sensing technology, which is a current-mode control method. The adaptive on-time control can reduce the variant of switching frequency. The pseudo-current sensing technology can accelerate the transient response of the system, simplify the circuit complexity, reduce the area of the chip and reduce the power consumption. The proposed converter has been fabricated with TSMC .035um 2P4M CMOS process and the total area of the chip is 1.3 x 1.4 〖mm〗^2. In the designed chip, the load current range is 100mA to 500mA, the operating input voltage range is 3V to 3.6V, and the output voltage range is 1V to 2.4V. The simulation show the best transient response is 3μs, and the maximum efficiency is 88.64% when the load current is 400mA. The second converter is a new low-EMI continuous-time delta-sigma boost converter which uses a voltage-mode control method. The pulse-frequency modulation technology can be used to achieve low static power consumption. The oversampling and noise-shifting can reduce the electromagnetic interference at the output. The proposed converter has been fabricated with TSMC .035um 2P4M CMOS process and the total area of the chip is 1.3 x 1.4 〖mm〗^2. In the designed chip, the load current range is 10mA to 100mA, the operating input voltage is 1.8V, and the output voltage is 3.3V. The best transient response is 5μs. The maximum efficiency is 88.2% when the load current is 60mA.

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Jung, Woo Young. "Time-based oversampled analog-to-digital converters in nano-scale integrated circuits." Thesis, 2014. http://hdl.handle.net/2152/29195.

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In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²). text

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徐基恩. "Building the power consumption model of discrete time single-loop multi-bit sigma-delta ADC and designing the circuit for ADSL-CO (central office) application." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/02642958766009751465.

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碩士 國立交通大學 電機與控制工程系所 95 In this work, we build the power consumption model of discrete time single-loop multi-bit sigma-delta ADC, and the power consumption model of discrete time single-loop multi-bit sigma-delta ADC can be divided into two parts. The one is the analog power consumption model, and the other is the digital power consumption model. The analog power consumption model includes the integrator power consumption model, the Quantizer power consumption model and the DAC power consumption model. The digital power consumption model includes the clock driver power consumption model and the switch power consumption model. We design the circuit for ADSL-CO (central office) application. And we used the discrete time single-loop single -bit sigma-delta ADC architecture to simulate.

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Frebrowski, Daniel Jordan. "Investigation of Time Domain Modulation and Switching-Mode Power Amplifiers Suitable for Digitally-Assisted Transmitters." Thesis, 2010. http://hdl.handle.net/10012/5492.

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Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

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Cho, Won Jin. "Mitigation of harmonic and inter-harmonic effects in nonlinear power converters." 2010. http://hdl.handle.net/2152/9814.

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Harmonic distortions are inevitably caused by a rectifier and an inverter due to their inherent nonlinearities. An AC-DC-AC converter, configured by the series connection of a rectifier, DC link, and an inverter, induces harmonic distortions at both AC sides and at the DC link. These harmonics can nonlinearly interact or modulate the fundamental frequencies at the AC sides to cause interharmonic distortions. Harmonic and interharmonic distortions can seriously hamper the normal operation of the power system by means of side effects such as excitation of undesirable electrical and/or mechanical resonances, misoperation of control devices, and so forth. This dissertation presents effective methodologies to mitigate harmonic and interharmonic distortions by applying dithered pulse-width modulated (PWM) signals to a voltage-sourced inverter (VSI) type adjustable speed drive (ASD). The proposed methods are also efficient because the dithering applications are performed on control signals without the need for additional devices. By the help of dithering, the rejection bandwidth of a harmonic filter can be relaxed, which enables a lower-order configuration of harmonic filters. First, this dissertation provides a dithering application on gating signals of a sinusoidal PWM (SPWM) inverter in the simulated VSI-ASD model. The dithering is implemented by adding intentional noise into the SPWM process to randomize rising and falling edges of each pulse in a PWM waveform. As a result of the randomized edges, the periodicity of each pulse is varied, which result in mitigated harmonic tones. This mitigation of PWM harmonics also reduces associated interharmonic distortions at the source side of the ASD. The spectral densities at harmonic and interharmonic frequencies are quanti fied by Fourier analysis. It demonstrates approximately up to 10 dB mitigation of harmonic and interharmonic distortions. The nonlinear relationship between the mitigated interharmonics and harmonics is confirmed by cross bicoherence analysis of source- and DC-side current signals. Second, this dissertation proposes a dithered sigma-delta modulation (SDM) technique as an alternative to the PWM method. The dithering method spreads harmonic tones of the SD M bitstream into the noise level. The noise-shaping property of SDM induces lower noise density near the fundamental frequency. The SDM bitstream is then converted into SDM waveform after zero-order interpolation by which the noise-shaping property repeats at every sampling frequency of the bitstream. The advantages of SDM are assessed by comparing harmonic densities and the number of switching events with those of SPWMs. The dithered SD M waveform bounds harmonic and noise densities below approximately -30 dB with respect to the fundamental spectral density without increasing the number of switching events. Third, this dissertation provides additional validity of the proposed method via hardware experiments. For harmonic assessment, a commercial three-phase inverter module is supplied by a DC voltage source. Simulated PWM signals are converted into voltage waveforms to control the inverter. To evaluate interharmonic distortions, the experimental configuration is extended to a VSI-ASD model by connecting a three-phase rectifier to the inverter module via a DC link. The measured voltage and current waveforms are analyzed to demonstrate coincident properties with the simulation results in mitigating harmonics and interharmonics. The experimental results also provide the efficacy of the proposed methods; the dithered SPWM method effectively mitigates the fundamental frequency harmonics and associated interharmonics, and the dithered SDM reduces harmonics with the desired noise-shaping property. text

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