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Journal articles on the topic 'Discrete Time Sigma Delta Modulation'

Author: Grafiati

Published: 4 June 2025

Last updated: 11 July 2025

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1

Lee, Kye-Shin. "Macro Model for Discrete-Time Sigma‒Delta Modulators." Electronics 11, no. 23 (2022): 3994. http://dx.doi.org/10.3390/electronics11233994.

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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2

Miranda, Igor D. dos S., and Antonio C. de C. Lima. "Impulsive Sound Detection Directly in Sigma-Delta Domain." Archives of Acoustics 42, no. 2 (2017): 255–61. http://dx.doi.org/10.1515/aoa-2017-0028.

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Abstract Recent implementations of Sigma-Delta (ΣΔ) converters have achieved low cost, low power consumption, and high integration while maintaining resolution as high as in Nyquist-rate converters. However, its usage implies demodulating the source signal delivered from ΣΔ modulation to Pulse-Code Modulation (PCM) on a pre-processing stage. This work proposes an algorithm based on Discrete Cosine Transform for impulsive signal detection to be applied directly on a modulated ΣΔ bitstream, targeting to reduce computational cost in acoustic event detection applications such as gunshot recognition systems. From pre-recorded impulsive sounds in ΣΔ format, it has been shown that the new method presents a similar error rate in comparison with traditional energy-based approaches in PCM, meanwhile, it reduces significantly the number of operations per unit time.

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3

Zhao, Feng, Hong Gao, Lin Xing, et al. "Continuous-Time Delta-Sigma Controller for DC-DC Converter." Key Engineering Materials 643 (May 2015): 53–59. http://dx.doi.org/10.4028/www.scientific.net/kem.643.53.

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This paper describes applications of a Delta-Sigma (ΔΣ) modulator to control a DC-DC converter. We propose to use a continuous-time (CT) feed-forward (FF) ΔΣ controller in a DC-DC converter and show that its transient response is faster than discrete-time (DT) and/or feedback-type (FB) ΔΣ controllers. We have also performed experiments of a DC-DC converter with a first-order continuous-time feedback ΔΣ controller and show its results.

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4

Chen, Dongliang, Liang Yin, Qiang Fu, et al. "A Straightforward Approach for Synthesizing Electromechanical Sigma-Delta MEMS Accelerometers." Sensors 20, no. 1 (2019): 91. http://dx.doi.org/10.3390/s20010091.

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The EM- Σ Δ (electromechanical sigma-delta) approach is a concise and efficient way to realize the digital interface for micro-electromechanical systems (MEMS) accelerometers. However, including a fixed MEMS element makes the synthesizing of the EM- Σ Δ loop an intricate problem. The loop parameters of EM- Σ Δ can not be directly mapped from existing electrical Σ Δ modulator, and the synthesizing problem relies an experience-dependent trail-and-error procedure. In this paper, we provide a new point of view to consider the EM- Σ Δ loop. The EM- Σ Δ loop is analyzed in detail from aspects of the signal loop, displacement modulation path and digital quantization loop. By taking a separate consideration of the signal loop and quantization noise loop, the design strategy is made clear and straightforward. On this basis, a discrete-time PID (proportional integral differential) loop compensator is introduced which enhances the in-band loop gain and suppresses the displacement modulation path, and hence, achieves better performance in system linearity and stability. A fifth-order EM- Σ Δ accelerometer system was designed and fabricated using 0.35 μ m CMOS-BCD technology. Based on proposed architecture and synthesizing procedure, the design effort was saved, and the in-band performance, linearity and stability were improved. A noise floor of 1 μ g / Hz , with a bandwidth 1 kHz and a dynamic range of 140 dB was achieved.

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5

Tao, Tao, Quanzhen Duan, and Tongjin Ge. "A Sigma-Delta Modulator with Single-Pole Double-Throw Analog Switch." Journal of Physics: Conference Series 2625, no. 1 (2023): 012047. http://dx.doi.org/10.1088/1742-6596/2625/1/012047.

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Abstract In this paper, a high precision and high energy efficiency discrete-time switching capacitive 3-order Sigma-Delta modulator (SDM) is proposed. The SDM is applied to portable electroencephalograms (EEG) because of its little energy and good performance. The energy efficiency levels of the current mainstream modulator systems are analyzed and compared, and the CIFF modulator architecture which is most conducive to realizing high energy efficiency is selected. The single-loop CIFF structure is selected to give consideration to the accuracy and stability of the circuit. The circuit is implemented in a hierarchical structure, and a single-pole double-throw (SPDT) analog switch is adopted to overcome the difficulty of opening conventional CMOS analog switches at low supply voltages and the increase in threshold voltage Vth of NMOS devices due to the base bias effect. The proposed discrete-time Sigma delta ADC modulator is designed with SMIC 0.18um CMOS technology and achieves an SNDR of 101.6dB under a 1.8V power supply voltage and a signal bandwidth of 2kHz. The power consumption is 520uW and the significant bit (ENOB) is 16.58 bits.

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6

Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares, and Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators." Sensors 22, no. 22 (2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.

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7

Kulchycki, Scott D., Roxana Trofin, Katelijn Vleugels, and Bruce A. Wooley. "A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator." IEEE Journal of Solid-State Circuits 43, no. 4 (2008): 796–804. http://dx.doi.org/10.1109/jssc.2008.917499.

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8

Cortez, Matheus, Alessandro Girardi, Lucas Severo, and Paulo De Aguirre. "Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1–10. http://dx.doi.org/10.29292/jics.v18i1.664.

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Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

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9

Chanyong Jeong, Yonghwan Kim, and Soowon Kim. "Efficient Discrete-Time Bandpass Sigma-Delta Modulator and Digital I/Q Demodulator for Multistandard Wireless Applications." IEEE Transactions on Consumer Electronics 54, no. 1 (2008): 25–32. http://dx.doi.org/10.1109/tce.2008.4470019.

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10

Lee, Song, and Roh. "A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications." Electronics 8, no. 10 (2019): 1093. http://dx.doi.org/10.3390/electronics8101093.

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This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

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11

Han, Yongchun, Wenhao Liu, Xiangwei Zhang, Xiaosong Wang, Xin Liu, and Yu Liu. "A Wide Dynamic Range Sigma-Delta Modulator for EEG Acquisition Using Randomized DWA and Dynamic-Modulated Scaling-Down Techniques." Sensors 23, no. 1 (2022): 201. http://dx.doi.org/10.3390/s23010201.

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This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180 nm CMOS technology with an area of 0.49 mm2. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized.

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12

Yoo, Mookyoung, Kyeongsik Nam, Gyuri Choi, et al. "A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer." Applied Sciences 12, no. 22 (2022): 11651. http://dx.doi.org/10.3390/app122211651.

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This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA.

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13

Jia, Yangchen, Jiangfei Guo, and Guiliang Guo. "A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer." Electronics 12, no. 2 (2023): 313. http://dx.doi.org/10.3390/electronics12020313.

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This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

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14

Ma, Song, Liyuan Liu, Tong Fang, Jian Liu, and Nanjian Wu. "A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques." IEEE Journal of Solid-State Circuits 55, no. 2 (2020): 333–43. http://dx.doi.org/10.1109/jssc.2019.2941540.

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15

Alizadeh Zanjani, Shima, Abumoslem Jannesari та Pooya Torkzadeh. "9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids". Electronics 12, № 7 (2023): 1747. http://dx.doi.org/10.3390/electronics12071747.

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In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier’s source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator’s effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively.

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Kong, Lingwei. "A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW". Journal of Sensors 2022 (16 вересня 2022): 1–9. http://dx.doi.org/10.1155/2022/9047631.

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This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

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Huang, Gongxing, Cong Wei, and Rongshan Wei. "A 90.9 dB SNDR 95.3 dB DR Audio Delta–Sigma Modulator with FIA-Assisted OTA." Sensors 24, no. 5 (2024): 1449. http://dx.doi.org/10.3390/s24051449.

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This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

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18

Chen, Dongliang, Liang Yin, Qiang Fu, Yufeng Zhang, and Xiaowei Liu. "A digital readout interface for a surface micromachined MEMS accelerometer with a novel loop compensator." Modern Physics Letters B 34, no. 27 (2020): 2050302. http://dx.doi.org/10.1142/s0217984920503029.

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This paper proposes a novel digital readout interface for capacitive MEMS accelerometer. The digitalization is fulfilled by incorporating a 1-bit [Formula: see text] (sigma-delta) modulator into the closed servo loop. It both realizes a direct digital output efficiently and linearizes the electrostatic feedback force. To maintain the stability and improve loop linearity, a discrete-time proportional integral and differential (PID) compensator is used. It improves the in-band gain, enhances quantization noise suppressing ability and maintain the high-frequency phase margin at the same time. Thus the linearity and noise performance are improved. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology. Test results show that, the linearity is better than 0.1% and the noise floor is as low as 1 [Formula: see text]g/[Formula: see text].

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19

Song, Seokjae, Jaedo Kim, and Jeongjin Roh. "100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics." IEEE Access 9 (2021): 39852–63. http://dx.doi.org/10.1109/access.2021.3064422.

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Sensors, Journal of. "Retracted: A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW". Journal of Sensors 2024 (24 січня 2024): 1. http://dx.doi.org/10.1155/2024/9839150.

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21

Hao, Xirui, Yidong Yuan, Jie Pan, et al. "An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers." Electronics 13, no. 19 (2024): 3865. http://dx.doi.org/10.3390/electronics13193865.

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Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

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22

Kwak, Yong-Sik, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, and Gil-Cho Ahn. "A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta–Sigma Modulator Using Source-Follower-Based Integrators." IEEE Journal of Solid-State Circuits 53, no. 10 (2018): 2772–82. http://dx.doi.org/10.1109/jssc.2018.2859401.

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23

Porrazzo, Serena, Alonso Morgado, David San Segundo Bello, et al. "A 155 /spl mu/W 88-dB DR Discrete-Time /spl Delta/ /spl Sigma/ Modulator for Digital Hearing Aids Exploiting a Summing SAR ADC Quantizer." IEEE Transactions on Biomedical Circuits and Systems 7, no. 5 (2013): 573–82. http://dx.doi.org/10.1109/tbcas.2013.2280694.

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24

Chen, Hongmei, Li Wang, Ting Li, Lin He та Fujiang Lin. "A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path". Journal of Circuits, Systems and Computers 26, № 07 (2017): 1750117. http://dx.doi.org/10.1142/s0218126617501171.

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This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

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Dunham, J. "Optimal Discrete-Time Delta Modulation System." IEEE Transactions on Communications 34, no. 5 (1986): 510–12. http://dx.doi.org/10.1109/tcom.1986.1096557.

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Leger, Gildas, Antonio J. Gines Arteaga, Eduardo J. Peralias Macias, and Adoración Rueda. "On Chopper Effects in Discrete-Time $\Sigma\Delta$ Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (2010): 2438–49. http://dx.doi.org/10.1109/tcsi.2010.2043996.

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Peng, Ziqiang, Cong Wei, Lijie Huang, Jinze Lai, Xiaoqiang Lu, and Rongshan Wei. "Design and optimization of discrete-time delta-sigma modulators." Microelectronics Journal 156 (February 2025): 106529. https://doi.org/10.1016/j.mejo.2024.106529.

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Nguyen, Minh Tien, Chadi Jabbour, Karim Ben Kalaia, Hanh-Phuc Le, Ngoc Nguyen, and Van-Tam Nguyen. "A Highly Flexible Passive/Active Discrete-Time Delta-Sigma Receiver." Electronics 13, no. 7 (2024): 1295. http://dx.doi.org/10.3390/electronics13071295.

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This paper presents a fourth-order discrete-time direct RF-to-digital Delta-Sigma receiver architecture for flexible receivers with a wide frequency range. The use of a current-driven passive mixer with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement of the RF amplifier. In addition, the reconfigurable passive/active loop filter offers a good compromise between power consumption, linearity, and dynamic range. The other important feature of the proposed architecture is the use of a sampling frequency that is a divisor of the LO frequency. This solves several problems such as the upmixing of quantization noise, the need to reconfigure the Delta-Sigma loop when changing the LO frequency, and the use of two independent clocks for the LO and the sampling frequency. The circuit was implemented using 65 nm CMOS technology. The I/Q Direct Delta-Sigma receiver has an RF bandwidth of 20 MHz and a sampling frequency of 400 MHz. Measurement results show a very high dynamic range of up to 80 dB with a peak SNDR of 46 dB for a power consumption of 46 mW at 800 MHz.

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29

Alwan, Nuha A. S., and Zahir M. Hussain. "Short Word-Length Entering Compressive Sensing Domain: Improved Energy Efficiency in Wireless Sensor Networks." Information 12, no. 10 (2021): 415. http://dx.doi.org/10.3390/info12100415.

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This work combines compressive sensing and short word-length techniques to achieve localization and target tracking in wireless sensor networks with energy-efficient communication between the network anchors and the fusion center. Gradient descent localization is performed using time-of-arrival (TOA) data which are indicative of the distance between anchors and the target thereby achieving range-based localization. The short word-length techniques considered are delta modulation and sigma-delta modulation. The energy efficiency is due to the reduction of the data volume transmitted from anchors to the fusion center by employing any of the two delta modulation variants with compressive sensing techniques. Delta modulation allows the transmission of one bit per TOA sample. The communication energy efficiency is increased by RⱮ, R ≥ 1, where R is the sample reduction ratio of compressive sensing, and Ɱ is the number of bits originally present in a TOA-sample word. It is found that the localization system involving sigma-delta modulation has a superior performance to that using delta-modulation or pure compressive sampling alone, in terms of both energy efficiency and localization error in the presence of TOA measurement noise and transmission noise, owing to the noise shaping property of sigma-delta modulation.

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Georgoudis, E. C., and D. Lagoyannis. "Short-time spectrum analyser based on delta-sigma modulation." IEE Proceedings G (Electronic Circuits and Systems) 133, no. 6 (1986): 295. http://dx.doi.org/10.1049/ip-g-1.1986.0051.

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Liu, Yan, Siliang Hua, Donghui Wang, and Chaohuan Hou. "A continuous-time/discrete-time mixed audio-band sigma delta ADC." Journal of Semiconductors 32, no. 1 (2011): 015004. http://dx.doi.org/10.1088/1674-4926/32/1/015004.

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Colodro, F., A. Torralba, and M. Laguna. "Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 3 (2008): 775–85. http://dx.doi.org/10.1109/tcsi.2008.919764.

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Oh, Goonseok, and Jintae Kim. "Low Power Discrete-Time Incremental Delta Sigma ADC with Passive Integrator." Journal of the Institute of Electronics and Information Engineers 54, no. 1 (2017): 26–32. http://dx.doi.org/10.5573/ieie.2017.54.1.026.

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Wu, Su-Hao, and Jieh-Tsorng Wu. "Background calibration of integrator leakage in discrete-time delta-sigma modulators." Analog Integrated Circuits and Signal Processing 81, no. 3 (2014): 645–55. http://dx.doi.org/10.1007/s10470-014-0421-y.

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Cho, Je-Kwang, and Donghyun Baek. "Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators." Analog Integrated Circuits and Signal Processing 90, no. 1 (2016): 55–63. http://dx.doi.org/10.1007/s10470-016-0855-5.

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36

Wei, Cong, Chengying Chen, Gongxing Huang, Lijie Huang, Renping Wang, and Rongshan Wei. "A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC." Microelectronics Journal 144 (February 2024): 106069. http://dx.doi.org/10.1016/j.mejo.2023.106069.

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DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

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An, Shengbiao, Shuang Xia, Yue Ma, et al. "A Low Power Sigma-Delta Modulator with Hybrid Architecture." Sensors 20, no. 18 (2020): 5309. http://dx.doi.org/10.3390/s20185309.

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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Golten, J. W., and A. A. Verwer. "SIGMA — Signal Generation Manipulation and Analysis Package." International Journal of Electrical Engineering & Education 25, no. 1 (1988): 63–76. http://dx.doi.org/10.1177/002072098802500115.

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‘SIGMA’ is a comprehensive package for the BBC microcomputer for manipulating and analysing signals in the time and frequency domains. Its ‘high-level’ language gives it great flexibility for applications involving discrete Fourier transforms and convolution. Effects such as noise, nonlinearities, modulation and quantisation are readily simulated.

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Wang, Qianqian, and Quanzhen Duan. "Low power delta sigma capacitor conversion circuit." Journal of Physics: Conference Series 2477, no. 1 (2023): 012013. http://dx.doi.org/10.1088/1742-6596/2477/1/012013.

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Abstract To accurately measure the micro capacitance, a kind of capacitance conversion circuit that uses a second-order Sigma-Delta modulation technique is introduced, and the measuring range of inductive capacitance is extended by a 4-bit DAC capacitor. The loop oscillator is used to provide the modulator with a 16 kHz square wave signal. Because the circuit has a built-in clock generation circuit, no external clock signal is required outside the chip. Chopping technology is used to reduce the impact of 1/f noise on circuit performance. This capacitance conversion circuit is based on the SMIC 0.18um process, simulated and verified with cadence, MATLAB and other tools. The circuit achieves a capacitance range from 0 to 35pF and consumes 25μA from a 1.2V single supply. The conversion time for one measurement is 15ms, during which the resolution is 4fF and good linearity is achieved.

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Wang, Yan, Pavan Kumar Hanumolu, and Gábor C. Temes. "Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay." IEEE Transactions on Circuits and Systems I: Regular Papers 58, no. 7 (2011): 1518–30. http://dx.doi.org/10.1109/tcsi.2011.2143110.

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Chopp, P. M., and A. A. Hamoui. "Analysis of Clock-Jitter Effects in Continuous-Time $\Delta \Sigma $ Modulators Using Discrete-Time Models." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 6 (2009): 1134–45. http://dx.doi.org/10.1109/tcsi.2008.2008501.

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Daniels, Jorg, Wim Dehaene, Michiel S. J. Steyaert, and Andreas Wiesbauer. "A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (2010): 2404–12. http://dx.doi.org/10.1109/tcsi.2010.2043169.

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Corey, Ryan M., and Andrew C. Singer. "Spatial sigma-delta modulation for coarsely quantized linear, circular, and spherical arrays." Journal of the Acoustical Society of America 153, no. 3_supplement (2023): A84. http://dx.doi.org/10.1121/10.0018254.

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Quantization noise shaping, also known as sigma-delta modulation, is widely used in analog-to-digital converters. Such converters oversample a signal in time, quantize it to one or a few bits of precision, and then use analog feedback to shape quantization noise outside the band of interest, producing a high-precision output. Similarly, if a sensor array is spatially oversampled so that its elements are much less than one-half wavelength apart, then quantization noise can be propagated between channels to shape its spatial distribution. A beamformer acts as a spatial filter, removing shaped quantization noise to produce a high-precision output even with coarsely quantized sensors. Spatial sigma-delta modulation has been explored primarily for radio-frequency applications using linear arrays. In this presentation, we apply spatial noise shaping to dense acoustic sensor arrays, including circular and spherical arrays. For immersive audio applications, we demonstrate how noise-shaping feedback can be used to push quantization noise into higher-order Ambisonic modes.

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Biswas, Arka, Arindam Mondal, and Prasanta Sarkar. "Design and implementation of digital controller in delta domain for buck converter." Facta universitatis - series: Electronics and Energetics 36, no. 1 (2023): 103–19. http://dx.doi.org/10.2298/fuee2301103b.

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This paper presents the design and implementation of a discrete-time controller for a DC-DC Buck converter in the complex delta domain. Whenever any continuous-time system is sampled to get a corresponding discrete-time system with a very high sampling rate, the shift operator parameterized discrete-time system fails to provide meaningful information. There is another discrete-time operator called delta operator. In the delta operator parameterized discrete-time system, the discrete-time results and continuous-time results can be obtained hand to hand, rather than in two special cases at a very high sampling rate. The superior property of the delta operator is capitalized in this paper to design the proposed controller in the discrete domain. The Proportional plus Integral (PI) controller designed in the delta domain is used to maintain the output voltage of the Buck converter at the load end for varying load and varying supply voltage conditions. The controller is designed and implemented using the DS1202 dSPACE board. The output voltage of the Buck converter is scaled to feed to the onboard analogue to digital converter of DS1202. Under the different disturbances, the error between the desired output voltage and the actual output voltage is measured and the delta PI controller is used to manipulate the duty cycle of the converter. The duty cycle of this pulse width modulation (PWM) signal is generated using a DS1202 board and is applied to the gate of the Metal Oxide Semiconductor field-effect transistor (MOSFET) via a suitable driver such that the output voltage of the Buck converter remains at its desired value.

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Khatami, Ramin, Haruo Kobayashi, and Yasunori Kobori. "Delta-Sigma Digital-to-Time Converter for Band-Select Spread Spectrum Clock." Key Engineering Materials 643 (May 2015): 79–91. http://dx.doi.org/10.4028/www.scientific.net/kem.643.79.

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This paper proposes an innovative method of converting digital signal to time-domain analog signal, which fully enjoys robustness and digital circuit friendliness. This technique utilizes a digital delta-sigma ( ) modulator following a digital-to-time converter (DTC) circuit with various modulation methods. As an application of the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as for DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noisespectrum spread in AM, FM radio bands. The proposed circuit takes advantage of digital technology, which is simple, fast (reachable at high clock frequency) and flexible (programmable).

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Takita, Hayato, Tatsuji Matsuura, Ryo Kishida, and Akira Hyogo. "Discreate-Time Second-Order Delta-Sigma A/D Modulator Improving SQNR and Suppressing Harmonic Distortions by Correlated Level Shifting Technique." IEEJ Transactions on Electronics, Information and Systems 141, no. 12 (2021): 1313–20. http://dx.doi.org/10.1541/ieejeiss.141.1313.

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Lee, Shuenn-Yuh, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, and Mark Po-Hung Lin. "Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist." Microelectronics Journal 42, no. 2 (2011): 347–57. http://dx.doi.org/10.1016/j.mejo.2010.11.004.

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49

Hamilton, Joseph, Shouli Yan, and T. R. Viswanathan. "A Discrete-Time Input $\Delta\Sigma$ ADC Architecture Using a Dual-VCO-Based Integrator." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 11 (2010): 848–52. http://dx.doi.org/10.1109/tcsii.2010.2068111.

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Pathan, Aneela, Tayab D. Memon, Rizwan Aziz, and Syed Haseeb Shah. "A novel approach toward optimized image processing using sigma delta modulation." Mehran University Research Journal of Engineering and Technology 43, no. 2 (2024): 195. http://dx.doi.org/10.22581/muet1982.3139.

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Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

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